LIBPFM(3)

πŸ“¦
version 4.14.1 Β· 2 versions
  • 4.14.1 Β· arch rolling, centos-stream 10, centos-stream 9, debian bookworm, debian trixie, fedora 43, fedora 44, nixos 26.05, nixpkgs unstable, opensuse-leap 16.0, ubuntu noble, ubuntu questing, ubuntu resolute, ubuntu stonking (latest)
  • 4.11.1+git32-gd0b85fb Β· ubuntu jammy
, in arch rolling, centos-stream 10, centos-stream 9, debian bookworm, debian trixie, fedora 43, fedora 44, nixos 26.05, nixpkgs unstable, opensuse-leap 16.0, ubuntu noble, ubuntu questing, ubuntu resolute, ubuntu stonking

🌸 LIBPFM πŸ’… β€” Linux Programmer's Manual, bestie edition πŸŽ€

okay so we're in the Linux Programmer's Manual today and the vibe is: Intel IceLakeX PMU support. sit down, hydrate, let's go ✨


✨ NAME ✨

libpfm_intel_icx β€” the whole support situation for the Intel IceLakeX core PMU 🧚


πŸ¦‹ SYNOPSIS πŸ¦‹

#include <perfmon/pfmlib.h>
  • PMU name: icx πŸ’–
  • PMU desc: Intel IceLakeX πŸ‘‘

πŸ’œ DESCRIPTION πŸ’œ

So the library is out here supporting the Intel IceLakeX core PMU. And like, important note bestie: this PMU model only covers each core's PMU, it does NOT cover the socket level PMU. don't get it twisted πŸ™ˆ

On IceLake, the number of generic counters depends on the Hyperthreading (HT) mode. so like, HT on, HT off, different counter counts, that's just how she is πŸ’…

The pfm_get_pmu_info() function returns the maximum number of generic counters in num_cntrs. that's the plug, fr fr ⭐


πŸŽ€ MODIFIERS πŸŽ€

The following modifiers are supported on Intel IceLakeX processors β€” collect them all like pokΓ©mon but they're all actually useful:

  • u β€” Measure at user level which includes privilege levels 1, 2, 3. This corresponds to PFM_PLM3. This is a boolean modifier. πŸ’–
  • k β€” Measure at kernel level which includes privilege level 0. This corresponds to PFM_PLM0. This is a boolean modifier. 🧚
  • i β€” Invert the meaning of the event. The counter will now count cycles in which the event is not occurring. This is a boolean modifier. it's giving "flip the script" πŸ”₯
  • e β€” Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier. ⚠️ no solo runs allowed bestie
  • c β€” Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255]. πŸ”’
  • ldlat β€” Pass a latency threshold to the MEM_TRANS_RETIRED:LOAD_LATENCY event. This is an integer attribute that must be in the range [1:65535]. It is required for this event. Note that the event must be used with precise sampling (PEBS). 🫢 don't skip this one, she's mandatory
  • intx β€” Monitor the event only when executing inside a transactional memory region (in tx). Event does not count otherwise. This is a boolean modifiers. Default value is 0. πŸ’€
  • intxcp β€” Do not count occurrences of the event when they are inside an aborted transactional memory region. This is a boolean modifier. Default value is 0. 🌸
  • fe_thres β€” This modifier is for the FRONTEND_RETIRED event only. It defines the period in core cycles after which the IDQ_*_BUBBLES umask counts. It acts as a threshold, i.e., at least a period of N core cycles where the frontend did not deliver X uops. It can only be used with the IDQ_*_BUBBLES umasks. If not specified, the default threshold value is 1 cycle. the valid values are in [1-4095]. πŸ‘‘

🌈 OFFCORE_RESPONSE events 🌈

Intel IceLakeX supports two encodings for offcore_response events. In the library, these are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. two of them, iconic, twins πŸ’…

Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in case multiple offcore_response events are monitored simultaneously, the operating system needs to manage the sharing of that extra register. sharing is caring but also, the OS has to do the logistics 😭

The offcore_response events are exposed as a normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. she handles it, don't worry 🫢

On Intel IceLakeX, unlike older processors, the event is treated as a regular event with a flat set of umasks to choose from. It is not possible to combine the various requests, supplier, snoop bits anymore. so that whole mix-and-match era? over. periodt πŸ’€

Therefore the library offers the list of validated combinations as per Intel's official event list. curated, approved, no cap ✨


πŸ’– AUTHORS πŸ’–

  • Stephane Eranian <eranian@gmail.com> β€” the main character, the blueprint, the moment πŸ‘‘

and that's the whole page bestie!! this one's from May, 2021, and yeah it lives under the LIBPFM(3) name in the Linux Programmer's Manual. go forth and profile responsibly πŸŽ€βœ¨πŸ’…

πŸ“¦ where this page comes from