LIBPFM(3)

✨ LIBPFM(3) ✨

okay bestie, welcome to the Linux Programmer's Manual πŸ’– you're about to read the libpfm_intel_emr page and honestly? it's giving niche but iconic. let's get into it 🫢


πŸ’… NAME πŸ’…

libpfm_intel_emr β€” support for Intel EmeraldRapid core PMU

like, that's the whole name. short. sweet. main character energy πŸ‘‘


🌸 SYNOPSIS 🌸

#include <perfmon/pfmlib.h>

PMU name: emr PMU desc: Intel EmeraldRapid

no cap, that's it. two little fields and a header include πŸŽ€


πŸ¦‹ DESCRIPTION πŸ¦‹

so the library supports the Intel EmeraldRapid core PMU. important note bestie: this PMU model only covers each core's PMU, it does NOT cover the socket level PMU. keep that straight in your head, iykyk πŸ™ˆ

On EmeraldRapid, the number of generic counters depends on the Hyperthreading (HT) mode. yes, it's giving "it depends". classic.

The pfm_get_pmu_info() function returns the maximum number of generic counters in num_cntrs. that's your go-to when you need the count πŸ’«


✨ MODIFIERS ✨

here are all the modifiers supported on Intel EmeraldRapid processors. read them all, don't skip, i'm literally watching πŸ‘€

  • u β€” measure at user level, which includes privilege levels 1, 2, 3. this corresponds to PFM_PLM3. it's a boolean modifier πŸ’–
  • k β€” measure at kernel level, which includes privilege level 0. this corresponds to PFM_PLM0. also a boolean modifier 🌸
  • i β€” invert the meaning of the event. the counter will now count cycles in which the event is not occurring. yep, another boolean modifier πŸ’…
  • e β€” enable edge detection, i.e. count only when there's a state transition from no occurrence of the event to at least one occurrence. heads up: this modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. boolean modifier πŸ¦‹
  • c β€” set the counter mask value. the mask acts as a threshold. the counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. this is an integer modifier with values in the range [0:255] ⭐
  • ldlat β€” pass a latency threshold to the MEM_TRANS_RETIRED:LOAD_LATENCY event. this is an integer attribute that must be in the range [1:65535]. it is required for this event. and note: the event must be used with precise sampling (PEBS) πŸ”₯
  • intx β€” monitor the event only when executing inside a transactional memory region (in tx). event does not count otherwise. this is a boolean modifier. default value is 0 πŸ™ˆ
  • intxcp β€” do not count occurrences of the event when they are inside an aborted transactional memory region. this is a boolean modifier. default value is 0 πŸ’€
  • fe_thres β€” this modifier is for the FRONTEND_RETIRED event only. it defines the period in core cycles after which the IDQ_*_BUBBLES umask counts. it acts as a threshold, i.e. at least a period of N core cycles where the frontend did not deliver X uops. it can only be used with the IDQ_*_BUBBLES umasks. if not specified, the default threshold value is 1 cycle. the valid values are in [1-4095] πŸ‘‘

🌈 OFFCORE_RESPONSE events 🌈

Intel EmeraldRapid supports two encodings for offcore_response events. in the library, these are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. two of them. periodt.

Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. so in case multiple offcore_response events are monitored simultaneously, the operating system needs to manage the sharing of that extra register. it's giving ✨resource management✨

The offcore_response events are exposed as normal events by the library. the extra settings are exposed as regular umasks. the library takes care of encoding the events according to the underlying kernel interface. you don't gotta do it yourself, bestie 🫢

On Intel EmeraldRapid, unlike older processors, the event is treated as a regular event with a flat set of umasks to choose from. it is not possible to combine the various requests, supplier, snoop bits anymore. so the library offers the list of validated combinations as per Intel's official event list. that's the vibe πŸ’œ


πŸŽ€ AUTHORS πŸŽ€

Stephane Eranian <eranian@gmail.com>


ok that's the whole page bestie, you ate that πŸ’… go forth and count some cycles πŸ’–

this one's from the Linux Programmer's Manual, and the source page is dated April, 2022 β€” written up as LIBPFM(3) and lovingly re-explained by your fave unix girlie ✨ bye bestie, slay πŸ¦‹