DPGEN_RF1D(3)

💖 DPGEN_RF1D 💖

okay bestie, so this page is straight out of the Alliance genlib User's Manual, and yes it's section 3 of the manual — the library-function girlies. pull up a chair, we're building register files 🎀

✨ NAME ✨

DPGEN_RF1D, DPGEN_RF1DR0 — Register File with Decoder Macro-Generator 🦋

like. it generates a register file. with a decoder. it's giving macro energy and we're obsessed 💅

🌸 SYNOPSIS 🌸

#include  <genlib.h>

void GENLIB_MACRO (DPGEN_RF1D, char *modelname, long flags, long N);

void GENLIB_MACRO (DPGEN_RF1DR0, char *modelname, long flags, long N);

💜 DESCRIPTION 💜

So what it does is generate a register file of regNumber words of N bits, with a decoder, and it's named modelname. cute, right? 😌

And listen, the DPGEN_RF1DR0 variant differs from the DPGEN_RF1D in one specific way: the register of address zero is stuck to zero. You can write into it, bestie, but it will not change the value. And when you read it, it will always return zero. that's just the deal. periodt. 💀

How it works, bestie: 👑

• datain0 and datain1 : the two write busses. Only one of them is actually used to write the register word, and which one is selected by the sel signal.
• sel : when it's set to '0', datain0 is used to write the register word. otherwise it'll be datain1.
• adr, adw : the width (Y) of those signals is computed from regNumber, like: Y = log2(regNumber). math girlie behavior fr fr ✨
• wen and ren : write enable and read enable, which allow reading and writing when they're set to '1'.

🎀 TERMINAL NAMES 🎀

1. ck : clock signal (input, 1 bit).
2. sel : select the write bus (input, 1 bit).
3. wen : write enable (input, 1 bit).
4. ren : read enable (input, 1 bit).
5. adr : the read address (input, Y bits).
6. adw : the write address (input, Y bits).
7. datain0 : first write bus (input, N bits).
8. datain1 : second write bus (input, N bits).
9. dataout : read bus (output, N bits).
10. vdd : power.
11. vss : ground.

🔥 EXAMPLE 🔥

here's the vibe, no cap:

GENLIB_MACRO(DPGEN_RF1D, "model_rf1dx8_32"
                       , F_BEHAV|F_PLACE
                       , 32  /* Words size.      */
                       , 8   /* Number of words. */
                       );

GENLIB_LOINS( "model_rf1dx8_32"
            , "instance1_rf1d_32"
            , "ck"
            , "sel"
            , "wen"
            , "ren"
            , "adr[2:0]"
            , "adw[2:0]"
            , "datain0[31:0]"
            , "datain1[31:0]"
            , "dataout[31:0]"
            , "vdd", "vss", NULL
            );

🌈 SEE ALSO 🌈

• GENLIB_MACRO(3)
• genlib(1)

okay that's the whole page bestie, you ate that 💖 this was the ASIM/LIP6 version, dated 30 July 2004 — iconic, historic, and yes she's still slaying 🫶✨🌸