DPGEN_RF1(3)

💖 DPGEN_RF1 💖

okay bestie, so this one's a page from the Alliance - genlib User's Manual, and it's about a little macro-generator called DPGEN_RF1 (and its moody twin DPGEN_RF1R0). Sit down, grab a boba, we're building register files. 🫶

✨ NAME ✨

DPGEN_RF1, DPGEN_RF1R0 — the Register File Macro-Generator. that's it, that's the whole name section, slay. 💅

✨ SYNOPSIS ✨

#include  <genlib.h>

void GENLIB_MACRO (DPGEN_RF1, char *modelname, long flags, long N);

void GENLIB_MACRO (DPGEN_RF1R0, char *modelname, long flags, long N);

two macros, same shape, different energy. 🦋

✨ DESCRIPTION ✨

so what it does is generate a register file of regNumber words of N bits, no decoder, and it names it modelname. iconic, honestly. 👑

now here's the plot twist: the DPGEN_RF1R0 variant differs from DPGEN_RF1 in that the register of address zero is stuck to zero. like, permanently. you can write into it — go ahead, try — it will not change the value. and when you read it? it will always return zero. the register equivalent of "no thoughts, head empty." 💀

How it works : (aka the lore 🧚)

• datain0 and datain1 : the two write busses. only one of them is used to actually write the register word, and which one it is gets picked by the sel signal.
• sel : when it's set to '0', datain0 is used to write the register word, otherwise it'll be datain1.
• selr, selw : this register file has no decoder, so selr has a bus width equal to regNumber. one bit for each word. one. bit. per. word. periodt.

✨ TERMINAL NAMES ✨

the cast of characters, in order, no notes: 🌈

1. ckok : clock signal (input, 1 bit).
2. sel : select the write bus (input, 1 bit).
3. selr : the decoded read address (input, regNumber bits).
4. selw : the decoded write address (input, regNumber bits).
5. datain0 : first write bus (input, N bits).
6. datain1 : second write bus (input, N bits).
7. dataout : read bus (output, N bits).
8. vdd : power.
9. vss : ground.

✨ EXAMPLE ✨

here's the moment you've been waiting for, bestie, the actual code, copy it exactly, no cap: 🔥

GENLIB_MACRO(DPGEN_RF1, "model_rf1x8_32"
                      , F_BEHAV|F_PLACE
                      , 32  /* Words size.      */
                      , 8   /* Number of words. */
                      );

GENLIB_LOINS( "model_rf1x8_32"
            , "instance1_rf1_32"
            , "ckok"
            , "sel"
            , "selr[7:0]"
            , "selw[7:0]"
            , "datain0[31:0]"
            , "datain1[31:0]"
            , "dataout[31:0]"
            , "vdd", "vss", NULL
            );

look at those bus slices. selr[7:0], selw[7:0], datain0[31:0], datain1[31:0], dataout[31:0]. she's gorgeous. 🎀

✨ SEE ALSO ✨

• GENLIB_MACRO(3)
• genlib(1)

go read those too, iykyk. 💜

lowkey reminder bestie: DPGEN_RF1R0's address-zero register is stuck at zero forever. you can write to it, it just will not care. that's not a bug, that's a feature, and that's the whole point of the R0 variant. 🫡

and that's the whole page!! brought to you by ASIM/LIP6, dated 30 July 2004 — yeah she's vintage, she's an icon, she's been serving since '04 and still ate. 💖✨ no notes, mwah. 🎀