libnvme(9)

πŸ“¦ version 3.2, in arch rolling

πŸ’… libnvme(9) β€” okay bestie, let's talk about enum nvme_lm_queue_attributes

Hi hi hiii 🫢 so this is a page from the libnvme API manual (section 9, iykyk), and today's main character is this enum. Lowkey it's a whole vibe check for how the controller tells you stuff about its I/O submission and I/O completion queues β€” masks and shifts, masks and shifts, that's the energy. Let's get into it ✨


🌸 NAME

enum nvme_lm_queue_attributes β€” I/O Submission and I/O Completion Queue Attributes.

That's it, that's the name. Short, iconic, does exactly what it says on the tin πŸ’…


πŸ¦‹ SYNOPSIS

enum nvme_lm_queue_attributes {
    NVME_LM_IOSQPC_MASK ,
    NVME_LM_IOSQPC_SHIFT ,
    NVME_LM_IOSQPRIO_MASK ,
    NVME_LM_IOSQPRIO_SHIFT ,
    NVME_LM_IOCQPC_MASK ,
    NVME_LM_IOCQPC_SHIFT ,
    NVME_LM_IOCQIEN_MASK ,
    NVME_LM_IOCQIEN_SHIFT ,
    NVME_LM_S0PT_MASK ,
    NVME_LM_S0PT_SHIFT ,
    NVME_LM_IOCQIV_MASK ,
    NVME_LM_IOCQIV_SHIFT

};

Twelve entries, all dressed up with nowhere to go except straight into your bit-twiddling ✨ Every one of them is either a _MASK or a _SHIFT, and honestly? That's the whole personality.


πŸŽ€ Constants

Grab a snack πŸ“ β€” here's every single one, no skips, no cap.

  • NVME_LM_IOSQPC_MASK β€” the mask that snags the Physically Contiguous (PC) bit for this I/O submission queue.
  • NVME_LM_IOSQPC_SHIFT β€” the shift that gets you the PC bit for this I/O submission queue.
  • NVME_LM_IOSQPRIO_MASK β€” the mask that pulls out the Priority for this I/O submission queue.
  • NVME_LM_IOSQPRIO_SHIFT β€” the shift that gets you the Priority for this I/O submission queue.
  • NVME_LM_IOCQPC_MASK β€” the mask for the Physicaly Contiguous (PC) bit for this I/O completion queue.
🫢 tiny heads-up: yes, the original spells it "Physicaly" β€” that's literally how it's written in the doc, so we're keeping it exactly as-is. No autocorrect in this house πŸ’…
  • NVME_LM_IOCQPC_SHIFT β€” the shift that gets you the PC bit for this I/O completion queue.
  • NVME_LM_IOCQIEN_MASK β€” the mask that grabs the Interrupts Enabled bit for this I/O completion queue.
  • NVME_LM_IOCQIEN_SHIFT β€” the shift that gets you the Interrupts Enabled bit for this I/O completion.
  • NVME_LM_S0PT_MASK β€” the mask that fishes out the value of the Phase Tag bit for Slot 0 of this I/O completion queue.
  • NVME_LM_S0PT_SHIFT β€” the shift that gets you the value of the Phase Tag bit for Slot 0 of this I/O completion queue.
  • NVME_LM_IOCQIV_MASK β€” the mask that pulls the Interrupt Vector (IV) for this I/O completion queue.
  • NVME_LM_IOCQIV_SHIFT β€” the shift that gets you the IV for this I/O completion queue.

Mask then shift, mask then shift β€” it's giving choreography πŸ”₯ You & with the mask, you >> by the shift, and boom, the field is yours. That's the pattern for every single pair up there, no exceptions, fr fr.


πŸ’œ That's the whole page bestie β€” all twelve constants, accounted for, nothing dropped. Go forth and bit-twiddle responsibly.

And that's a wrap! 🌈 This was libnvme(9) β€” source/version is libnvme, dated October 2026 πŸ“… mwah, drink some water, and may your queues always be properly masked πŸ’–πŸŽ€πŸ¦‹

πŸ“¦ where this page comes from