libnvme(9)

πŸ“¦ version 3.2, in arch rolling

πŸ’– libnvme(9) β€” part one, bestie πŸ’–

okay so. this is a page from the libnvme API manual, section 9, and before you panic at the size of it: it's literally just one enum. one. that's the whole page. we're gonna get through it together 🫢


🌸 NAME 🌸

enum nvme_feat β€” the Features Access Shifts/Masks values.

that's it, that's the name. it's giving "I contain multitudes" because there are so many constants in here, but the job description is exactly one line: these are the shift and mask values for feature access. ✨


πŸ¦‹ SYNOPSIS πŸ¦‹

so the way this works is chef's kiss simple lowkey: for basically every NVMe feature, there's a <THING>_SHIFT constant and a matching <THING>_MASK constant, all chillin' in one enum. you take a value, you shift it, you mask it, you're done. iconic behaviour honestly πŸ’…

and then there are a handful of absolute renegades in here that show up without a _MASK sibling β€” those are just vibing on their own, no cap, and yes you will spot them on the way down πŸ‘€

here's the whole thing, character for character, exactly as the header has it:

enum nvme_feat {
    NVME_FEAT_ARBITRATION_BURST_SHIFT ,
    NVME_FEAT_ARBITRATION_BURST_MASK ,
    NVME_FEAT_ARBITRATION_LPW_SHIFT ,
    NVME_FEAT_ARBITRATION_LPW_MASK ,
    NVME_FEAT_ARBITRATION_MPW_SHIFT ,
    NVME_FEAT_ARBITRATION_MPW_MASK ,
    NVME_FEAT_ARBITRATION_HPW_SHIFT ,
    NVME_FEAT_ARBITRATION_HPW_MASK ,
    NVME_FEAT_PWRMGMT_PS_SHIFT ,
    NVME_FEAT_PWRMGMT_PS_MASK ,
    NVME_FEAT_PWRMGMT_WH_SHIFT ,
    NVME_FEAT_PWRMGMT_WH_MASK ,
    NVME_FEAT_PWRMGMT_IIELL_SHIFT ,
    NVME_FEAT_PWRMGMT_IIELL_MASK ,
    NVME_FEAT_LBAR_NR_SHIFT ,
    NVME_FEAT_LBAR_NR_MASK ,
    NVME_FEAT_TT_TMPTH_SHIFT ,
    NVME_FEAT_TT_TMPTH_MASK ,
    NVME_FEAT_TT_TMPSEL_SHIFT ,
    NVME_FEAT_TT_TMPSEL_MASK ,
    NVME_FEAT_TT_THSEL_SHIFT ,
    NVME_FEAT_TT_THSEL_MASK ,
    NVME_FEAT_TT_TMPTHH_SHIFT ,
    NVME_FEAT_TT_TMPTHH_MASK ,
    NVME_FEAT_ERROR_RECOVERY_TLER_SHIFT ,
    NVME_FEAT_ERROR_RECOVERY_TLER_MASK ,
    NVME_FEAT_ERROR_RECOVERY_DULBE_SHIFT ,
    NVME_FEAT_ERROR_RECOVERY_DULBE_MASK ,
    NVME_FEAT_VWC_WCE_SHIFT ,
    NVME_FEAT_VWC_WCE_MASK ,
    NVME_FEAT_NRQS_NSQR_SHIFT ,
    NVME_FEAT_NRQS_NSQR_MASK ,
    NVME_FEAT_NRQS_NCQR_SHIFT ,
    NVME_FEAT_NRQS_NCQR_MASK ,
    NVME_FEAT_IRQC_THR_SHIFT ,
    NVME_FEAT_IRQC_THR_MASK ,
    NVME_FEAT_IRQC_TIME_SHIFT ,
    NVME_FEAT_IRQC_TIME_MASK ,
    NVME_FEAT_ICFG_IV_SHIFT ,
    NVME_FEAT_ICFG_IV_MASK ,
    NVME_FEAT_ICFG_CD_SHIFT ,
    NVME_FEAT_ICFG_CD_MASK ,
    NVME_FEAT_WA_DN_SHIFT ,
    NVME_FEAT_WA_DN_MASK ,
    NVME_FEAT_AE_SMART_SHIFT ,
    NVME_FEAT_AE_SMART_MASK ,
    NVME_FEAT_AE_NAN_SHIFT ,
    NVME_FEAT_AE_NAN_MASK ,
    NVME_FEAT_AE_FW_SHIFT ,
    NVME_FEAT_AE_FW_MASK ,
    NVME_FEAT_AE_TELEM_SHIFT ,
    NVME_FEAT_AE_TELEM_MASK ,
    NVME_FEAT_AE_ANA_SHIFT ,
    NVME_FEAT_AE_ANA_MASK ,
    NVME_FEAT_AE_PLA_SHIFT ,
    NVME_FEAT_AE_PLA_MASK ,
    NVME_FEAT_AE_LBAS_SHIFT ,
    NVME_FEAT_AE_LBAS_MASK ,
    NVME_FEAT_AE_EGA_SHIFT ,
    NVME_FEAT_AE_EGA_MASK ,
    NVME_FEAT_AE_NNSSHDN_SHIFT ,
    NVME_FEAT_AE_NNSSHDN_MASK ,
    NVME_FEAT_AE_TTHRY_SHIFT ,
    NVME_FEAT_AE_TTHRY_MASK ,
    NVME_FEAT_AE_RASSN_SHIFT ,
    NVME_FEAT_AE_RASSN_MASK ,
    NVME_FEAT_AE_RGRP0_SHIFT ,
    NVME_FEAT_AE_RGRP0_MASK ,
    NVME_FEAT_AE_ANSAN_SHIFT ,
    NVME_FEAT_AE_ANSAN_MASK ,
    NVME_FEAT_AE_CCRCN_SHIFT ,
    NVME_FEAT_AE_CCRCN_MASK ,
    NVME_FEAT_AE_LHCN_SHIFT ,
    NVME_FEAT_AE_LHCN_MASK ,
    NVME_FEAT_AE_RLCCN_SHIFT ,
    NVME_FEAT_AE_RLCCN_MASK ,
    NVME_FEAT_AE_ZDCN_SHIFT ,
    NVME_FEAT_AE_ZDCN_MASK ,
    NVME_FEAT_AE_PMDRLPCN_SHIFT ,
    NVME_FEAT_AE_PMDRLPCN_MASK ,
    NVME_FEAT_AE_ADLPCN_SHIFT ,
    NVME_FEAT_AE_ADLPCN_MASK ,
    NVME_FEAT_AE_HDLPCN_SHIFT ,
    NVME_FEAT_AE_HDLPCN_MASK ,
    NVME_FEAT_AE_DLPCN_SHIFT ,
    NVME_FEAT_AE_DLPCN_MASK ,
    NVME_FEAT_APST_APSTE_SHIFT ,
    NVME_FEAT_APST_APSTE_MASK ,
    NVME_FEAT_HMEM_EHM_SHIFT ,
    NVME_FEAT_HMEM_EHM_MASK ,
    NVME_FEAT_KATO_TIMEOUT_SHIFT ,
    NVME_FEAT_KATO_TIMEOUT_MASK ,
    NVME_FEAT_HCTM_TMT2_SHIFT ,
    NVME_FEAT_HCTM_TMT2_MASK ,
    NVME_FEAT_HCTM_TMT1_SHIFT ,
    NVME_FEAT_HCTM_TMT1_MASK ,
    NVME_FEAT_NOPS_NOPPME_SHIFT ,
    NVME_FEAT_NOPS_NOPPME_MASK ,
    NVME_FEAT_RRL_NVMSETID_SHIFT ,
    NVME_FEAT_RRL_NVMSETID_MASK ,
    NVME_FEAT_RRL_RRL_SHIFT ,
    NVME_FEAT_RRL_RRL_MASK ,
    NVME_FEAT_PLM_NVMSETID_SHIFT ,
    NVME_FEAT_PLM_NVMSETID_MASK ,
    NVME_FEAT_PLM_LPE_SHIFT ,
    NVME_FEAT_PLM_LPE_MASK ,
    NVME_FEAT_PLMW_WS_SHIFT ,
    NVME_FEAT_PLMW_WS_MASK ,
    NVME_FEAT_LBAS_LSIRI_SHIFT ,
    NVME_FEAT_LBAS_LSIRI_MASK ,
    NVME_FEAT_LBAS_LSIPI_SHIFT ,
    NVME_FEAT_LBAS_LSIPI_MASK ,
    NVME_FEAT_SC_NODRM_SHIFT ,
    NVME_FEAT_SC_NODRM_MASK ,
    NVME_FEAT_EG_ENDGID_SHIFT ,
    NVME_FEAT_EG_ENDGID_MASK ,
    NVME_FEAT_EG_EGCW_SHIFT ,
    NVME_FEAT_EG_EGCW_MASK ,
    NVME_FEAT_FDPE_PHNDL_SHIFT ,
    NVME_FEAT_FDPE_PHNDL_MASK ,
    NVME_FEAT_FDPE_NOET_SHIFT ,
    NVME_FEAT_FDPE_NOET_MASK ,
    NVME_FEAT_SPM_PBSLC_SHIFT ,
    NVME_FEAT_SPM_PBSLC_MASK ,
    NVME_FEAT_HOSTID_EXHID_SHIFT ,
    NVME_FEAT_HOSTID_EXHID_MASK ,
    NVME_FEAT_RM_REGPRE_SHIFT ,
    NVME_FEAT_RM_REGPRE_MASK ,
    NVME_FEAT_RM_RESREL_SHIFT ,
    NVME_FEAT_RM_RESREL_MASK ,
    NVME_FEAT_RM_RESPRE_SHIFT ,
    NVME_FEAT_RM_RESPRE_MASK ,
    NVME_FEAT_RP_PTPL_SHIFT ,
    NVME_FEAT_RP_PTPL_MASK ,
    NVME_FEAT_WP_WPS_SHIFT ,
    NVME_FEAT_WP_WPS_MASK ,
    NVME_FEAT_IOCSP_IOCSCI_SHIFT ,
    NVME_FEAT_IOCSP_IOCSCI_MASK ,
    NVME_FEAT_SPINUP_CONTROL_SHIFT ,
    NVME_FEAT_SPINUP_CONTROL_MASK ,
    NVME_FEAT_PLS_MODE_SHIFT ,
    NVME_FEAT_PLS_MODE_MASK ,
    NVME_FEAT_PERFC_ATTRI_SHIFT ,
    NVME_FEAT_PERFC_ATTRI_MASK ,
    NVME_FEAT_PERFC_RVSPA_SHIFT ,
    NVME_FEAT_PERFC_RVSPA_MASK ,
    NVME_FEAT_PERFC_ATTRTYP_SHIFT ,
    NVME_FEAT_PERFC_ATTRTYP_MASK ,
    NVME_FEAT_FDP_ENABLED_SHIFT ,
    NVME_FEAT_FDP_ENABLED_MASK ,
    NVME_FEAT_FDP_INDEX_SHIFT ,
    NVME_FEAT_FDP_INDEX_MASK ,
    NVME_FEAT_FDP_EVENTS_ENABLE_SHIFT ,
    NVME_FEAT_FDP_EVENTS_ENABLE_MASK ,
    NVME_FEAT_HOST_ID_EXHID_SHIFT ,
    NVME_FEAT_HOST_ID_EXHID_MASK ,
    NVME_FEAT_BPWPC_BP0WPS_SHIFT ,
    NVME_FEAT_BPWPC_BP0WPS_MASK ,
    NVME_FEAT_BPWPC_BP1WPS_SHIFT ,
    NVME_FEAT_BPWPC_BP1WPS_MASK ,
    NVME_FEAT_SANITIZE_NODRM_SHIFT ,
    NVME_FEAT_SANITIZE_NODRM_MASK ,
    NVME_FEAT_RESP_PTPL_SHIFT ,
    NVME_FEAT_RESP_PTPL_MASK ,
    NVME_FEAT_CDP_CHPS ,
    NVME_FEAT_CDP_PERFS ,
    NVME_FEAT_CDP_PERID_SHIFT ,
    NVME_FEAT_CDP_PERID_MASK ,
    NVME_FEAT_CDP_PMDSS ,
    NVME_FEAT_CDP_PPSC ,
    NVME_FEAT_POWER_LIMIT_PLV_SHIFT ,
    NVME_FEAT_POWER_LIMIT_PLV_MASK ,
    NVME_FEAT_POWER_LIMIT_PLS_SHIFT ,
    NVME_FEAT_POWER_LIMIT_PLS_MASK ,
    NVME_FEAT_POWER_THRESH_PTV_SHIFT ,
    NVME_FEAT_POWER_THRESH_PTV_MASK ,
    NVME_FEAT_POWER_THRESH_PTS_SHIFT ,
    NVME_FEAT_POWER_THRESH_PTS_MASK ,
    NVME_FEAT_POWER_THRESH_PMTS_SHIFT ,
    NVME_FEAT_POWER_THRESH_PMTS_MASK ,
    NVME_FEAT_POWER_THRESH_EPT_SHIFT ,
    NVME_FEAT_POWER_THRESH_EPT_MASK ,
    NVME_FEAT_POWER_MEAS_ACT_SHIFT ,
    NVME_FEAT_POWER_MEAS_ACT_MASK ,
    NVME_FEAT_POWER_MEAS_PMTS_SHIFT ,
    NVME_FEAT_POWER_MEAS_PMTS_MASK ,
    NVME_FEAT_POWER_MEAS_SMT_SHIFT ,
    NVME_FEAT_POWER_MEAS_SMT_MASK ,
    NVME_FEAT_VOLTAGE_THRESHOLD_UVT_SHIFT ,
    NVME_FEAT_VOLTAGE_THRESHOLD_UVT_MASK ,
    NVME_FEAT_VOLTAGE_THRESHOLD_OVT_SHIFT ,
    NVME_FEAT_VOLTAGE_THRESHOLD_OVT_MASK ,
    NVME_FEAT_VOLTAGE_THRESHOLD_EVT ,
    NVME_FEAT_VOLTAGE_THRESHOLD_VSENS_SHIFT ,
    NVME_FEAT_VOLTAGE_THRESHOLD_VSENS_MASK ,
    NVME_FEAT_VOLTAGE_MEASUREMENT_ACT_SHIFT ,
    NVME_FEAT_VOLTAGE_MEASUREMENT_ACT_MASK ,
    NVME_FEAT_RATE_LIMITING_TID_SHIFT ,
    NVME_FEAT_RATE_LIMITING_TID_MASK ,
    NVME_FEAT_RATE_LIMITING_TGT_SHIFT ,
    NVME_FEAT_RATE_LIMITING_TGT_MASK

};
⚠️ okay quick vibe check, bestie: this enum is literally the whole content of this section. there's no extra prose in the original telling you what each constant is for β€” it's just the declaration. so if you were waiting for me to spill the tea on what NVME_FEAT_AE_HDLPCN_MASK actually masks... that info lives somewhere else, not here. πŸ™ˆ i'm not gonna make it up, that would be so not slay of me.

πŸŽ€ a lil tour, because it's long and you deserve a map πŸŽ€

not new info, just me pointing at what's already right there in the list β€” so you don't get lost in the sauce 🌈

  • the _SHIFT / _MASK pairs are the standard move β€” every one of these comes as a matched set, and the pattern <GROUP>_<FIELD>_SHIFT next to <GROUP>_<FIELD>_MASK holds all the way down the file πŸ’–
  • NVME_FEAT_ARBITRATION_* kicks it off with BURST, LPW, MPW, HPW β€” four fields, eight constants, first of many πŸ¦‹
  • NVME_FEAT_PWRMGMT_*, NVME_FEAT_TT_* (TMPTH, TMPSEL, THSEL, TMPTHH), NVME_FEAT_ERROR_RECOVERY_*, NVME_FEAT_NRQS_*, NVME_FEAT_IRQC_* β€” yes bestie, they really did just keep going πŸ”₯
  • the NVME_FEAT_AE_* family is the absolute main character of this list β€” SMART, NAN, FW, TELEM, ANA, PLA, LBAS, EGA, NNSSHDN, TTHRY, RASSN, RGRP0, ANSAN, CCRCN, LHCN, RLCCN, ZDCN, PMDRLPCN, ADLPCN, HDLPCN, DLPCN… that's twenty-one fields, bestie. twenty-one. and honestly? ate. πŸ‘‘
  • NVME_FEAT_CDP_CHPS, NVME_FEAT_CDP_PERFS, NVME_FEAT_CDP_PMDSS, NVME_FEAT_CDP_PPSC and NVME_FEAT_VOLTAGE_THRESHOLD_EVT β€” here they are, the no-mask solo artists πŸ’€ they're nestled right in between their paired-up neighbours and they simply do not have a _SHIFT/_MASK twin. iconic, mysterious, slightly chaotic. we don't question them. πŸ™ˆ
  • the power / voltage / rate-limiting crew closes us out β€” POWER_LIMIT_*, POWER_THRESH_*, POWER_MEAS_*, VOLTAGE_THRESHOLD_*, VOLTAGE_MEASUREMENT_*, RATE_LIMITING_* ⚑🌸
  • also don't sleep on the near-duplicates, because they are not typos and you cannot merge them: NVME_FEAT_HOSTID_EXHID_SHIFT/_MASK and NVME_FEAT_HOST_ID_EXHID_SHIFT/_MASK are two separate things living their two separate lives, same with NVME_FEAT_RP_PTPL_* vs NVME_FEAT_RESP_PTPL_*, and NVME_FEAT_LBAS_* shows up in two different neighbourhoods. copy the exact name you need, every time, no shortcuts 😭

and that's the whole of part one, bestie β€” no exit statuses, no error codes, no environment variables hiding in here, it's pure constants 🌸

πŸ’œ there's more coming, so don't go anywhere β€” this is not the end of the page, and the rest is still loading in. 🧚

🌸 CONSTANTS 🌸

okay bestie, sit down, hydrate, this is the long one πŸ’… it's the full constant dump, in order, nothing skipped β€” every _SHIFT and every _MASK is here, and the ones that had a little note in the original get their note. everything in backticks is literal, copy it exactly, don't get cute with the spelling ✨

most of these are just a name and a vibe (no description given, the name is doing all the work), and a few come with an actual explanation which I've kept for you 🫢


  • NVME_FEAT_ARBITRATION_BURST_SHIFT
  • NVME_FEAT_ARBITRATION_BURST_MASK
  • NVME_FEAT_ARBITRATION_LPW_SHIFT
  • NVME_FEAT_ARBITRATION_LPW_MASK
  • NVME_FEAT_ARBITRATION_MPW_SHIFT
  • NVME_FEAT_ARBITRATION_MPW_MASK
  • NVME_FEAT_ARBITRATION_HPW_SHIFT
  • NVME_FEAT_ARBITRATION_HPW_MASK

arbitration era πŸŽ€ four pairs, no notes, zero elaboration, but they're iconic for showing up first.


  • NVME_FEAT_PWRMGMT_PS_SHIFT
  • NVME_FEAT_PWRMGMT_PS_MASK
  • NVME_FEAT_PWRMGMT_WH_SHIFT
  • NVME_FEAT_PWRMGMT_WH_MASK
  • NVME_FEAT_PWRMGMT_IIELL_SHIFT β€” the shift amount to set/get the Idle I/O Exit Latency Limit (IIELL), in units of 100 microseconds ⏱️
  • NVME_FEAT_PWRMGMT_IIELL_MASK β€” the mask to set/get IIELL

  • NVME_FEAT_LBAR_NR_SHIFT
  • NVME_FEAT_LBAR_NR_MASK
  • NVME_FEAT_TT_TMPTH_SHIFT
  • NVME_FEAT_TT_TMPTH_MASK
  • NVME_FEAT_TT_TMPSEL_SHIFT
  • NVME_FEAT_TT_TMPSEL_MASK
  • NVME_FEAT_TT_THSEL_SHIFT
  • NVME_FEAT_TT_THSEL_MASK
  • NVME_FEAT_TT_TMPTHH_SHIFT
  • NVME_FEAT_TT_TMPTHH_MASK
  • NVME_FEAT_ERROR_RECOVERY_TLER_SHIFT
  • NVME_FEAT_ERROR_RECOVERY_TLER_MASK
  • NVME_FEAT_ERROR_RECOVERY_DULBE_SHIFT
  • NVME_FEAT_ERROR_RECOVERY_DULBE_MASK
  • NVME_FEAT_VWC_WCE_SHIFT
  • NVME_FEAT_VWC_WCE_MASK
  • NVME_FEAT_NRQS_NSQR_SHIFT
  • NVME_FEAT_NRQS_NSQR_MASK
  • NVME_FEAT_NRQS_NCQR_SHIFT
  • NVME_FEAT_NRQS_NCQR_MASK
  • NVME_FEAT_IRQC_THR_SHIFT
  • NVME_FEAT_IRQC_THR_MASK
  • NVME_FEAT_IRQC_TIME_SHIFT
  • NVME_FEAT_IRQC_TIME_MASK
  • NVME_FEAT_ICFG_IV_SHIFT
  • NVME_FEAT_ICFG_IV_MASK
  • NVME_FEAT_ICFG_CD_SHIFT
  • NVME_FEAT_ICFG_CD_MASK
  • NVME_FEAT_WA_DN_SHIFT
  • NVME_FEAT_WA_DN_MASK

that's a whole little block of shift + mask besties, no commentary attached in the source, so no invented lore from me πŸ™ˆ


now the async event notification ones, and honestly this run ate πŸ‘‘

  • NVME_FEAT_AE_SMART_SHIFT
  • NVME_FEAT_AE_SMART_MASK
  • NVME_FEAT_AE_NAN_SHIFT
  • NVME_FEAT_AE_NAN_MASK
  • NVME_FEAT_AE_FW_SHIFT
  • NVME_FEAT_AE_FW_MASK
  • NVME_FEAT_AE_TELEM_SHIFT
  • NVME_FEAT_AE_TELEM_MASK
  • NVME_FEAT_AE_ANA_SHIFT
  • NVME_FEAT_AE_ANA_MASK
  • NVME_FEAT_AE_PLA_SHIFT
  • NVME_FEAT_AE_PLA_MASK
  • NVME_FEAT_AE_LBAS_SHIFT
  • NVME_FEAT_AE_LBAS_MASK
  • NVME_FEAT_AE_EGA_SHIFT
  • NVME_FEAT_AE_EGA_MASK
  • NVME_FEAT_AE_NNSSHDN_SHIFT
  • NVME_FEAT_AE_NNSSHDN_MASK
  • NVME_FEAT_AE_TTHRY_SHIFT
  • NVME_FEAT_AE_TTHRY_MASK
  • NVME_FEAT_AE_RASSN_SHIFT
  • NVME_FEAT_AE_RASSN_MASK
  • NVME_FEAT_AE_RGRP0_SHIFT
  • NVME_FEAT_AE_RGRP0_MASK
  • NVME_FEAT_AE_ANSAN_SHIFT
  • NVME_FEAT_AE_ANSAN_MASK
  • NVME_FEAT_AE_CCRCN_SHIFT
  • NVME_FEAT_AE_CCRCN_MASK
  • NVME_FEAT_AE_LHCN_SHIFT
  • NVME_FEAT_AE_LHCN_MASK
  • NVME_FEAT_AE_RLCCN_SHIFT β€” the shift amount to get/set the Rate Limiting Configuration Change Notices (RLCCN)
  • NVME_FEAT_AE_RLCCN_MASK β€” the mask to get/set RLCCN
  • NVME_FEAT_AE_ZDCN_SHIFT
  • NVME_FEAT_AE_ZDCN_MASK
  • NVME_FEAT_AE_PMDRLPCN_SHIFT
  • NVME_FEAT_AE_PMDRLPCN_MASK
  • NVME_FEAT_AE_ADLPCN_SHIFT
  • NVME_FEAT_AE_ADLPCN_MASK
  • NVME_FEAT_AE_HDLPCN_SHIFT
  • NVME_FEAT_AE_HDLPCN_MASK
  • NVME_FEAT_AE_DLPCN_SHIFT
  • NVME_FEAT_AE_DLPCN_MASK

  • NVME_FEAT_APST_APSTE_SHIFT
  • NVME_FEAT_APST_APSTE_MASK
  • NVME_FEAT_HMEM_EHM_SHIFT
  • NVME_FEAT_HMEM_EHM_MASK
  • NVME_FEAT_KATO_TIMEOUT_SHIFT
  • NVME_FEAT_KATO_TIMEOUT_MASK
  • NVME_FEAT_HCTM_TMT2_SHIFT
  • NVME_FEAT_HCTM_TMT2_MASK
  • NVME_FEAT_HCTM_TMT1_SHIFT
  • NVME_FEAT_HCTM_TMT1_MASK
  • NVME_FEAT_NOPS_NOPPME_SHIFT
  • NVME_FEAT_NOPS_NOPPME_MASK
  • NVME_FEAT_RRL_NVMSETID_SHIFT
  • NVME_FEAT_RRL_NVMSETID_MASK
  • NVME_FEAT_RRL_RRL_SHIFT
  • NVME_FEAT_RRL_RRL_MASK
  • NVME_FEAT_PLM_NVMSETID_SHIFT
  • NVME_FEAT_PLM_NVMSETID_MASK
  • NVME_FEAT_PLM_LPE_SHIFT
  • NVME_FEAT_PLM_LPE_MASK
  • NVME_FEAT_PLMW_WS_SHIFT
  • NVME_FEAT_PLMW_WS_MASK
  • NVME_FEAT_LBAS_LSIRI_SHIFT
  • NVME_FEAT_LBAS_LSIRI_MASK
  • NVME_FEAT_LBAS_LSIPI_SHIFT
  • NVME_FEAT_LBAS_LSIPI_MASK
  • NVME_FEAT_SC_NODRM_SHIFT
  • NVME_FEAT_SC_NODRM_MASK
  • NVME_FEAT_EG_ENDGID_SHIFT
  • NVME_FEAT_EG_ENDGID_MASK
  • NVME_FEAT_EG_EGCW_SHIFT
  • NVME_FEAT_EG_EGCW_MASK
  • NVME_FEAT_FDPE_PHNDL_SHIFT
  • NVME_FEAT_FDPE_PHNDL_MASK
  • NVME_FEAT_FDPE_NOET_SHIFT
  • NVME_FEAT_FDPE_NOET_MASK
  • NVME_FEAT_SPM_PBSLC_SHIFT
  • NVME_FEAT_SPM_PBSLC_MASK
  • NVME_FEAT_HOSTID_EXHID_SHIFT
  • NVME_FEAT_HOSTID_EXHID_MASK
  • NVME_FEAT_RM_REGPRE_SHIFT
  • NVME_FEAT_RM_REGPRE_MASK
  • NVME_FEAT_RM_RESREL_SHIFT
  • NVME_FEAT_RM_RESREL_MASK
  • NVME_FEAT_RM_RESPRE_SHIFT
  • NVME_FEAT_RM_RESPRE_MASK
  • NVME_FEAT_RP_PTPL_SHIFT
  • NVME_FEAT_RP_PTPL_MASK
  • NVME_FEAT_WP_WPS_SHIFT
  • NVME_FEAT_WP_WPS_MASK
  • NVME_FEAT_IOCSP_IOCSCI_SHIFT
  • NVME_FEAT_IOCSP_IOCSCI_MASK
  • NVME_FEAT_SPINUP_CONTROL_SHIFT
  • NVME_FEAT_SPINUP_CONTROL_MASK
  • NVME_FEAT_PLS_MODE_SHIFT
  • NVME_FEAT_PLS_MODE_MASK
  • NVME_FEAT_PERFC_ATTRI_SHIFT
  • NVME_FEAT_PERFC_ATTRI_MASK
  • NVME_FEAT_PERFC_RVSPA_SHIFT
  • NVME_FEAT_PERFC_RVSPA_MASK
  • NVME_FEAT_PERFC_ATTRTYP_SHIFT
  • NVME_FEAT_PERFC_ATTRTYP_MASK
  • NVME_FEAT_FDP_ENABLED_SHIFT
  • NVME_FEAT_FDP_ENABLED_MASK
  • NVME_FEAT_FDP_INDEX_SHIFT
  • NVME_FEAT_FDP_INDEX_MASK
  • NVME_FEAT_FDP_EVENTS_ENABLE_SHIFT
  • NVME_FEAT_FDP_EVENTS_ENABLE_MASK
  • NVME_FEAT_HOST_ID_EXHID_SHIFT
  • NVME_FEAT_HOST_ID_EXHID_MASK
  • NVME_FEAT_BPWPC_BP0WPS_SHIFT
  • NVME_FEAT_BPWPC_BP0WPS_MASK
  • NVME_FEAT_BPWPC_BP1WPS_SHIFT
  • NVME_FEAT_BPWPC_BP1WPS_MASK
  • NVME_FEAT_SANITIZE_NODRM_SHIFT
  • NVME_FEAT_SANITIZE_NODRM_MASK
  • NVME_FEAT_RESP_PTPL_SHIFT
  • NVME_FEAT_RESP_PTPL_MASK
heads up bestie: NVME_FEAT_HOSTID_EXHID_SHIFT / _MASK and NVME_FEAT_HOST_ID_EXHID_SHIFT / _MASK are two different spellings that both live in here πŸ‘€ don't go "fixing" one into the other, they're both listed in the source and both must stay. copy-paste, never retype, iykyk 😭

the CDP ones πŸ¦‹

these are the change-personality constants, and a few of them came with actual notes about which dword they live in β€” keep those exact:

  • NVME_FEAT_CDP_CHPS β€” Change Personality Settings (Set Features Command Dword 13 only)
  • NVME_FEAT_CDP_PERFS β€” Personality Freeze State (Set Features Command Dword 13, and Get Features Completion Queue Entry Dword 0)
  • NVME_FEAT_CDP_PERID_SHIFT β€” the shift amount to set/get the Personality Identifier (Set Features Command Dword 13, and Get Features Completion Queue Entry Dword 0)
  • NVME_FEAT_CDP_PERID_MASK β€” the mask to set/get the Personality Identifier
  • NVME_FEAT_CDP_PMDSS β€” Personality Manufacturing Default Settings State (Get Features Completion Queue Entry Dword 0 only)
  • NVME_FEAT_CDP_PPSC β€” Pending Personality Settings Change (Get Features Completion Queue Entry Dword 0 only)

power stuff πŸ”₯

  • NVME_FEAT_POWER_LIMIT_PLV_SHIFT
  • NVME_FEAT_POWER_LIMIT_PLV_MASK
  • NVME_FEAT_POWER_LIMIT_PLS_SHIFT
  • NVME_FEAT_POWER_LIMIT_PLS_MASK
  • NVME_FEAT_POWER_THRESH_PTV_SHIFT
  • NVME_FEAT_POWER_THRESH_PTV_MASK
  • NVME_FEAT_POWER_THRESH_PTS_SHIFT
  • NVME_FEAT_POWER_THRESH_PTS_MASK
  • NVME_FEAT_POWER_THRESH_PMTS_SHIFT
  • NVME_FEAT_POWER_THRESH_PMTS_MASK
  • NVME_FEAT_POWER_THRESH_EPT_SHIFT
  • NVME_FEAT_POWER_THRESH_EPT_MASK
  • NVME_FEAT_POWER_MEAS_ACT_SHIFT
  • NVME_FEAT_POWER_MEAS_ACT_MASK
  • NVME_FEAT_POWER_MEAS_PMTS_SHIFT
  • NVME_FEAT_POWER_MEAS_PMTS_MASK
  • NVME_FEAT_POWER_MEAS_SMT_SHIFT
  • NVME_FEAT_POWER_MEAS_SMT_MASK

voltage + rate limiting ⚑

these ones do have notes, and the notes reference enums, so keep the enum names exactly as written bestie:

  • NVME_FEAT_VOLTAGE_THRESHOLD_UVT_SHIFT β€” the shift amount to set/get the Undervoltage Threshold (UVT)
  • NVME_FEAT_VOLTAGE_THRESHOLD_UVT_MASK β€” the mask to set/get UVT
  • NVME_FEAT_VOLTAGE_THRESHOLD_OVT_SHIFT β€” the shift amount to set/get the Overvoltage Threshold (OVT)
  • NVME_FEAT_VOLTAGE_THRESHOLD_OVT_MASK β€” the mask to set/get OVT
  • NVME_FEAT_VOLTAGE_THRESHOLD_EVT β€” Enable Voltage Threshold
  • NVME_FEAT_VOLTAGE_THRESHOLD_VSENS_SHIFT β€” the shift amount to set/get the Voltage Sensor Select (VSENS), see enum nvme_voltage_sensor
  • NVME_FEAT_VOLTAGE_THRESHOLD_VSENS_MASK β€” the mask to set/get VSENS
  • NVME_FEAT_VOLTAGE_MEASUREMENT_ACT_SHIFT β€” the shift amount to set the Action (ACT), see enum nvme_voltage_measurement_act
  • NVME_FEAT_VOLTAGE_MEASUREMENT_ACT_MASK β€” the mask to set ACT
  • NVME_FEAT_RATE_LIMITING_TID_SHIFT β€” the shift amount to set/get the Target Identifier (TID)
  • NVME_FEAT_RATE_LIMITING_TID_MASK β€” the mask to set/get TID
  • NVME_FEAT_RATE_LIMITING_TGT_SHIFT β€” the shift amount to set/get the Target (TGT), see enum nvme_rate_limiting_target
  • NVME_FEAT_RATE_LIMITING_TGT_MASK β€” the mask to set/get TGT

and that's the whole list, bestie β€” every single constant, in order, accounted for 🌈 that's the entire Constants section of enum nvme_feat, no cap, nothing dropped on the floor. you ate that πŸ’…βœ¨

this was the enum nvme_feat page from libnvme, dated October 2026 β€” mwah, go touch some grass, then come back and read part one again πŸ«ΆπŸ’œ

πŸ“¦ where this page comes from