YOSYS-SMTBMC(1)

✨ yosys-smtbmc ✨

okay bestie, gather round πŸ’– this is the manual page for yosys-smtbmc, and its whole entire job is writing your design out to an SMT2-LIBv2 file. that's it. that's the gig. no cap.

it's giving "tiny tool, big consequences," and honestly? iconic.


🌸 SYNOPSIS 🌸

yosys-smtbmc [options] <yosys_smt2_output>

you hand it the SMT2 output from Yosys, you sprinkle some options on top, and off it goes πŸ¦‹


πŸ’… OPTIONS πŸ’…

  • -t [<skip_steps>:]<num_steps> β€” sets your steps, and yes the bracket part is optional. the defaults are skip_steps=0 and num_steps=20, so if you just vibe with it, that's what you get. ✨
  • -u <start_step> β€” assumes asserts in skipped steps when you're in BMC mode. lowkey a whole mood.
  • -S <step_size> β€” proves <step_size> time steps all at once. big batch energy. πŸ”₯
  • -c <vcd_filename> β€” writes the counter-example out to this VCD file. πŸ’€ (hint: use write_smt2 -wires for maximum coverage of signals in the generated VCD file β€” trust, you want the coverage bestie.)
  • -i β€” instead of BMC, runs temporal induction. different mode, different destiny.
  • -m <module_name> β€” names the top module. main character module selection, periodt. πŸ‘‘
  • -s <solver> β€” sets the SMT solver. your choices are z3, cvc4, yices, and mathsat. default: z3. 🌈
  • -v β€” enables debug output. for when you simply must know everything.
  • -p β€” disables the timer display during solving. if watching the clock stresses you out, this one's for you 🫢
  • -d <filename> β€” writes smt2 statements to a file. saving the receipts, fr fr. πŸ“

πŸŽ€ AUTHOR πŸŽ€

this manual page was written by Sebastian Kuzminsky <seb@highlab.com> for the Debian project (and may be used by others). we love a documented legend. πŸ’œ


and that's the whole page bestie!! πŸ’– this was yosys-smtbmc, dated 13 July 2026, and you now know everything it has to offer. go write some SMT2 files and slay. βœ¨πŸ¦‹πŸŽ€ iykyk 🧚

πŸ“¦ where this page comes from