AS(1)

📦

version 2.45.50.20251209 · 5 versions

2.45.50.20251209 · ubuntu resolute, ubuntu stonking (latest)
2.38 · ubuntu jammy
2.40 · debian bookworm
2.41 · ubuntu noble
2.44 · debian trixie

💅 AS(1) — the portable GNU assembler, but make it a whole personality 💅

okay so bestie, welcome to as(1), and yes, that's the page from the GNU Development Tools corner of the manual — section 1, where all the user-facing commands live. this page is long, like genuinely long, but I'm walking you through every single crumb because you deserve to know your assembler the way I know my skincare routine. 🫶

🎀 NAME 🎀

AS — the portable GNU assembler. that's the whole thing, short, iconic, no notes. 👑

✨ SYNOPSIS ✨

here's the entire silhouette of the command, every flag sitting exactly where it lives:

as [-a[cdghilns][=file]]
 [--alternate]
 [--compress-debug-sections] [--nocompress-debug-sections]
 [-D]
 [--dump-config]
 [--debug-prefix-map old=new]
 [--defsym sym=val]
 [--elf-stt-common=[no|yes]]
 [--emulation=name]
 [-f]
 [-g] [--gstabs] [--gstabs+]
 [--gdwarf-<N>] [--gdwarf-sections]
 [--gdwarf-cie-version=VERSION]
 [--generate-missing-build-notes=[no|yes]]
 [--gsframe] [--gsframe=[no|yes]]
 [--hash-size=N]
 [--help] [--target-help]
 [--info] [--no-info]
 [-I dir]
 [-J]
 [-K]
 [--keep-locals]
 [-L]
 [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM]
 [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM]
 [--multibyte-handling=[allow|warn|warn-sym-only]]
 [--no-pad-sections]
 [-o objfile] [-R]
 [--scfi=experimental]
 [--sectname-subst]
 [--size-check=[error|warning]]
 [--statistics]
 [-v] [--verbose]
 [-version] [--version]
 [-W] [--no-warn] [--warn] [--fatal-warnings]
 [-w] [-x]
 [-Z] [@FILE]
 [target-options]
 [--|files ...]

see how it all lines up? [target-options] and then [--|files ...] close the whole thing out at the bottom. the -- there is the classic "okay I'm done with flags, everything after this is a file" move, and @FILE is that little read-my-options-from-a-file situation. we love a tidy synopsis. 🌸

🌈 TARGET 🌈

okay this is the part where the page goes absolutely feral, because every CPU architecture on earth wants a word. each of these is a target option group — you only care about the one that matches the chip you're assembling for, so don't panic, just find your fave and scroll. 💅

🦋 Target AArch64 options

[-EB|-EL]
[-mabi=ABI]

🦋 Target Alpha options

[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]

🦋 Target ARC options

[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]

🦋 Target ARM options

[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
 -mapcs-reentrant]
[-mthumb-interwork] [-k]

🦋 Target Blackfin options

[-mcpu=processor[-sirevision]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]

🦋 Target BPF options

[-EL] [-EB]

🦋 Target CRIS options

[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
[--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]

🦋 Target C-SKY options

[-march=arch] [-mcpu=cpu]
[-EL] [-mlittle-endian] [-EB] [-mbig-endian]
[-fpic] [-pic]
[-mljump] [-mno-ljump]
[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
[-mnolrw ] [-mno-lrw]
[-melrw] [-mno-elrw]
[-mlaf ] [-mliterals-after-func]
[-mno-laf] [-mno-literals-after-func]
[-mlabr] [-mliterals-after-br]
[-mno-labr] [-mnoliterals-after-br]
[-mistack] [-mno-istack]
[-mhard-float] [-mmp] [-mcp] [-mcache]
[-msecurity] [-mtrust]
[-mdsp] [-medsp] [-mvdsp]

(those stray spaces inside [-no-jsri2bsr ] and [-mnolrw ] and [-mlaf ]? yeah, they're really in the original, and I am not touching them, periodt. 🙈)

🦋 Target D10V options

[-O]

🦋 Target D30V options

[-O|-n|-N]

🦋 Target EPIPHANY options

[-mepiphany|-mepiphany16]

🦋 Target H8/300 options

[-h-tick-hex]

🦋 Target i386 options

[--32|--x32|--64] [-n]
[-march=CPU[+EXTENSION...]] [-mtune=CPU]

🦋 Target IA-64 options

[-mconstant-gp|-mauto-pic]
[-milp32|-milp64|-mlp64|-mp64]
[-mle|mbe]
[-mtune=itanium1|-mtune=itanium2]
[-munwind-check=warning|-munwind-check=error]
[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
[-x|-xexplicit] [-xauto] [-xdebug]

🦋 Target IP2K options

[-mip2022|-mip2022ext]

🦋 Target M32C options

[-m32c|-m16c] [-relax] [-h-tick-hex]

🦋 Target M32R options

[--m32rx|--[no-]warn-explicit-parallel-conflicts|
--W[n]p]

🦋 Target M680X0 options

[-l] [-m68000|-m68010|-m68020|...]

🦋 Target M68HC11 options

[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branches] [--short-branches]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]

🦋 Target MCORE options

[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]

🦋 Target Meta options

[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
[-mlittle-endian] [-mbig-endian]

okay so real talk: the original page genuinely runs the Meta line straight into Target MICROBLAZE options: with no line break in between, so that's exactly how I'm leaving it. love a little formatting chaos, it's giving ✨ authentic ✨.

🦋 Target MIPS options

[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot [-mvxworks-pic]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-mfp64] [-mgp64] [-mfpxx]
[-modd-spreg] [-mno-odd-spreg]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
[-mips64r3] [-mips64r5] [-mips64r6]
[-construct-floats] [-no-construct-floats]
[-mignore-branch-isa] [-mno-ignore-branch-isa]
[-mnan=encoding]
[-trap] [-no-break] [-break] [-no-trap]
[-mips16] [-no-mips16]
[-mmips16e2] [-mno-mips16e2]
[-mmicromips] [-mno-micromips]
[-msmartmips] [-mno-smartmips]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdsp] [-mno-dsp]
[-mdspr2] [-mno-dspr2]
[-mdspr3] [-mno-dspr3]
[-mmsa] [-mno-msa]
[-mxpa] [-mno-xpa]
[-mmt] [-mno-mt]
[-mmcu] [-mno-mcu]
[-mcrc] [-mno-crc]
[-mginv] [-mno-ginv]
[-mloongson-mmi] [-mno-loongson-mmi]
[-mloongson-cam] [-mno-loongson-cam]
[-mloongson-ext] [-mno-loongson-ext]
[-mloongson-ext2] [-mno-loongson-ext2]
[-minsn32] [-mno-insn32]
[-mfix7000] [-mno-fix7000]
[-mfix-rm7000] [-mno-fix-rm7000]
[-mfix-vr4120] [-mno-fix-vr4120]
[-mfix-vr4130] [-mno-fix-vr4130]
[-mfix-r5900] [-mno-fix-r5900]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]

MIPS really said "hold my boba" and then listed like forty things. respect. 😭

🦋 Target MMIX options

[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]

🦋 Target NDS32 options

[-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
[-misa=isa] [-mabi=abi] [-mall-ext]
[-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
[-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
[-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
[-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
[-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
[-mb2bb]

🦋 Target PDP11 options

[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]

🦋 Target picoJava options

[-mb|-me]

🦋 Target PowerPC options

[-a32|-a64]
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
[-many] [-maltivec|-mvsx|-mhtm|-mvle]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
[-nops=count]

🦋 Target PRU options

[-link-relax]
[-mnolink-relax]
[-mno-warn-regname-label]

🦋 Target RISC-V options

[-fpic|-fPIC|-fno-pic]
[-march=ISA|Profiles|Profiles_ISA]
[-mabi=ABI]
[-mlittle-endian|-mbig-endian]

🦋 Target RL78 options

[-mg10]
[-m32bit-doubles|-m64bit-doubles]

🦋 Target RX options

[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]

🦋 Target s390 options

[-m31|-m64] [-mesa|-mzarch] [-march=CPU]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]
[-mwarn-regtype-mismatch=strict
 -mwarn-regtype-mismatch=relaxed
 -mwarn-regtype-mismatch=no
 -mno-warn-regtype-mismatch]

🦋 Target SCORE options

[-EB][-EL][-FIXDD][-NWARN]
[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
[-march=score7][-march=score3]
[-USE_R1][-KPIC][-O0][-G num][-V]

🦋 Target SPARC options

[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
 -Asparcvisr|-Asparc5]
[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
 -bump]
[-32|-64]
[--enforce-aligned-data][--dcti-couples-detect]

🦋 Target TIC54X options

[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]

🦋 Target TIC6X options

[-march=arch] [-mbig-endian|-mlittle-endian]
[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
[-mpic|-mno-pic]

🦋 Target TILE-Gx options

[-m32|-m64][-EB][-EL]

🦋 Target Visium options

[-mtune=arch]

🦋 Target Xtensa options

[--[no-]text-section-literals] [--[no-]auto-litpools]
[--[no-]absolute-literals]
[--[no-]target-align] [--[no-]longcalls]
[--[no-]transform]
[--rename-section oldname=newname]
[--[no-]trampolines]
[--abi-windowed|--abi-call0]

🦋 Target Z80 options

[-march=CPU[-EXT][+EXT]]
[-local-prefix=PREFIX]
[-colonless]
[-sdcc]
[-fp-s=FORMAT]
[-fp-d=FORMAT]

and that's where part 1 wraps up bestie — the name, the synopsis, and literally every target on the roster. keep scrolling because there is so much more where this came from and I am not done hyping you through it. 🧚✨

💖 DESCRIPTION 💖

okay so real talk: GNU as is not just one assembler, it's literally a whole family of assemblers 🫶. If you've used the GNU assembler on one architecture, bestie, you're gonna feel right at home on another one — the environment is lowkey the same vibe. Every version has a ton in common with the others, like object file formats, most assembler directives (which we also call pseudo-ops, iykyk), and assembler syntax. It's giving consistent ✨.

as is primarily meant to assemble the output of the GNU C compiler gcc so the linker ld can do its thing. But ngl, they really tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions? Documented explicitly, no cap. That said, this does NOT mean as always uses the same syntax as another assembler for the same architecture — for example, we know of several incompatible versions of 680x0 assembly language syntax 💀.

Every single time you run as, it assembles exactly one source program. That source program is made up of one or more files. (And yes, the standard input counts as a file too, iconic.)

You hand as a command line with zero or more input file names. The input files get read left to right, bestie. A command-line argument (in any position) that doesn't have a special meaning? It's taken as an input file name. Periodt.

If you give as no file names at all, it attempts to read one input file from the as standard input, which is normally your terminal. You might have to type ctl-D to tell as there's no more program to assemble 🙈.

Use -- if you need to explicitly name the standard input file in your command line. (Yes, fr fr.)

If the source is empty, as produces a small, empty object file. Cute. Minimalist. Slay.

as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly. So like, a warning is "we're still going bestie 🥲" and an error is "we are SO done 💀".

If you're invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and from the -Wa) by commas. For example:

gcc -c -g -O -Wa,-alh,-L file.c

This passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table). Obsessed with a little passthrough moment ✨.

Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.) 👑

✨ OPTIONS ✨

@file — Read command-line options from file. The options read are inserted in place of the original @file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed. Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively. (It's giving inception 🌀)
-a[cdghilmns] — Turn on listings, in any of a variety of ways:
- -ac — omit false conditionals
- -ad — omit debugging directives
- -ag — include general information, like as version and options passed
- -ah — include high-level source
- -al — include assembly
- -ali — include assembly with ginsn
- -am — include macro expansions
- -an — omit forms processing
- -as — include symbols
- =file — set the name of the listing file

You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls. Mix and match, bestie 🎀

--alternate — Begin in alternate macro mode.
--compress-debug-sections — Compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities. Note: if compression would make a given section larger, then it is not compressed. (Sensible 💅)
--compress-debug-sections=none
--compress-debug-sections=zlib
--compress-debug-sections=zlib-gnu
--compress-debug-sections=zlib-gabi
--compress-debug-sections=zstd — These options control how DWARF debug sections are compressed. --compress-debug-sections=none is equivalent to --nocompress-debug-sections. --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to --compress-debug-sections. --compress-debug-sections=zlib-gnu compresses DWARF debug sections using the obsoleted zlib-gnu format. The debug sections are renamed to begin with .zdebug. --compress-debug-sections=zstd compresses DWARF debug sections using zstd. Note: if compression would actually make a section larger, then it is not compressed nor renamed.
--nocompress-debug-sections — Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.
-D — Enable debugging in target specific backends, if supported. Otherwise ignored. Even if ignored, this option is accepted for script compatibility with calls to other assemblers.
--debug-prefix-map old=new — When assembling files in directory old, record debugging information describing them as in new instead.
--defsym sym=value — Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a .set pseudo-op.
--dump-config — Displays how the assembler is configured and then exits. (Receipts 🧾)
--elf-stt-common=no
--elf-stt-common=yes — These options control whether the ELF assembler should generate common symbols with the STT_COMMON type. The default can be controlled by a configure option --enable-elf-stt-common.
--emit-local-absolute — Emit even pre-defined (local) absolute symbols to the outgoing symbol table. Note that this isn't the exact opposite of --strip-local-absolute. (Careful, bestie, it's close but not exactly the mirror 🙈)
--emulation=name — If the assembler is configured to support multiple different target configurations then this option can be used to select the desired form.
-f — "fast" — skip whitespace and comment preprocessing (assume source is compiler output).
-g
--gen-debug — Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a .debug_info and .debug_line section is only emitted when the assembly file doesn't generate one itself.
--gstabs — Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
--gstabs+ — Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program 😭. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time.

⚠️ heads up: --gstabs+ is the spicy one — those GNU extensions can genuinely make other debuggers crash or refuse to read your program. gdb only, bestie.

--gdwarf-2 — Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note — this option is only supported by some targets, not all of them.
--gdwarf-3 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
--gdwarf-4 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
--gdwarf-5 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
--gdwarf-sections — Instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. For example a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. If the code section is just called .text then debug line section will still be called just .debug_line without any suffix.
--gdwarf-cie-version=version — Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specified the default is version 1, though some targets can modify this default. Other possible values for version are 3 or 4.
--generate-missing-build-notes=yes
--generate-missing-build-notes=no — These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the --enable-generate-build-notes configure option.
--gsframe
--gsframe
--gsframe=no
--gsframe=yes — Create .sframe section from CFI directives. The explicit --gsframe=yes option behaves the same as --gsframe. Generation can be suppressed with --gsframe=no. The default can be controlled by a configure option --enable-default-sframe.
--hash-size N — Ignored. Supported for command line compatibility with other assemblers. (It's just there for the vibes 🌈)
--help — Print a summary of the command-line options and exit.
--target-help — Print a summary of all target specific options and exit.
--info — Don't suppress informational messages.
--no-info — Suppress informational messages.
-I dir — drops dir into the search list for .include directives, so your include-hunting has more places to look 💅
-J — do NOT warn about signed overflow. just… letting it vibe 🙈
-K — warns you when difference tables got altered for long displacements.
-L, --keep-locals — keeps local symbols in the symbol table. these cuties start with system-specific local label prefixes, typically .L for ELF systems or L for traditional a.out systems. keeping them, no cap ✨
--listing-lhs-width=number — sets the max width, in words, of the output data column for an assembler listing to number.
--listing-lhs-width2=number — same energy but for continuation lines in an assembler listing — max width in words of the output data column, set to number.
--listing-rhs-width=number — sets the max width of an input source line as shown in a listing, measured in number bytes.
--listing-cont-lines=number — sets the max number of lines printed in a listing for a single line of input to number + 1.
--multibyte-handling=allow
--multibyte-handling=warn
--multibyte-handling=warn-sym-only
--multibyte-handling=warn_sym_only — this whole lil family controls how the assembler deals with multibyte characters in the input. the default — which you can bring back by passing the allow argument — is to just allow those characters, zero complaints. passing warn makes the assembler generate a warning message every single time any multibyte character shows up. passing warn-sym-only only generates a warning when a symbol is defined with a name containing multibyte characters. (references to undefined symbols will not generate a warning.) 🫶
--no-pad-sections — tells the assembler to stop padding the ends of output sections to the alignment of that section. the default is to pad the sections, but that can waste space which might be needed on targets with tight memory constraints. 💀
-o objfile — names the object-file output from as objfile. that's the one, bestie.
-R — folds the data section into the text section.
--reduce-memory-overheads — ignored. it's supported for compatibility with tools that pass the same option to both the assembler and the linker. it's giving legacy 🎀
--scfi=experimental — controls whether the assembler should synthesize CFI for hand-written input. if the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning. note that --scfi=experimental is not intended to be used for compiler-generated code, including inline assembly. this experimental support is work in progress. only System V AMD64 ABI is supported.

each input function in assembly must begin with the .type directive, and should ideally be closed off using a .size directive. when using SCFI, each .type directive prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry). this implies that with each .type directive, a previous block of instructions, if any, is finalised as a distinct FDE. 👑

--sectname-subst — honors substitution sequences in section names. fancy ✨
--size-check=error
--size-check=warning — issues an error or a warning for an invalid ELF .size directive. pick your drama level.
--statistics — prints the maximum space (in bytes) and total time (in seconds) used by assembly. receipts 📊
--strip-local-absolute — removes local absolute symbols from the outgoing symbol table.
-v, --verbose — prints the as version.
--version, -version — prints the as version and exits. bye bestie 👋
-W, --no-warn — suppresses warning messages. shhh 🤫
--warn — don't suppress warning messages, and don't treat them as errors either.
--fatal-warnings — treats warnings as errors. no chill mode 😭
-w — ignored.
-x — ignored.
-Z — generates an object file even after errors. bold move, honestly 🔥
-- files ... — standard input, or source files to assemble.

The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). 🦋

-EB — this option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.
-EL — this option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.
-mabi=abi — specifies which ABI the source code uses. the recognized arguments are: ilp32 and lp64, which decide the generated object file in ELF32 and ELF64 format respectively. the default is lp64.
-mcpu=processor[+extension...] — this option specifies the target processor. the assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. the following processor names are recognized: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a510, cortex-a520, cortex-a710, cortex-a720, ares, exynos-m1, falkor, neoverse-n1, neoverse-n2, neoverse-e1, neoverse-v1, qdf24xx, saphira, thunderx, vulcan, xgene1 xgene2, cortex-r82, cortex-x1, cortex-x2, cortex-x3, and cortex-x4. the special name all may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions.

in addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.

if some implementations of a particular processor can have an extension, then then those extensions are automatically enabled. consequently, you will not normally have to specify any additional extensions. 💅

-march=architecture[+extension...] — this option specifies the target architecture. the assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. the following architecture names are recognized: armv8-a, armv8.1-a, armv8.2-a, armv8.3-a, armv8.4-a armv8.5-a, armv8.6-a, armv8.7-a, armv8.8-a, armv8.9-a, armv8-r, armv9-a, armv9.1-a, armv9.2-a, armv9.3-a, armv9.4-a and armv9.5-a.

if both -mcpu and -march are specified, the assembler will use the setting for -mcpu. if neither are specified, the assembler will default to -mcpu=all.

the architecture option can be extended with the same instruction set extension options as the -mcpu option. unlike -mcpu, extensions are not always enabled by default. 🙈

-mverbose-error — this option enables verbose error messages for AArch64 gas. this option is enabled by default.
-mno-verbose-error — this option disables verbose error messages in AArch64 gas.
-menable-sysreg-checking — this option enables error messages that are issued if an attempt is made to assemble a system register access which will not execute on the target architecture.

The following options are available when as is configured for an Alpha processor. ⭐

-mcpu — this option specifies the target processor. if an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. this option is equivalent to the .arch directive.

the following processor names are recognized: 21064, 21064a, 21066, 21068, 21164, 21164a, 21164pc, 21264, 21264a, 21264b, ev4, ev5, lca45, ev5, ev56, pca56, ev6, ev67, ev68. the special name all may be used to allow the assembler to accept instructions valid for any Alpha processor.

in order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the electro-vlasic names (e.g. ev4) do not.

-mdebug
-no-mdebug — enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. the default is to automatically enable .mdebug when the first stabs directive is seen.
-relax — this option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. however, the option can still be useful in specific applications.
-replace
-noreplace — enables or disables the optimization of procedure calls, both at assemblage and at link time. these options are only available for VMS targets and -replace is the default. see section 1.4.1 of the OpenVMS Linker Utility Manual.
-g — this option is used when the compiler generates debug information. when gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. otherwise this option has no effect.
-Gsize — a local common symbol larger than size is placed in .bss, while smaller symbols are placed in .sbss.
-F
-32addr — these options are ignored for backward compatibility.

The following options are available when as is configured for an ARC processor. 🌈

-mcpu=cpu — this option selects the core processor variant.
-EB | -EL — select either big-endian (-EB) or little-endian (-EL) output.
-mcode-density — enable Code Density extension instructions. packing it in 📦

The following options are available when as is configured for the ARM processor family. 🎀

-mcpu=processor[+extension...] — specify which ARM processor variant is the target.
-march=architecture[+extension...] — specify which ARM architecture variant is used by the target.
-mfpu=floating-point-format — select which Floating Point architecture is the target.
-mfloat-abi=abi — select which floating point ABI is in use.
-mthumb — enable Thumb only instruction decoding.
-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant — select which procedure calling convention is in use.
-EB | -EL — select either big-endian (-EB) or little-endian (-EL) output.
-mthumb-interwork — specify that the code has been generated with interworking between Thumb and ARM code in mind.
-mccs — flips on CodeComposer Studio assembly syntax compatibility mode 💅
-k — announces that PIC code has been generated. that's it, that's the whole vibe ✨

okay bestie, when as is built for the Blackfin processor family, here's the menu you're working with:

-mcpu=processor[-sirevision] — picks your target processor. the optional sirevision part? the assembler genuinely does not use it — it's just sitting there so GCC can casually pass its -mcpu= option down the line. if you try to assemble an instruction that won't actually execute on the target processor, the assembler will hit you with an error message. the processor names it recognizes are: "bf504", "bf506", "bf512", "bf514", "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526", "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not implemented yet, sad), "bf536", "bf537", "bf538", "bf539", "bf542", "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m", "bf549", "bf549m", "bf561", and "bf592".
-mfdpic — assemble for the FDPIC ABI.
-mno-fdpic, -mnopic — disables -mfdpic. bye felicia 🫶

and when as is configured for the Linux kernel BPF processor family, you get these:

🌈 @chapter BPF Dependent Features

🦋 BPF Options

-EB — tells the assembler to emit big-endian eBPF.
-EL — tells the assembler to emit little-endian eBPF.
-mdialect=dialect — picks which assembly language dialect the assembler should recognize while assembling. it supports normal and pseudoc.
-misa-spec=spec — picks which version of the BPF instruction set to use while assembling. the supported BPF ISA versions are v1, v2, v3 and v4.

you can also pass the value xbpf to recognize extra instructions that GCC uses for testing purposes. but ⚠️ beware — this is not valid BPF.

-mno-relax — tells the assembler to not relax instructions.

heads up: if you don't specify any endianness option on the command line, the host endianness gets used. also, for documentation of the CRIS-specific options, go see the info pages 👀

now for the C-SKY processor family, when as is configured for it:

-march=archname — assemble for architecture archname. the --help option lists valid values for archname.
-mcpu=cpuname — assemble for architecture cpuname. the --help option lists valid values for cpuname.
-EL, -mlittle-endian — generate little-endian output.
-EB, -mbig-endian — generate big-endian output.
-fpic, -pic — generate position-independent code.
-mljump, -mno-ljump — enable/disable transformation of the short branch instructions "jbf", "jbt", and "jbr" to "jmpi". this one is for V2 processors only. it gets ignored on CK801 and CK802 targets, which don't support the "jmpi" instruction at all, and it's enabled by default for other processors.
-mbranch-stub, -mno-branch-stub — pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr" instructions to the linker.

this option is only available for bare-metal C-SKY V2 ELF targets, where it's enabled by default. 🚨 it cannot be used in code that will be dynamically linked against shared libraries.

-force2bsr, -mforce2bsr, -no-force2bsr, -mno-force2bsr — enable/disable transformation of "jbsr" instructions to "bsr". this option is always enabled (and -mno-force2bsr is ignored) for CK801/CK802 targets. it's also always enabled when -mbranch-stub is in effect.
-jsri2bsr, -mjsri2bsr, -no-jsri2bsr, -mno-jsri2bsr — enable/disable transformation of "jsri" instructions to "bsr". enabled by default, bestie.
-mnolrw, -mno-lrw — enable/disable transformation of "lrw" instructions into a "movih"/"ori" pair.
-melrw, -mno-elrw — enable/disable extended "lrw" instructions. this one's enabled by default for CK800-series processors.
-mlaf, -mliterals-after-func, -mno-laf, -mno-literals-after-func — enable/disable placement of literal pools after each function.
-mlabr, -mliterals-after-br, -mno-labr, -mnoliterals-after-br — enable/disable placement of literal pools after unconditional branches. enabled by default.
-mistack, -mno-istack — enable/disable interrupt stack instructions. enabled by default on CK801, CK802, and CK802 processors.

the following options explicitly enable certain optional instructions. these features are also enabled implicitly by using -mcpu= to specify a processor that supports it.

-mhard-float — enable hard float instructions.
-mmp — enable multiprocessor instructions.
-mcp — enable coprocessor instructions.
-mcache — enable cache prefetch instruction.
-msecurity — enable C-SKY security instructions.
-mtrust — enable C-SKY trust instructions.
-mdsp — enable DSP instructions.
-medsp — enable enhanced DSP instructions.
-mvdsp — enable vector DSP instructions.

when as is configured for an Epiphany processor:

-mepiphany — specifies that both 32 and 16 bit instructions are allowed. this is the default behavior.
-mepiphany16 — restricts the permitted instructions to just the 16 bit set.

when as is configured for an H8/300 processor:

🌸 @chapter H8/300 Dependent Features

Options

the Renesas H8/300 version of "as" has one machine-dependent option:

-h-tick-hex — support H'00 style hex constants in addition to 0x00 style.
-mach=name — sets the H8300 machine variant. the following machine names are recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and "h8300sxn".

and when as is configured for an i386 processor, it's giving:

--32 | --x32 | --64 — select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.

these options are only available with the ELF object file format, and they require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure to enable 64-bit usage and use x86-64 as target platform).

-n — by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. this switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.
--divide — on SVR4-derived platforms, the character / is treated as a comment character, which means it cannot be used in expressions. the --divide option turns / into a normal character. this does not disable / at the beginning of a line starting a comment, and it doesn't affect using # for starting a comment either.
-march=CPU[+EXTENSION...] — specifies the target processor. the assembler will issue an error message if you attempt to assemble an instruction which will not execute on the target processor. recognized processor names: "i8086", "i186", "i286", "i386", "i486", "i586", "i686", "pentium", "pentiumpro", "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona", "core", "core2", "corei7", "iamcu", "k6", "k6_2", "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2", "bdver3", "bdver4", "znver1", "znver2", "znver3", "znver4", "znver5", "znver6", "btver1", "btver2", "generic32" and "generic64".

on top of the basic instruction set, the assembler can be told to accept various extension mnemonics. for example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. the currently supported extensions are: 8087, 287, 387, 687, "cmov", "fxsr", "mmx", "sse", "sse2", "sse3", "sse4a", "ssse3", "sse4.1", "sse4.2", "sse4", "avx", "avx2", "lahf_sahf", "monitor", "adx", "rdseed", "prfchw", "smap", "mpx", "sha", "rdpid", "ptwrite", "cet", "gfni", "vaes", "vpclmulqdq", "prefetchwt1", "clflushopt", "se1", "clwb", "movdiri", "movdir64b", "enqcmd", "serialize", "tsxldtrk", "kl", "widekl", "hreset", "avx512f", "avx512cd", "avx512er", "avx512pf", "avx512vl", "avx512bw", "avx512dq", "avx512ifma", "avx512vbmi", "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq", "avx512_vbmi2", "avx512_vnni", "avx512_bitalg", "avx512_vp2intersect", "tdx", "avx512_bf16", "avx_vnni", "avx512_fp16", "avx512_bmm", "prefetchi", "avx_ifma", "avx_vnni_int8", "cmpccxadd", "wrmsrns", "msrlist", "avx_ne_convert", "rao_int", "fred", "lkgs", "avx_vnni_int16", "sha512", "sm3", "sm4", "pbndkb", "avx10.1", "avx10.1/512", "avx10.1/256", "avx10.1/128", "user_msr", "msr_imm", "apx_f", "apx_nci", "apx_ndd", "apx_nf", "apx_nci_ndd_nf", "avx10.2", "avx10.2/512", "avx10.2/256", "avx10.2/128", "movrs", "amx_int8", "amx_bf16", "amx_fp16", "amx_complex", "amx_transpose", "amx_tf32", "amx_fp8" "amx_movrs", "amx_avx512", "amx_tile", "vmx", "vmfunc", "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes", "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe", "ept", "lzcnt", "popcnt", "hle", "rtm", "tsx", "invpcid", "clflush", "mwaitx", "clzero", "wbnoinvd", "pconfig", "waitpkg", "uintr", "cldemote", "rdpru", "mcommit", "sev_es", "lwp", "fma4", "xop", "cx16", "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5", "snp", "invlpgb", "tlbsync", "rmpquery", "rmpread", "svme", "gmism2", "gmiccs", "padlockrng2", "padlockphe2", "padlockxmodx" and "padlock". note that these extension mnemonics can be prefixed with "no" to revoke the respective (and any dependent) functionality. note further that the suffixes permitted on -march=avx10.<N> enforce a vector length restriction, i.e. despite these otherwise being "enabling" options, using these suffixes will disable all insns with wider vector or mask register operands.

when the .arch directive is used with -march, the .arch directive will take precedent.

-mtune=CPU — specifies a processor to optimize for. when used in conjunction with the -march option, only instructions of the processor specified by the -march option will be generated.

valid CPU values are identical to the processor list of -march=CPU.

-moperand-check=none, -moperand-check=warning, -moperand-check=error — bestie these three control whether the assembler does certain instruction operand or operand-combo checks. Like, imagine an instruction where the operand size literally cannot be inferred from its operands and nobody bothered to specify it with an instruction suffix — that's the vibe. -moperand-check=none = no checks, we simply do not look 💅. -moperand-check=warning = issue a warning when the checks fail, and this is the default. -moperand-check=error = full on error when the checks fail, no cap.
-msse2avx — says the assembler should encode SSE instructions with a VEX prefix, which means you need AVX to be available, periodt. And SSE instructions using extended GPRs get encoded with an EVEX prefix, which means you need AVX512 or AVX10 to be available. Iconic but demanding. 👑
-muse-unaligned-vector-move — tells the assembler to encode aligned vector move as unaligned vector move. That's it, that's the whole thing.
-msse-check=none, -msse-check=warning, -msse-check=error — these control whether the assembler checks SSE instructions. -msse-check=none = it does not check SSE instructions, which is the default (chill). -msse-check=warning = issue a warning for any SSE instruction. -msse-check=error = issue an error for any SSE instruction (dramatic 💀).
-mavxscalar=128, -mavxscalar=256 — how the assembler encodes scalar AVX instructions. -mavxscalar=128 encodes scalar AVX instructions with 128bit vector length, which is the default. -mavxscalar=256 encodes them with 256bit vector length.

⚠️ WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. Not me warning you twice, bestie, but here we are. 😭

-mvexwig=0, -mvexwig=1 — how the assembler encodes VEX.W-ignored (WIG) VEX instructions. -mvexwig=0 encodes WIG VEX instructions with vex.w = 0, which is the default. -mvexwig=1 will encode WIG EVEX instructions with vex.w = 1. (Yes it says EVEX in that last one, we're just reporting the facts, no editing, that's the assignment 🫶.)

⚠️ WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. Again!! 🚨

-mevexlig=128, -mevexlig=256, -mevexlig=512 — how the assembler encodes length-ignored (LIG) EVEX instructions. -mevexlig=128 encodes LIG EVEX instructions with 128bit vector length, which is the default. -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions with 256bit and 512bit vector length, respectively. Big girl vector lengths ✨
-mevexwig=0, -mevexwig=1 — how the assembler encodes w-ignored (WIG) EVEX instructions. -mevexwig=0 encodes WIG EVEX instructions with evex.w = 0, which is the default. -mevexwig=1 will encode WIG EVEX instructions with evex.w = 1.
-mmnemonic=att, -mmnemonic=intel — specifies the instruction mnemonic used for matching instructions. Heads up: the .att_mnemonic and .intel_mnemonic directives will take precedent. iykyk 🎀
-msyntax=att, -msyntax=intel — specifies the instruction syntax when processing instructions. And again, the .att_syntax and .intel_syntax directives will take precedent.
-mnaked-reg — specifies that registers don't require a % prefix. And (you guessed it) the .att_syntax and .intel_syntax directives will take precedent.
-madd-bnd-prefix — forces the assembler to add a BND prefix to all branches, even if that prefix was never explicitly specified in the source code. Adding things you didn't ask for, main character energy fr fr 💅
-mno-shared — on ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The -mshared option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions. Lowkey a whole paragraph, but every word matters. 🌸
-mbig-obj — on PE/COFF target this option forces the use of the big object file format, which allows more than 32768 sections. Big object, big energy. 👑
-momit-lock-prefix=no, -momit-lock-prefix=yes — how the assembler encodes the lock prefix. This option is a workaround for processors that fail on the lock prefix. It can only be safely used with single-core, single-thread computers. -momit-lock-prefix=yes will omit all lock prefixes. -momit-lock-prefix=no will encode the lock prefix as usual, which is the default.

⚠️ The safety note is not a joke bestie — single-core, single-thread only, we said what we said.

-mfence-as-lock-add=no, -mfence-as-lock-add=yes — how the assembler encodes lfence, mfence and sfence. -mfence-as-lock-add=yes will encode lfence, mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will encode lfence, mfence and sfence as usual, which is the default.
-mrelax-relocations=no, -mrelax-relocations=yes — whether the assembler should generate relax relocations, R_386_GOT32X in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX in 64-bit mode. -mrelax-relocations=yes will generate relax relocations. -mrelax-relocations=no will not generate relax relocations. Simple as that, no notes. 🦋
-mtls-check=no, -mtls-check=yes — whether the assembler checks tls relocation. -mtls-check=yes will check tls relocation. -mtls-check=no will not check tls relocation. The default can be controlled by a configure option --enable-x86-tls-check. 🧚
-malign-branch-boundary=NUM — controls how the assembler should align branches with segment prefixes or NOP. NUM must be a power of 2. It should be 0 or no less than 16. Branches will be aligned within NUM byte boundary. -malign-branch-boundary=0, which is the default, doesn't align branches. Math girlies rise ✨
-malign-branch=TYPE[+TYPE...] — specifies types of branches to align. TYPE is a combination of jcc, which aligns conditional jumps, fused, which aligns fused conditional jumps, jmp, which aligns unconditional jumps, call which aligns calls, ret, which aligns rets, indirect, which aligns indirect jumps and calls. The default is -malign-branch=jcc+fused+jmp. Mix and match, bestie 🎀
-malign-branch-prefix-size=NUM — specifies the maximum number of prefixes on an instruction to align branches. NUM should be between 0 and 5. The default NUM is 5.
-mbranches-within-32B-boundaries — aligns conditional jumps, fused conditional jumps and unconditional jumps within 32 byte boundary with up to 5 segment prefixes on an instruction. It is equivalent to -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5. The default doesn't align branches. One flag doing three flags' job, we love an overachiever 💅
-mlfence-after-load=no, -mlfence-after-load=yes — whether the assembler should generate lfence after load instructions. -mlfence-after-load=yes will generate lfence. -mlfence-after-load=no will not generate lfence, which is the default.
-mlfence-before-indirect-branch=none, -mlfence-before-indirect-branch=all, -mlfence-before-indirect-branch=register, -mlfence-before-indirect-branch=memory — whether the assembler should generate lfence before indirect near branch instructions. Let's break it down, babes:
- -mlfence-before-indirect-branch=all will generate lfence before indirect near branch via register and issue a warning before indirect near branch via memory. It also implicitly sets -mlfence-before-ret=shl when there's no explicit -mlfence-before-ret=.
- -mlfence-before-indirect-branch=register will generate lfence before indirect near branch via register.
- -mlfence-before-indirect-branch=memory will issue a warning before indirect near branch via memory.
- -mlfence-before-indirect-branch=none will not generate lfence nor issue a warning, which is the default.
- Note that lfence won't be generated before indirect near branch via register with -mlfence-after-load=yes since lfence will be generated after loading branch target register. Important lore, don't skip it 📖
-mlfence-before-ret=none, -mlfence-before-ret=shl, -mlfence-before-ret=or, -mlfence-before-ret=yes, -mlfence-before-ret=not — whether the assembler should generate lfence before ret. -mlfence-before-ret=or will generate generate or instruction with lfence. -mlfence-before-ret=shl/yes will generate shl instruction with lfence. -mlfence-before-ret=not will generate not instruction with lfence. -mlfence-before-ret=none will not generate lfence, which is the default. (And yes, "generate generate" is in there, we keep it real, we don't fix the original 🫶)
-mx86-used-note=no, -mx86-used-note=yes — whether the assembler should generate GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes. The default can be controlled by the --enable-x86-used-note configure option.
-mevexrcig=rne, -mevexrcig=rd, -mevexrcig=ru, -mevexrcig=rz — how the assembler encodes SAE-only EVEX instructions. -mevexrcig=rne will encode RC bits of EVEX instruction with 00, which is the default. -mevexrcig=rd, -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX instructions with 01, 10 and 11 RC bits, respectively. Two bits, four moods 🌈
-mamd64, -mintel64 — specifies that the assembler should accept only AMD64 or Intel64 ISA in 64-bit mode. The default is to accept common, Intel64 only and AMD64 ISAs. Pick a side, or don't — the default is everybody 🦋
-O0 | -O | -O1 | -O2 | -Os — optimize instruction encoding with smaller instruction size. -O and -O1 encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with 32-bit register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions, encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions, and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical. Shrinking instructions is the whole aesthetic, slay 💅
-O2 — this is -O1 optimization plus it encodes 256-bit/512-bit EVEX vector register clearing instructions using 128-bit EVEX vector register clearing instructions ✨ (yes bestie, smaller is cuter). In 64-bit mode, VEX encoded instructions with commutative source operands also get their source operands swapped, but only if that lets us use the 2-byte VEX prefix form instead of the 3-byte one. And certain forms of AND, plus OR, where the same (register) operand is specified twice, get changed to TEST. glow up 💅
-Os — -O2 optimization plus it encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. And -O0 turns this optimization off 🚫

The following options are available when `as` is configured for the Ubicom IP2K series.

-mip2022ext — says the extended IP2022 instructions are allowed 🎀
-mip2022 — restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones 🔒

The following options are available when `as` is configured for the Renesas M32C and M16C processors.

-m32c — assemble M32C instructions 🌸
-m16c — assemble M16C instructions (this one is the default) 💖
-relax — enable support for link-time relaxations 😌
-h-tick-hex — support H'00 style hex constants in addition to 0x00 style ✨

The following options are available when `as` is configured for the Renesas M32R (formerly Mitsubishi M32R) series.

--m32rx — specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX 👑
--warn-explicit-parallel-conflicts or --Wp — produce warning messages when questionable parallel constructs are encountered 👀
--no-warn-explicit-parallel-conflicts or --Wnp — do not produce warning messages when questionable parallel constructs are encountered 🙈

The following options are available when `as` is configured for the Motorola 68000 series.

-l — shorten references to undefined symbols, to one word instead of two ✂️
-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 — specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time 🛠️
-m68881 | -m68882 | -mno-68881 | -mno-68882 — the target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor 🧮
-m68851 | -mno-68851 — the target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up 🧠

For details about the PDP-11 machine dependent features options, see PDP-11-Options.

-mpic | -mno-pic — generate position-independent (or position-dependent) code. The default is -mpic 🌈
-mall
-mall-extensions — enable all instruction set extensions. This is the default. 💖
-mno-extensions — disable all instruction set extensions 🚫
-mextension | -mno-extension — enable (or disable) a particular instruction set extension ✨
-mcpu — enable the instruction set extensions supported by a particular CPU, and disable all other extensions 👑
-mmachine — enable the instruction set extensions supported by a particular machine model, and disable all other extensions 🏗️

The following options are available when `as` is configured for a picoJava processor.

-mb — generate "big endian" format output 🐘
-ml — generate "little endian" format output 🐭

The following options are available when `as` is configured for a PRU processor.

-mlink-relax — assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LD would shorten the LDI32 instruction to a single LDI. In such case as will output DIFF relocations for diff expressions 🎯
-mno-link-relax — assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted 🙅
-mno-warn-regname-label — do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off 🤐

The following options are available when `as` is configured for a MIPS processor.

-G num — this option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8 💫
-EB — generate "big endian" format output 🐘
-EL — generate "little endian" format output 🐭
-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips32r3
-mips32r5
-mips32r6
-mips64
-mips64r2
-mips64r3
-mips64r5
-mips64r6 — generate code for a particular MIPS Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively 👑
-march=cpu — generate code for a particular MIPS CPU 🏗️
-mtune=cpu — schedule and tune for a particular MIPS CPU 🎵
-mfix7000
-mno-fix7000 — cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions 🩹
-mfix-rm7000
-mno-fix-rm7000 — cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction 🩹
-mfix-r5900
-mno-fix-r5900 — do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a nop instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip 💀

bestie this one is a real hardware bug, not a vibe — that's why the workaround exists 🙈

-mdebug
-no-mdebug — cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections 🐛
-mpdr
-mno-pdr — control generation of .pdr sections 📄
-mgp32
-mfp32 — the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers ✨
-mgp64
-mfp64 — the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times. -mgp64 controls the size of general-purpose registers and -mfp64 controls the size of floating-point registers ✨
-mfpxx — the register sizes are normally inferred from the ISA and ABI, but using this flag in combination with -mabi=32 enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide 🎀
-modd-spreg
-mno-odd-spreg — enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA. -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg 💅
-mips16
-no-mips16 — generate code for the MIPS 16 processor. This is equivalent to putting .module mips16 at the start of the assembly file. -no-mips16 turns off this option 🎯
-mmips16e2
-mno-mips16e2 — enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting .module mips16e2 at the start of the assembly file. -mno-mips16e2 turns off this option 🎯
-mmicromips
-mno-micromips — generate code for the microMIPS processor. This is equivalent to putting .module micromips at the start of the assembly file. -mno-micromips turns off this option. This is equivalent to putting .module nomicromips at the start of the assembly file 🎯
-msmartmips
-mno-smartmips — enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting .module smartmips at the start of the assembly file. -mno-smartmips turns off this option 🧠
-mips3d
-no-mips3d — generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option 🧊
-mdmx
-no-mdmx — generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option ✨
-mdsp
-mno-dsp — generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option 🎛️
-mdspr2
-mno-dspr2 — generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option 🎛️
-mdspr3
-mno-dspr3 — generate code for the DSP Release 3 Application Specific Extension. This option implies -mdsp and -mdspr2. This tells the assembler to accept DSP Release 3 instructions. -mno-dspr3 turns off this option 🎛️
-mmsa
-mno-msa — generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. -mno-msa turns off this option 🌈
-mxpa
-mno-xpa — generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions. -mno-xpa turns off this option 🗺️
-mmt
-mno-mt — generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns off this option 🧵
-mmcu, -mno-mcu — bestie, this one generates code for the MCU Application Specific Extension 💅 it tells the assembler to accept MCU instructions. -mno-mcu turns it back off, like closing the tab.
-mcrc, -mno-crc — generates code for the MIPS cyclic redundancy check (CRC) Application Specific Extension ✨ so the assembler will accept CRC instructions. -mno-crc switches it off.
-mginv, -mno-ginv — generates code for the Global INValidate (GINV) Application Specific Extension 🌸 assembler accepts GINV instructions, -mno-ginv says sike, no.
-mloongson-mmi, -mno-loongson-mmi — generates code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension 🎀 assembler accepts MMI instructions, -mno-loongson-mmi turns it off.
-mloongson-cam, -mno-loongson-cam — generates code for the Loongson Content Address Memory (CAM) instructions 🦋 assembler accepts Loongson CAM instructions, and -mno-loongson-cam turns that off.
-mloongson-ext, -mno-loongson-ext — generates code for the Loongson EXTensions (EXT) instructions ⭐ assembler accepts Loongson EXT instructions, -mno-loongson-ext disables it.
-mloongson-ext2, -mno-loongson-ext2 — generates code for the Loongson EXTensions R2 (EXT2) instructions 🌈 heads up, this option implies -mloongson-ext. It tells the assembler to accept Loongson EXT2 instructions, and -mno-loongson-ext2 turns this option off.
-minsn32, -mno-insn32 — only use 32-bit instruction encodings when generating code for the microMIPS processor 👑 this option inhibits the use of any 16-bit instructions. It's equivalent to putting .set insn32 at the start of the assembly file. -mno-insn32 turns this option off, and it's equivalent to putting .set noinsn32 at the start of the assembly file. By default -mno-insn32 is selected, allowing all instructions to be used. so you get the whole menu, not just the appetizer.
--construct-floats, --no-construct-floats — the --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register 💅 by default --construct-floats is selected, allowing construction of these floating point constants.
--relax-branch, --no-relax-branch — --relax-branch enables the relaxation of out-of-range branches ✨ by default --no-relax-branch is selected, causing any out-of-range branches to produce an error. no chill, just errors.
-mignore-branch-isa, -mno-ignore-branch-isa — ignore branch checks for invalid transitions between ISA modes 🌸 the semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. Therefore GAS has checks implemented that verify in branch assembly that the two ISA modes match. -mignore-branch-isa disables these checks. By default -mno-ignore-branch-isa is selected, causing any invalid branch requiring a transition between ISA modes to produce an error 💀
-mnan=encoding — pick between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format 🦋 the latter is the default, no cap.
--emulation=name — okay this one's a little historical bestie 📜 it was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. It is retained for backwards compatibility.

The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferred options instead.

-nocpp — as literally ignores this option 🙈 it is accepted for compatibility with the native tools.
--trap, --no-trap, --break, --no-break — these control how to deal with multiplication overflow and division by zero 😭 --trap or --no-break (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher); --break or --no-trap (also synonyms, and the default) take a break exception.
-n — when this option is used, as will issue a warning every time it generates a nop instruction from a macro. it's giving very attentive.

🌈 The following options are available when `as` is configured for a LoongArch processor 🌈

-fpic, -fPIC — generate position-independent code ✨
-fno-pic — don't generate position-independent code (default) 💅

🦋 The following options are available when `as` is configured for a Meta processor 🦋

-mcpu=metac11 — generate code for Meta 1.1.
-mcpu=metac12 — generate code for Meta 1.2.
-mcpu=metac21 — generate code for Meta 2.1.
-mfpu=metac21 — allow code to use FPU hardware of Meta 2.1 🔥

See the info pages for documentation of the MMIX-specific options. 🫶 (yes, that's really all it says here, go read the info pages bestie)

🎀 The following options are available when `as` is configured for a NDS32 processor 🎀

-O1 — optimize for performance 🔥
-Os — optimize for space 🌸
-EL — produce little endian data output.
-EB — produce little endian data output. (yes bestie, the page literally says little endian for -EB too 🙈 that's exactly what it says, we don't make the rules)
-mpic — generate PIC.
-mno-fp-as-gp-relax — suppress fp-as-gp relaxation for this file.
-mb2bb-relax — back-to-back branch optimization ✨
-mno-all-relax — suppress all relaxation for this file.
-march=<arch name> — assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.
-mbaseline=<baseline> — assemble for baseline <baseline> which could be v2, v3, v3m.
-mfpu-freg=FREG — specify a FPU configuration 💅 and the vibes are:

0      8 SP /  4 DP registers
1     16 SP /  8 DP registers
2     32 SP / 16 DP registers
3     32 SP / 32 DP registers

-mabi=abi — specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
-m[no-]mac — enable/disable Multiply instructions support.
-m[no-]div — enable/disable Divide instructions support.
-m[no-]16bit-ext — enable/disable 16-bit extension.
-m[no-]dx-regs — enable/disable d0/d1 registers.
-m[no-]perf-ext — enable/disable Performance extension.
-m[no-]perf2-ext — enable/disable Performance extension 2.
-m[no-]string-ext — enable/disable String extension.
-m[no-]reduced-regs — enable/disable Reduced Register configuration (GPR16) option.
-m[no-]audio-isa-ext — enable/disable AUDIO ISA extension.
-m[no-]fpu-sp-ext — enable/disable FPU SP extension.
-m[no-]fpu-dp-ext — enable/disable FPU DP extension.
-m[no-]fpu-fma — enable/disable FPU fused-multiply-add instructions.
-mall-ext — turn on all extensions and instructions support 👑 the full send.

💜 The following options are available when `as` is configured for a PowerPC processor 💜

-a32 — generate ELF32 or XCOFF32.
-a64 — generate ELF64 or XCOFF64.
-K PIC — set EF_PPC_RELOCATABLE_LIB in ELF flags.
-mpwrx | -mpwr2 — generate code for POWER/2 (RIOS2).
-mpwr — generate code for POWER (RIOS1).
-m601 — generate code for PowerPC 601.
-mppc, -mppc32, -m603, -m604 — generate code for PowerPC 603/604.
-m403, -m405 — generate code for PowerPC 403/405.
-m440 — generate code for PowerPC 440. BookE and some 405 instructions.
-m464 — generate code for PowerPC 464.
-m476 — generate code for PowerPC 476.
-m7400, -m7410, -m7450, -m7455 — generate code for PowerPC 7400/7410/7450/7455.
-m750cl, -mgekko, -mbroadway — generate code for PowerPC 750CL/Gekko/Broadway.
-m821, -m850, -m860 — generate code for PowerPC 821/850/860.
-mppc64, -m620 — generate code for PowerPC 620/625/630.
-me200z2, -me200z4 — generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.
-me300 — generate code for PowerPC e300 family.
-me500, -me500x2 — generate code for Motorola e500 core complex.
-me500mc — generate code for Freescale e500mc core complex.
-me500mc64 — generate code for Freescale e500mc64 core complex.
-me5500 — generate code for Freescale e5500 core complex.
-me6500 — generate code for Freescale e6500 core complex.
-mlsp — enable LSP instructions. (Disables SPE and SPE2.) 💀 choose your fighter
-mspe — generate code for Motorola SPE instructions. (Disables LSP.)
-mspe2 — generate code for Freescale SPE2 instructions. (Disables LSP.)
-mtitan — generate code for AppliedMicro Titan core complex.
-mppc64bridge — generate code for PowerPC 64, including bridge insns.
-mbooke — generate code for 32-bit BookE.
-ma2 — generate code for A2 architecture.
-maltivec — generate code for processors with AltiVec instructions.
-mvle — generate code for Freescale PowerPC VLE instructions.
-mvsx — generate code for processors with Vector-Scalar (VSX) instructions.
-mhtm — generate code for processors with Hardware Transactional Memory instructions.
-mpower4, -mpwr4 — generate code for Power4 architecture.
-mpower5, -mpwr5, -mpwr5x — generate code for Power5 architecture.
-mpower6, -mpwr6 — generate code for Power6 architecture.
-mpower7, -mpwr7 — generate code for Power7 architecture.
-mpower8, -mpwr8 — generate code for Power8 architecture.
-mpower9, -mpwr9 — generate code for Power9 architecture.
-mpower10, -mpwr10 — generate code for Power10 architecture.
-mpower11, -mpwr11 — generate code for Power11 architecture.
-mfuture — generate code for 'future' architecture. 👑 manifesting
-mcell, -mcell — generate code for Cell Broadband Engine architecture. (and yes, it's listed twice in the original, we are simply honoring the source 💀)
-mcom — generate code Power/PowerPC common instructions.
-many — generate code for any architecture (PWR/PWRX/PPC). the "why not both" of options ✨
-mregnames — allow symbolic names for registers.
-mno-regnames — do not allow symbolic names for registers.
-mrelocatable — support for GCC's -mrelocatable option.
-mrelocatable-lib — support for GCC's -mrelocatable-lib option.
-memb — set PPC_EMB bit in ELF flags.
-mlittle, -mlittle-endian, -le — generate code for a little endian machine.
-mbig, -mbig-endian, -be — generate code for a big endian machine. that's the whole vibe, no notes 💜
-nops=count — if an alignment directive inserts more than count nops, a branch gets dropped at the beginning to skip execution of all those nops. like a lil shortcut past the boring part 🏃‍♀️

💖 when `as` is configured for a RISC-V processor 💖

-fpic, -fPIC — generate position-independent code ✨
-fno-pic — don't generate position-independent code. this is the default, no cap.
-march=ISA|Profiles|Profiles_ISA — picks the base isa, exactly as specified by ISA or Profiles or Profies_ISA. for example -march=rv32ima -march=RVI20U64 -march=RVI20U64_d. if this option and the architecture attributes aren't set, the assembler checks the default configure setting --with-arch=ISA 👀
-misa-spec=ISAspec — selects the default isa spec version. if the version of ISA isn't set by -march, then the assembler helps set the version according to the default chosen spec. if this option isn't set, then the assembler checks the default configure setting --with-isa-spec=ISAspec.
-mpriv-spec=PRIVspec — selects the privileged spec version. we can decide whether the CSR is valid or not according to the chosen spec. if this option and the privilege attributes aren't set, then the assembler checks the default configure setting --with-priv-spec=PRIVspec.
-mabi=ABI — selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or "e" to indicate the soft-float calling convention ("e" indicates a soft-float RVE ABI). choose your fighter 🥊
-mrelax — take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. this one is the default 🌟
-mno-relax — don't do linker relaxations. periodt.
-march-attr — generate the default contents for the riscv elf attribute section if the .attribute directives are not set. this section is used to record the information that a linker or runtime loader needs to check compatibility. that information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification 📝
-mno-arch-attr — don't generate the default riscv elf attribute section if the .attribute directives are not set.
-mcsr-check — enable the CSR checking for the ISA-dependent CRS and the read-only CSR. the ISA-dependent CSR are only valid when the specific ISA is set. the read-only CSR can not be written by the CSR instructions. so don't even try it 🚫
-mno-csr-check — don't do CSR checking.
-mlittle-endian — generate code for a little endian machine.
-mbig-endian — generate code for a big endian machine.

see the info pages for documentation of the RX-specific options. iykyk 📖

🧚 s390 processor family 🧚

-m31, -m64 — select the word size, either 31/32 bits or 64 bits.
-mesa, -mzarch — select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch). iconic naming honestly.
-march=processor — specify which s390 processor variant is the target: g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or z17 (or arch15). that's a whole roster fr fr 💀
-mregnames, -mno-regnames — allow or disallow symbolic names for registers.
-mwarn-areg-zero — warn whenever the operand for a base or index register has been specified but evaluates to zero. ⚠️
-mwarn-regtype-mismatch=strict, -mwarn-regtype-mismatch=relaxed, -mwarn-regtype-mismatch=no, -mno-warn-regtype-mismatch — controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type. the default (which can be restored by using the relaxed argument) is to perform relaxed register name type checks, which allow floating point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating point register (FPR) operands. this is acceptable as the FPR are embedded into the lower half of the VR. using the strict argument, strict register name type checks are performed. the no argument, which is equivalent to -mno-warn-regtype-mismatch, disables any register name type checks. bestie said pick a lane 🫶

🍓 TMS320C6000 processor 🍓

-march=arch — enable (only) instructions from architecture arch. by default, all instructions are permitted.

the following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x".

-mdsbt, -mno-dsbt — the -mdsbt option causes the assembler to generate the "Tag_ABI_DSBT" attribute with a value of 1, indicating that the code is using DSBT addressing. the -mno-dsbt option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. the linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. so like, don't mix them 🙈
-mpid=no, -mpid=near, -mpid=far — the -mpid= option causes the assembler to generate the "Tag_ABI_PID" attribute with a value indicating the form of data addressing used by the code. -mpid=no, the default, indicates position-dependent data addressing, -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing, and -mpid=far indicates position-independent addressing with GOT accesses using far DP addressing. the linker will emit a warning if objects built with different settings of this option are linked together. ⚠️
-mpic, -mno-pic — the -mpic option causes the assembler to generate the "Tag_ABI_PIC" attribute with a value of 1, indicating that the code is using position-independent code addressing. the "-mno-pic" option, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. the linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together.
-mbig-endian, -mlittle-endian — generate code for the specified endianness. the default is little-endian 🦋

🌈 TILE-Gx processor 🌈

-m32 | -m64 — select the word size, either 32 bits or 64 bits.
-EB | -EL — select the endianness, either big-endian (-EB) or little-endian (-EL). the whole alphabet energy 💅

⭐ Visium processor ⭐

-mtune=arch — this option specifies the target architecture. if an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. 🛑

the following names are recognized: "mcm24" "mcm" "gr5" "gr6"

🎀 Xtensa processor 🎀

--text-section-literals | --no-text-section-literals — control the treatment of literal pools. the default is --no-text-section-literals, which places literals in separate sections in the output file. this allows the literal pool to be placed in a data RAM/ROM. with --text-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. this may be necessary for large assembly files, where the literals would otherwise be out of range of the "L32R" instructions in the text section. literals are grouped into pools following .literal_position directives or preceding "ENTRY" instructions. these options only affect literals referenced via PC-relative "L32R" instructions; literals for absolute mode "L32R" instructions are handled separately. so specific, we love a detail-oriented king 👑
--auto-litpools | --no-auto-litpools — control the treatment of literal pools. the default is --no-auto-litpools, which in the absence of --text-section-literals places literals in separate sections in the output file. this allows the literal pool to be placed in a data RAM/ROM. with --auto-litpools, the literals are interspersed in the text section in order to keep them as close as possible to their references, explicit .literal_position directives are not required. this may be necessary for very large functions, where single literal pool at the beginning of the function may not be reachable by "L32R" instructions at the end. these options only affect literals referenced via PC-relative "L32R" instructions; literals for absolute mode "L32R" instructions are handled separately. when used together with --text-section-literals, --auto-litpools takes precedence. it's giving main character energy ✨
--absolute-literals | --no-absolute-literals — indicate to the assembler whether "L32R" instructions use absolute or PC-relative addressing. if the processor includes the absolute addressing option, the default is to use absolute "L32R" relocations. otherwise, only the PC-relative "L32R" relocations can be used.
--target-align | --no-target-align — enable or disable automatic alignment to reduce branch penalties at some expense in code size. this optimization is enabled by default. note that the assembler will always align instructions like "LOOP" that have fixed alignment requirements. so some things just always snap into place 💅
--longcalls | --no-longcalls — enable or disable transformation of call instructions to allow calls across a greater range of addresses. this option should be used when call targets can potentially be out of range. it may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. the default is --no-longcalls.
--transform | --no-transform — enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. the default is --transform; --no-transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source. using --no-transform causes out of range instruction operands to be errors. 🚨
--rename-section oldname=newname — rename the oldname section to newname. this option can be used multiple times to rename multiple sections. glow-up for your sections fr fr 🦋
--trampolines, --no-trampolines — turns the rewriting of jump instructions on or off, so your jumps can reach waaaay further addresses 🦋. You want this when the jump targets might legitimately be out of range. If you don't have any of those far-flung jumps, this option changes literally nothing — same code size, same performance, no cap. The default is --trampolines.
--abi-windowed, --abi-call0 — picks which ABI tag gets written into the .xtensa.info section. That tag is basically a lil name badge telling everyone what ABI the assembly code speaks 💅. If you try to link object files with inconsistent ABI tags, the linker will clock it and issue a warning. Fun fact: the default ABI isn't picked by you, it's chosen by the Xtensa core configuration. Not your call, bestie.

The next batch of options is what you get when as is configured for a Z80 processor. 🌈

🎀 Z80 DEPENDENT FEATURES 🎀

✨ Command-line Options ✨

-march=CPU[-EXT...][+EXT...] — sets the target processor, periodt. If you try to assemble an instruction that won't actually execute on that processor, the assembler hits you with an error message 🙈. Here are the processor names it recognizes: "z80", "z180", "ez80", "gbz80", "z80n", "r800".

And it's not just the base instruction set, okay? You can also tell the assembler to accept certain extension mnemonics. Like, -march=z180+sli+infc extends z180 with SLI instructions and IN F,(C) 💫. These are the extensions currently supported:

"full" — all known instructions
"adl" — ADL CPU mode by default, eZ80 only
"sli" — the instruction known as SLI, SLL or SL1
"xyhl" — instructions with halves of index registers: IXL, IXH, IYL, IYH
"xdcb" — instructions like RotOp (II+d),R and BitOp n,(II+d),R
"infc" — the instruction IN F,(C) or IN (C)
"outc0" — the instruction OUT (C),0

Now here's the plot twist 🫶: instead of extending a basic instruction set, an extension mnemonic that starts with - revokes that functionality. So -march=z80-full+xyhl first strips away all the default extensions, then adds support for the index register halves only. Iconic behaviour, honestly.

If you don't specify this option at all, then -march=z80+xyhl+infc is just assumed. Defaults, slay.

-local-prefix=prefix — marks every label with the specified prefix as local. But (and this is important!) such a label can still be explicitly marked global in the code, no drama. Also this option does **not change the default local label prefix .L, it just adds a new one on top. Two prefixes, bestie, we're rich 💖.
-colonless — accepts colonless labels. Every symbol at the beginning of a line gets treated as a label. Yes, really, all of them 👀.
-sdcc — accepts assembler code produced by SDCC. That's it, that's the whole vibe.
*-fp-s=FORMAT* — the format for single precision floating point numbers. Default: ieee754 (32 bit) 🌸.
*-fp-d=FORMAT* — the format for double precision floating point numbers. Default: ieee754 (64 bit) 🌸.

💜 SEE ALSO 💜

gcc(1), ld(1), and the Info entries for binutils and ld. Go read them, they're giving lore 🦋.

👑 COPYRIGHT 👑

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".

And that's the whole page, bestie!! 🌟 This one is binutils-2.45.50, dated 2025-12-09, and it's AS(1) — go forth and assemble something gorgeous. Mwah 💅💖

📦 where this page comes from

ubuntu resolute: binutils-xtensa-lx106 2.45.50.20251209-1ubuntu1+6build1
ubuntu stonking: binutils-xtensa-lx106 2.45.50.20251209-1ubuntu1+6build1
💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash on 2026-10-13: a language model's rewrite of the original, under its terms