AS(1)
💅 AS(1) — the portable GNU assembler 💅
GNU Development Tools ✨
okay bestie, this is the manual page for as, aka the portable GNU assembler. she's iconic, she's lowkey everywhere, and she has a lot of target options. let's get into it. 🫶
🎀 NAME 🎀
as — the portable GNU assembler. that's the whole name, no cap. 💖
✨ SYNOPSIS ✨
the synopsis is literally this:
as [-a[cdghilns][=file]]
[--alternate]
[--compress-debug-sections] [--nocompress-debug-sections]
[-D]
[--dump-config]
[--debug-prefix-map old=new]
[--defsym sym=val]
[--elf-stt-common=[no|yes]]
[--emulation=name]
[-f]
[-g] [--gstabs] [--gstabs+]
[--gdwarf-<N>] [--gdwarf-sections]
[--gdwarf-cie-version=VERSION]
[--generate-missing-build-notes=[no|yes]]
[--gsframe]
[--hash-size=N]
[--help] [--target-help]
[--info] [--no-info]
[-I dir]
[-J]
[-K]
[--keep-locals]
[-L]
[--listing-lhs-width=NUM]
[--listing-lhs-width2=NUM]
[--listing-rhs-width=NUM]
[--listing-cont-lines=NUM]
[--multibyte-handling=[allow|warn|warn-sym-only]]
[--no-pad-sections]
[-o objfile] [-R]
[--scfi=experimental]
[--sectname-subst]
[--size-check=[error|warning]]
[--statistics]
[-v] [-version] [--version]
[-W] [--no-warn] [--warn] [--fatal-warnings]
[-w] [-x]
[-Z] [@FILE]
[target-options]
[--|files ...]🎯 TARGET 🎯
target options go absolutely hard. here is every single one, organized by architecture. do not skip a flag, periodt. 💅
Target AArch64 options:
-EB/-EL-mabi=ABI
Target Alpha options:
-mcpu-mdebug/-no-mdebug-replace/-noreplace-relax-g-Gsize-F-32addr
Target ARC options:
-mcpu=cpu-mA6/-mARC600/-mARC601/-mA7/-mARC700/-mEM/-mHS-mcode-density-mrelax-EB/-EL
Target ARM options:
-mcpu=processor[+extension...]-march=architecture[+extension...]-mfpu=floating-point-format-mfloat-abi=abi-meabi=ver-mthumb-EB/-EL-mapcs-32/-mapcs-26/-mapcs-float/-mapcs-reentrant-mthumb-interwork-k
Target Blackfin options:
-mcpu=processor[-sirevision]-mfdpic-mno-fdpic-mnopic
Target BPF options:
-EL-EB
Target CRIS options:
--underscore/--no-underscore--pic-N--emulation=criself/--emulation=crisaout--march=v0_v10/--march=v10/--march=v32/--march=common_v10_v32
Target C-SKY options:
-march=arch-mcpu=cpu-EL-mlittle-endian-EB-mbig-endian-fpic-pic-mljump-mno-ljump-force2bsr-mforce2bsr-no-force2bsr-mno-force2bsr-jsri2bsr-mjsri2bsr-no-jsri2bsr-mno-jsri2bsr-mnolrw-mno-lrw-melrw-mno-elrw-mlaf-mliterals-after-func-mno-laf-mno-literals-after-func-mlabr-mliterals-after-br-mno-labr-mnoliterals-after-br-mistack-mno-istack-mhard-float-mmp-mcp-mcache-msecurity-mtrust-mdsp-medsp-mvdsp
Target D10V options:
-O
Target D30V options:
-O/-n/-N
Target EPIPHANY options:
-mepiphany/-mepiphany16
Target H8/300 options:
-h-tick-hex
Target i386 options:
--32/--x32/--64-n-march=CPU[+EXTENSION...]-mtune=CPU
Target IA-64 options:
-mconstant-gp/-mauto-pic-milp32/-milp64/-mlp64/-mp64-mle/mbeyes bestie,mbehas no dash in the original, we keep it exactly 💀-mtune=itanium1/-mtune=itanium2-munwind-check=warning/-munwind-check=error-mhint.b=ok/-mhint.b=warning/-mhint.b=error-x/-xexplicit-xauto-xdebug
Target IP2K options:
-mip2022/-mip2022ext
Target M32C options:
-m32c/-m16c-relax-h-tick-hex
Target M32R options:
--m32rx/--[no-]warn-explicit-parallel-conflicts/--W[n]p
Target M680X0 options:
-l-m68000/-m68010/-m68020/...
Target M68HC11 options:
-m68hc11/-m68hc12/-m68hcs12/-mm9s12x/-mm9s12xg-mshort/-mlong-mshort-double/-mlong-double--force-long-branches--short-branches--strict-direct-mode--print-insn-syntax--print-opcodes--generate-example
Target MCORE options:
-jsri2bsr-sifilter-relax-mcpu=[210|340]
Target Meta options:
-mcpu=cpu-mfpu=cpu-mdsp=cpu
Target MICROBLAZE options:
-mlittle-endian-mbig-endian
Target MIPS options:
-nocpp-EL-EB-O[optimization level]-g[debug level]-G num-KPIC-call_shared-non_shared-xgot-mvxworks-pic-mabi=ABI-32-n32-64-mfp32-mgp32-mfp64-mgp64-mfpxx-modd-spreg-mno-odd-spreg-march=CPU-mtune=CPU-mips1-mips2-mips3-mips4-mips5-mips32-mips32r2-mips32r3-mips32r5-mips32r6-mips64-mips64r2-mips64r3-mips64r5-mips64r6-construct-floats-no-construct-floats-mignore-branch-isa-mno-ignore-branch-isa-mnan=encoding-trap-no-break-break-no-trap-mips16-no-mips16-mmips16e2-mno-mips16e2-mmicromips-mno-micromips-msmartmips-mno-smartmips-mips3d-no-mips3d-mdmx-no-mdmx-mdsp-mno-dsp-mdspr2-mno-dspr2-mdspr3-mno-dspr3-mmsa-mno-msa-mxpa-mno-xpa-mmt-mno-mt-mmcu-mno-mcu-mcrc-mno-crc-mginv-mno-ginv-mloongson-mmi-mno-loongson-mmi-mloongson-cam-mno-loongson-cam-mloongson-ext-mno-loongson-ext-mloongson-ext2-mno-loongson-ext2-minsn32-mno-insn32-mfix7000-mno-fix7000-mfix-rm7000-mno-fix-rm7000-mfix-vr4120-mno-fix-vr4120-mfix-vr4130-mno-fix-vr4130-mfix-r5900-mno-fix-r5900-mdebug-no-mdebug-mpdr-mno-pdr
Target MMIX options:
--fixed-special-register-names--globalize-symbols--gnu-syntax--relax--no-predefined-symbols--no-expand--no-merge-gregs-x--linker-allocated-gregs
Target NDS32 options:
-EL-EB-O-Os-mcpu=cpu-misa=isa-mabi=abi-mall-ext-m[no-]16-bit-m[no-]perf-ext-m[no-]perf2-ext-m[no-]string-ext-m[no-]dsp-ext-m[no-]mac-m[no-]div-m[no-]audio-isa-ext-m[no-]fpu-sp-ext-m[no-]fpu-dp-ext-m[no-]fpu-fma-mfpu-freg=FREG-mreduced-regs-mfull-regs-m[no-]dx-regs-mpic-mno-relax-mb2bb
Target PDP11 options:
-mpic/-mno-pic-mall-mno-extensions-mextension/-mno-extension-mcpu-mmachine
Target picoJava options:
-mb/-me
Target PowerPC options:
-a32/-a64-mpwrx/-mpwr2/-mpwr/-m601/-mppc/-mppc32/-m603/-m604/-m403/-m405/-m440/-m464/-m476/-m7400/-m7410/-m7450/-m7455/-m750cl/-mgekko/-mbroadway/-mppc64/-m620/-me500/-e500x2/-me500mc/-me500mc64/-me5500/-me6500/-mppc64bridge/-mbooke/-mpower4/-mpwr4/-mpower5/-mpwr5/-mpwr5x/-mpower6/-mpwr6/-mpower7/-mpwr7/-mpower8/-mpwr8/-mpower9/-mpwr9-ma2/-mcell/-mspe/-mspe2/-mtitan/-me300/-mcom-many-maltivec/-mvsx/-mhtm/-mvle-mregnames/-mno-regnames-mrelocatable/-mrelocatable-lib/-K PIC-memb-mlittle/-mlittle-endian/-le/-mbig/-mbig-endian/-be-msolaris/-mno-solaris-nops=count
Target PRU options:
-link-relax-mnolink-relax-mno-warn-regname-label
Target RISC-V options:
-fpic/-fPIC/-fno-pic-march=ISA-mabi=ABI-mlittle-endian/-mbig-endian
Target RL78 options:
-mg10-m32bit-doubles/-m64bit-doubles
Target RX options:
-mlittle-endian/-mbig-endian-m32bit-doubles/-m64bit-doubles-muse-conventional-section-names-msmall-data-limit-mpid-mrelax-mint-register=number-mgcc-abi/-mrx-abi
Target s390 options:
-m31/-m64-mesa/-mzarch-march=CPU-mregnames/-mno-regnames-mwarn-areg-zero-mwarn-regtype-mismatch=strict-mwarn-regtype-mismatch=relaxed-mwarn-regtype-mismatch=no-mno-warn-regtype-mismatch
Target SCORE options:
-EB-EL-FIXDD-NWARN-SCORE5-SCORE5U-SCORE7-SCORE3-march=score7-march=score3-USE_R1-KPIC-O0-G num-V
Target SPARC options:
-Av6/-Av7/-Av8/-Aleon/-Asparclet/-Asparclite/-Av8plus/-Av8plusa/-Av8plusb/-Av8plusc/-Av8plusd/-Av8plusv/-Av8plusm/-Av9/-Av9a/-Av9b/-Av9c/-Av9d/-Av9e/-Av9v/-Av9m/-Asparc/-Asparcvis/-Asparcvis2/-Asparcfmaf/-Asparcima/-Asparcvis3/-Asparcvisr/-Asparc5-xarch=v8plus/-xarch=v8plusa/-xarch=v8plusb/-xarch=v8plusc/-xarch=v8plusd/-xarch=v8plusv/-xarch=v8plusm/-xarch=v9/-xarch=v9a/-xarch=v9b/-xarch=v9c/-xarch=v9d/-xarch=v9e/-xarch=v9v/-xarch=v9m/-xarch=sparc/-xarch=sparcvis/-xarch=sparcvis2/-xarch=sparcfmaf/-xarch=sparcima/-xarch=sparcvis3/-xarch=sparcvisr/-xarch=sparc5/-bump-32/-64--enforce-aligned-data--dcti-couples-detect
Target TIC54X options:
-mcpu=54[123589]/-mcpu=54[56]lp-mfar-mode/-mf-merrors-to-file <filename>/-me <filename>
Target TIC6X options:
-march=arch-mbig-endian/-mlittle-endian-mdsbt/-mno-dsbt-mpid=no/-mpid=near/-mpid=far-mpic/-mno-pic
Target TILE-Gx options:
-m32/-m64-EB-EL
Target Visium options:
-mtune=arch
Target Xtensa options:
--[no-]text-section-literals--[no-]auto-litpools--[no-]absolute-literals--[no-]target-align--[no-]longcalls--[no-]transform--rename-section oldname=newname--[no-]trampolines--abi-windowed/--abi-call0
Target Z80 options:
-march=CPU[-EXT][+EXT]-local-prefix=PREFIX-colonless-sdcc-fp-s=FORMAT-fp-d=FORMAT
💅 DESCRIPTION 💅
okay so bestie, plot twist: GNU as isn't just one assembler, it's literally a whole family of them 👑. If you've used the GNU assembler on one architecture, switching to another one should feel like... pretty much the same vibe? Each version has a ton in common with the others: object file formats, most assembler directives (aka pseudo-ops, iykyk), and assembler syntax. It's giving ✨consistency✨.
as is mainly meant to assemble the output of the GNU C compiler gcc, so that the linker ld can do its thing. That said, they really tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions? Documented explicitly, no cap. This does not mean as always uses the same syntax as another assembler for the same architecture — like, we literally know of several incompatible versions of 680x0 assembly language syntax. Messy 💀.
Every single time you run as, it assembles exactly one source program. That source program is made up of one or more files. (And yes, standard input counts as a file too 🫶.)
You hand as a command line with zero or more input file names. The input files get read from left to right. Any command-line argument (in any position) that doesn't have some special meaning? It's taken as an input file name. Periodt.
If you give as no file names at all, it tries to read one input file from as's standard input, which is normally your terminal 🌸. You might have to type ctl-D to tell as there's no more program to assemble.
Use -- if you need to explicitly name the standard input file in your command line.
If the source is empty, as produces a small, empty object file. iconic behaviour honestly.
as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly 😭.
If you're invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and from the -Wa) by commas. For example:
gcc -c -g -O -Wa,-alh,-L file.cThis passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table).
Usually you do not need to use this -Wa mechanism, since lots of compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.) slay 🎀
✨ OPTIONS ✨
@file— Read command-line options from file. The options read get inserted in place of the original@fileoption. If file doesn't exist, or can't be read, then the option gets treated literally and is not removed 🙈.- Options inside file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional
@fileoptions; any such options will be processed recursively. it's giving inception 🌀
- Options inside file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional
-a[cdghilmns]— Turn on listings, in any of a variety of ways:-acomit false conditionals-adomit debugging directives-aginclude general information, likeasversion and options passed-ahinclude high-level source-alinclude assembly-aliinclude assembly with ginsn-aminclude macro expansions-anomit forms processing-asinclude symbols=fileset the name of the listing file
You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls 👑
--alternate— Begin in alternate macro mode.--compress-debug-sections— Compress DWARF debug sections using zlib withSHF_COMPRESSEDfrom the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities 🫠. Note: if compression would make a given section larger, then it is not compressed.--compress-debug-sections=none,--compress-debug-sections=zlib,--compress-debug-sections=zlib-gnu,--compress-debug-sections=zlib-gabi,--compress-debug-sections=zstd— These options control how DWARF debug sections are compressed.--compress-debug-sections=noneis equivalent to--nocompress-debug-sections.--compress-debug-sections=zliband--compress-debug-sections=zlib-gabiare equivalent to--compress-debug-sections.--compress-debug-sections=zlib-gnucompresses DWARF debug sections using the obsoleted zlib-gnu format 💀. The debug sections are renamed to begin with.zdebug.--compress-debug-sections=zstdcompresses DWARF debug sections using zstd. Note: if compression would actually make a section larger, then it is neither compressed nor renamed.
--nocompress-debug-sections— Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.-D— Enable debugging in target specific backends, if supported. Otherwise ignored. Even if ignored, this option is accepted for script compatibility with calls to other assemblers 🤝.--debug-prefix-map old=new— When assembling files in directory old, record debugging information describing them as in new instead.--defsym sym=value— Define the symbol sym to value before assembling the input file. value must be an integer constant. As in C, a leading0xindicates a hexadecimal value, and a leading0indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a.setpseudo-op.--dump-config— Displays how the assembler is configured and then exits.--elf-stt-common=no,--elf-stt-common=yes— These options control whether the ELF assembler should generate common symbols with theSTT_COMMONtype. The default can be controlled by a configure option--enable-elf-stt-common.--emulation=name— If the assembler is configured to support multiple different target configurations, then this option can be used to select the desired form.-f— "fast" — skip whitespace and comment preprocessing (assume source is compiler output). speed demon energy 🏎️-g,--gen-debug— Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a.debug_infoand.debug_linesection is only emitted when the assembly file doesn't generate one itself.--gstabs— Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.--gstabs+— Generate stabs debugging information for each assembler line, with GNU extensions that probably onlygdbcan handle, and that could make other debuggers crash or refuse to read your program 😭. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time.--gdwarf-2— Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note: this option is only supported by some targets, not all of them 🫠.--gdwarf-3— Same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information — the choice to do so is on a per target basis.--gdwarf-4— Same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information — the choice to do so is on a per target basis.--gdwarf-5— Same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information — the choice to do so is on a per target basis.--gdwarf-sections— Instead of creating a.debug_linesection, create a series of.debug_line.foosections where foo is the name of the corresponding code section. For example a code section called.text.funcwill have its dwarf line number information placed into a section called.debug_line.text.func. If the code section is just called.textthen the debug line section will still be called just.debug_linewithout any suffix.--gdwarf-cie-version=version— Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specified the default is version1, though some targets can modify this default. Other possible values for version are3or4.--generate-missing-build-notes=yes,--generate-missing-build-notes=no— These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the--enable-generate-build-notesconfigure option.--gsframe,--gsframe— Create.sframesection from CFI directives. (yes bestie, it's listed twice in the original, and we're keeping that energy 💖)--hash-size N— Ignored. Supported for command line compatibility with other assemblers.--help— Print a summary of the command-line options and exit.--target-help— Print a summary of all target specific options and exit.--info— Don't suppress informational messages.--no-info— Suppress informational messages.-I dir— Add directory dir to the search list for.includedirectives.-J— Don't warn about signed overflow.-K— Issue warnings when difference tables altered for long displacements.-L,--keep-locals— Keep (in the symbol table) local symbols. These symbols start with system-specific local label prefixes, typically.Lfor ELF systems orLfor traditional a.out systems.--listing-lhs-width=number— sets the max width, measured in words, of the output data column in an assembler listing tonumber. 🎀--listing-lhs-width2=number— same idea as the one above, but for the continuation lines in an assembler listing. Max width, in words, set tonumber. ✨--listing-rhs-width=number— sets the max width of an input source line, as shown in a listing, tonumberbytes. 💅--listing-cont-lines=number— sets the max number of lines printed in a listing for a single line of input tonumber + 1. yes, plus one. that's not a typo, that's the spec. 😌--multibyte-handling=allow--multibyte-handling=warn--multibyte-handling=warn-sym-only--multibyte-handling=warn_sym_only
okay so this one controls how the assembler deals with multibyte characters in the input, and there are four spellings of it up there — warn_sym_only is just the underscore twin of warn-sym-only, same energy, different punctuation. 🦋
The default (which you can bring back by passing the allow argument) is to allow such characters with zero complaints. Using warn makes the assembler generate a warning message whenever any multibyte character is encountered. Using warn-sym-only only generates a warning when a symbol is defined with a name that contains multibyte characters. (References to undefined symbols will not generate a warning.) lowkey very specific of it, but ok 👑
--no-pad-sections— stops the assembler from padding the ends of output sections to the alignment of that section. The default is to pad the sections, but that can waste space, and space might be exactly what you're short on when a target has tight memory constraints. 🫶-o objfile— names the object-file output fromasasobjfile. iconic, classic, you know her. 💖-R— folds the data section into the text section. 🌀--reduce-memory-overheads— Ignored. It's only there for compatibility with tools that pass the same option to both the assembler and the linker. it's a decoy bestie, it does nothing 💀--scfi=experimental— controls whether the assembler should synthesize CFI for hand-written input. If the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning. 🚨
Note that --scfi=experimental is not intended to be used for compiler-generated code, including inline assembly. This experimental support is work in progress. Only the System V AMD64 ABI is supported.
Each input function in assembly must begin with the .type directive, and should ideally be closed off using a .size directive. When using SCFI, each .type directive prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry). This implies that with each .type directive, a previous block of instructions, if any, is finalised as a distinct FDE. so basically every .type is a chapter break, no cap 📖
--sectname-subst— honors substitution sequences in section names. 🌈--size-check=error--size-check=warning
issue an error or a warning (your pick) for an invalid ELF .size directive. 👀
--statistics— prints the maximum space (in bytes) and the total time (in seconds) used by assembly. the receipts, basically. 🧾--strip-local-absolute— removes local absolute symbols from the outgoing symbol table. 🧹-v-version
print the as version. 🎀
--version— prints theasversion and exits. (yes, this one dips out immediately, that's the whole difference) ✌️-W--no-warn
suppress warning messages. shhh. 🤫
--warn— does not suppress warning messages and does not treat them as errors. the chill option, the peacekeeper 🕊️--fatal-warnings— treats warnings as errors. uh oh. every little warning is now a whole crime 😭-w— Ignored. 💀-x— Ignored. 💀💀-Z— generates an object file even after errors. chaotic. brave. kinda iconic honestly. 🔥- *
--| *files ... — standard input, or source files to assemble. 🫶
okay bestie, that's the generic menu. now we get into the per-processor zone, and these next ones are only available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). 🦋✨
-EB— specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. 🐘-EL— specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. 🐭-mabi=abi— specifies which ABI the source code uses. The recognized arguments are:ilp32andlp64, which decide the generated object file in ELF32 and ELF64 format respectively. The default islp64. 💅-mcpu=processor[+extension...]— specifies the target processor. The assembler will issue an error message if you try to assemble an instruction which will not execute on the target processor. 🙈
The following processor names are recognized: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a510, cortex-a520, cortex-a710, cortex-a720, ares, exynos-m1, falkor, neoverse-n1, neoverse-n2, neoverse-e1, neoverse-v1, qdf24xx, saphira, thunderx, vulcan, xgene1 xgene2, cortex-r82, cortex-x1, cortex-x2, cortex-x3, and cortex-x4. that's a whole group chat of chips omg 👑
The special name all may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions.
In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.
If some implementations of a particular processor can have an extension, then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions. the chip already knows, bestie, it's got this 🫶
-march=architecture[+extension...]— specifies the target architecture. The assembler will issue an error message if you try to assemble an instruction which will not execute on the target architecture. 😬
The following architecture names are recognized: armv8-a, armv8.1-a, armv8.2-a, armv8.3-a, armv8.4-a armv8.5-a, armv8.6-a, armv8.7-a, armv8.8-a, armv8.9-a, armv8-r, armv9-a, armv9.1-a, armv9.2-a, armv9.3-a, armv9.4-a and armv9.5-a. ✨
If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assembler will default to -mcpu=all.
The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu, extensions are not always enabled by default. so like, you gotta ask nicely here 🎀
-mverbose-error— enables verbose error messages for AArch64 gas. This option is enabled by default. 🗣️-mno-verbose-error— disables verbose error messages in AArch64 gas. 🤐
and these next ones show up when as is configured for an Alpha processor. 🌸
-mcpu— specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the.archdirective.
The following processor names are recognized: 21064, 21064a, 21066, 21068, 21164, 21164a, 21164pc, 21264, 21264a, 21264b, ev4, ev5, lca45, ev5, ev56, pca56, ev6, ev67, ev68. (yep, ev5 is in there twice — that's the original, not me being clumsy 💅) The special name all may be used to allow the assembler to accept instructions valid for any Alpha processor.
In order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the electro-vlasic names (e.g. ev4) do not. ⚡
-mdebug-no-mdebug
enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. The default is to automatically enable .mdebug when the first stabs directive is seen. 🙈
-relax— forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time.
Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications.
-replace-noreplace
enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets, and -replace is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual. 📖
-g— this option is used when the compiler generates debug information. When gcc is usingmips-tfileto generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect. 🫠-Gsize— a local common symbol larger thansizeis placed in.bss, while smaller symbols are placed in.sbss. the size cutoff decides the neighborhood 🏘️-F-32addr
these options are ignored for backward compatibility. 💀
next up: the options for when as is configured for an ARC processor. 🌈
-mcpu=cpu— selects the core processor variant. 💅-EB|-EL— select either big-endian (-EB) or little-endian (-EL) output. 🐘🐭-mcode-density— enable Code Density extension instructions. smol code, big brain 🧠
and these are the ones for the ARM processor family. 👑
-mcpu=processor[+extension...]— specify which ARM processor variant is the target. 🎯-march=architecture[+extension...]— specify which ARM architecture variant is used by the target. 🏛️-mfpu=floating-point-format— select which Floating Point architecture is the target. 🦋-mfloat-abi=abi— select which floating point ABI is in use. 🫶-mthumb— enable Thumb only instruction decoding. 👍-mapcs-32|-mapcs-26|-mapcs-float|-mapcs-reentrant— select which procedure calling convention is in use. pick your fighter 💅-EB|-EL— select either big-endian (-EB) or little-endian (-EL) output. 🐘🐭-mthumb-interwork— specify that the code has been generated with interworking between Thumb and ARM code in mind. 🤝-mccs— turns on CodeComposer Studio assembly syntax compatibility mode. 🎛️-k— specify that PIC code has been generated. 🌟
The following options are available when as is configured for the Blackfin processor family. 🖤
-mcpu=processor[-sirevision]— ok so this one picks your target processor, bestie. That optionalsirevisionbit? Not used by the assembler at all — it's literally just chillin' there so GCC can pass its own-mcpu=straight down. If you try to assemble an instruction that won't actually run on your target processor, the assembler will hit you with an error message. The processor names it recognizes are:bf504,bf506,bf512,bf514,bf516,bf518,bf522,bf523,bf524,bf525,bf526,bf527,bf531,bf532,bf533,bf534,bf535(not implemented yet, sad),bf536,bf537,bf538,bf539,bf542,bf542m,bf544,bf544m,bf547,bf547m,bf548,bf548m,bf549,bf549m,bf561, andbf592.-mfdpic— assemble for the FDPIC ABI. ✨-mno-fdpic-mnopic— turns-mfdpicback off. Bye bestie 💅
The following options are available when as is configured for the Linux kernel BPF processor family.
@chapter BPF Dependent Features
🌸 BPF Options 🌸
-EB— tells the assembler to emit big-endian eBPF.-EL— tells the assembler to emit little-endian eBPF.-mdialect=dialect— picks which assembly language dialect to recognize while assembling. The assembler supportsnormalandpseudoc.-misa-spec=spec— sets which version of the BPF instruction set to use while assembling. The supported BPF ISA versions arev1,v2,v3andv4.
You can also pass xbpf as the value to recognize extra instructions that GCC uses for testing purposes. But beware, bestie — that is not valid BPF. 🫣
-mno-relax— tells the assembler to not relax instructions.
Note that if no endianness option is specified on the command line, the host endianness is used. See the info pages for documentation of the CRIS-specific options.
The following options are available when as is configured for the C-SKY processor family.
-march=archname— assemble for architecture archname. The--helpoption lists the valid values for archname. 👑-mcpu=cpuname— assemble for architecture cpuname. The--helpoption lists the valid values for cpuname.-EL-mlittle-endian— generate little-endian output.-EB-mbig-endian— generate big-endian output.-fpic-pic— generate position-independent code. 🦋-mljump-mno-ljump— enable/disable transformation of the short branch instructionsjbf,jbt, andjbrintojmpi. This one is for V2 processors only. It gets ignored on CK801 and CK802 targets (they don't support thejmpiinstruction at all), and it's enabled by default for other processors.-mbranch-stub-mno-branch-stub— pass throughR_CKCORE_PCREL_IMM26BY2relocations forbsrinstructions to the linker.
This option is only available for bare-metal C-SKY V2 ELF targets, where it's enabled by default. It cannot be used in code that's going to be dynamically linked against shared libraries. 🚫
-force2bsr-mforce2bsr-no-force2bsr-mno-force2bsr— enable/disable transformation ofjbsrinstructions intobsr. This is always enabled (and-mno-force2bsris just ignored, sorry) for CK801/CK802 targets. It's also always enabled whenever-mbranch-stubis in effect.-jsri2bsr-mjsri2bsr-no-jsri2bsr-mno-jsri2bsr— enable/disable transformation ofjsriinstructions intobsr. Enabled by default. ✨-mnolrw-mno-lrw— enable/disable transformation oflrwinstructions into amovih/oripair.-melrw-mno-elrw— enable/disable extendedlrwinstructions. Enabled by default for CK800-series processors.-mlaf-mliterals-after-func-mno-laf-mno-literals-after-func— enable/disable placement of literal pools after each function.-mlabr-mliterals-after-br-mno-labr-mnoliterals-after-br— enable/disable placement of literal pools after unconditional branches. Enabled by default. 💖-mistack-mno-istack— enable/disable interrupt stack instructions. Enabled by default on CK801, CK802, and CK802 processors.
The following options explicitly enable certain optional instructions. These features are also enabled implicitly by using -mcpu= to specify a processor that supports it.
-mhard-float— enable hard float instructions.-mmp— enable multiprocessor instructions.-mcp— enable coprocessor instructions.-mcache— enable cache prefetch instruction.-msecurity— enable C-SKY security instructions.-mtrust— enable C-SKY trust instructions.-mdsp— enable DSP instructions.-medsp— enable enhanced DSP instructions.-mvdsp— enable vector DSP instructions.
The following options are available when as is configured for an Epiphany processor.
-mepiphany— specifies that both 32 and 16 bit instructions are allowed. This is the default behavior, no cap.-mepiphany16— restricts the permitted instructions to just the 16 bit set.
The following options are available when as is configured for an H8/300 processor.
@chapter H8/300 Dependent Features
🎀 Options 🎀
The Renesas H8/300 version of as has one machine-dependent option:
-h-tick-hex— supportsH'00style hex constants in addition to0x00style.-mach=name— sets the H8300 machine variant. The machine names it recognizes are:h8300h,h8300hn,h8300s,h8300sn,h8300sxandh8300sxn.
The following options are available when as is configured for an i386 processor.
--32|--x32|--64— selects the word size, either 32 bits or 64 bits.--32implies Intel i386 architecture, while--x32and--64imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.
These options are only available with the ELF object file format, and they require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure to enable 64-bit usage, and use x86-64 as target platform). 🛠️
-n— by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such asleal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.--divide— on SVR4-derived platforms, the character/is treated as a comment character, which means it can't be used in expressions. The--divideoption turns/into a normal character. It does not disable/at the beginning of a line starting a comment, and it doesn't affect using#for starting a comment. 🧚-march=CPU[+EXTENSION...]— specifies the target processor. The assembler will issue an error message if you try to assemble an instruction that won't execute on the target processor. The processor names it recognizes are:i8086,i186,i286,i386,i486,i586,i686,pentium,pentiumpro,pentiumii,pentiumiii,pentium4,prescott,nocona,core,core2,corei7,iamcu,k6,k6_2,athlon,opteron,k8,amdfam10,bdver1,bdver2,bdver3,bdver4,znver1,znver2,znver3,znver4,znver5,btver1,btver2,generic32andgeneric64.
On top of the basic instruction set, the assembler can be told to accept various extension mnemonics. For example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. The extensions currently supported are: 8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb, avx10.1, avx10.1/512, avx10.1/256, avx10.1/128, user_msr, msr_imm, apx_f, avx10.2, avx10.2/512, avx10.2/256, avx10.2/128, movrs, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8 amx_movrs, amx_avx512, amx_tile, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, snp, invlpgb, tlbsync, svme, gmism2, gmiccs, padlockrng2, padlockphe2 and padlock.
Heads up bestie — these extension mnemonics can be prefixed withnoto revoke the respective (and any dependent) functionality. And also note that the suffixes permitted on-march=avx10.<N>enforce a vector length restriction, i.e. despite these otherwise being "enabling" options, using these suffixes will disable all insns with wider vector or mask register operands. 💀
When the .arch directive is used with -march, the .arch directive will take precedent.
-mtune=CPU— specifies a processor to optimize for. When used in conjunction with the-marchoption, only instructions of the processor specified by the-marchoption will be generated.
Valid CPU values are identical to the processor list of -march=CPU. 💅
-moperand-check=none,-moperand-check=warning,-moperand-check=error— bestie these three decide whether the assembler does a lil vibe check on certain instruction operands or operand combos 🔍 Like, think instructions where you literally can't infer the operand size from the operands themselves and nobody slapped an instruction suffix on it either.-moperand-check=none= no checks at all, we're chillin.-moperand-check=warning= throws a warning when the checks fail, and that's the default ✨.-moperand-check=error= full on error when the checks fail 💀.-msse2avx— this one says hey assembler, encode SSE instructions with a VEX prefix, which means AVX needs to be available, periodt. And if those SSE instructions use extended GPRs, they get encoded with an EVEX prefix instead, which needs AVX512 or AVX10 to be available 👑-muse-unaligned-vector-move— tells the assembler to encode aligned vector moves as unaligned vector moves. That's it, that's the whole thing 🎀-msse-check=none,-msse-check=warning,-msse-check=error— these control whether the assembler checks SSE instructions.-msse-check=nonemeans it won't check SSE instructions, and that's the default 🙈.-msse-check=warningissues a warning for any SSE instruction.-msse-check=errorissues an error for any SSE instruction. pick ur fighter 💅-mavxscalar=128,-mavxscalar=256— controls how scalar AVX instructions get encoded.-mavxscalar=128encodes them with 128bit vector length, which is the default.-mavxscalar=256encodes them with 256bit vector length 🌸
WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models. fr fr do not ship this 😭
-mvexwig=0,-mvexwig=1— controls how the assembler encodes VEX.W-ignored (WIG) VEX instructions.-mvexwig=0encodes WIG VEX instructions withvex.w = 0, which is the default.-mvexwig=1encodes WIG EVEX instructions withvex.w = 1👀
WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models. same energy, still not safe bestie 💀
-mevexlig=128,-mevexlig=256,-mevexlig=512— controls how length-ignored (LIG) EVEX instructions get encoded.-mevexlig=128encodes LIG EVEX instructions with 128bit vector length, which is the default.-mevexlig=256and-mevexlig=512encode them with 256bit and 512bit vector length respectively ✨-mevexwig=0,-mevexwig=1— controls how the assembler encodes w-ignored (WIG) EVEX instructions.-mevexwig=0encodes WIG EVEX instructions withevex.w = 0, which is the default.-mevexwig=1encodes WIG EVEX instructions withevex.w = 1🦋-mmnemonic=att,-mmnemonic=intel— picks the instruction mnemonic used for matching instructions. Note that the.att_mnemonicand.intel_mnemonicdirectives will take precedent 👑-msyntax=att,-msyntax=intel— picks the instruction syntax used when processing instructions. The.att_syntaxand.intel_syntaxdirectives will take precedent 💅-mnaked-reg— says registers don't need a%prefix. The.att_syntaxand.intel_syntaxdirectives will take precedent 🎀-madd-bnd-prefix— forces the assembler to add a BND prefix to all branches, even if that prefix wasn't explicitly specified in the source code. no exceptions, we're adding it everywhere 🔥-mno-shared— on ELF targets, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The-msharedoption tells the assembler to generate code that may go into a shared library, where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions 🌈-mbig-obj— on PE/COFF targets this forces the use of the big object file format, which allows more than 32768 sections. big file energy 📦-momit-lock-prefix=no,-momit-lock-prefix=yes— controls how the assembler encodes the lock prefix. This one is intended as a workaround for processors that fail on the lock prefix. It can only be safely used with single-core, single-thread computers.-momit-lock-prefix=yesomits all lock prefixes.-momit-lock-prefix=noencodes the lock prefix as usual, which is the default 🧚-mfence-as-lock-add=no,-mfence-as-lock-add=yes— controls howlfence,mfenceandsfenceget encoded.-mfence-as-lock-add=yesencodeslfence,mfenceandsfenceaslock addl $0x0, (%rsp)in 64-bit mode andlock addl $0x0, (%esp)in 32-bit mode.-mfence-as-lock-add=noencodeslfence,mfenceandsfenceas usual, which is the default ✨-mrelax-relocations=no,-mrelax-relocations=yes— controls whether the assembler generates relax relocations:R_386_GOT32Xin 32-bit mode, orR_X86_64_GOTPCRELXandR_X86_64_REX_GOTPCRELXin 64-bit mode.-mrelax-relocations=yesgenerates relax relocations.-mrelax-relocations=nodoes not generate them. The default can be controlled by a configure option--enable-x86-relax-relocations🔧-mtls-check=no,-mtls-check=yes— controls whether the assembler checks tls relocation.-mtls-check=yeschecks tls relocation.-mtls-check=nodoes not check tls relocation. The default can be controlled by a configure option--enable-x86-tls-check💜-malign-branch-boundary=NUM— controls how the assembler aligns branches with segment prefixes or NOP.NUMmust be a power of 2. It should be 0 or no less than 16. Branches get aligned within aNUMbyte boundary.-malign-branch-boundary=0, which is the default, doesn't align branches 📐-malign-branch=TYPE[+TYPE...]— specifies the types of branches to align.TYPEis a combination of:jcc, which aligns conditional jumps;fused, which aligns fused conditional jumps;jmp, which aligns unconditional jumps;call, which aligns calls;ret, which aligns rets; andindirect, which aligns indirect jumps and calls. The default is-malign-branch=jcc+fused+jmp🌸-malign-branch-prefix-size=NUM— specifies the maximum number of prefixes on an instruction to align branches.NUMshould be between 0 and 5. The defaultNUMis 5 🎀-mbranches-within-32B-boundaries— aligns conditional jumps, fused conditional jumps and unconditional jumps within a 32 byte boundary, with up to 5 segment prefixes on an instruction. It's equivalent to-malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5. The default doesn't align branches ⭐-mlfence-after-load=no,-mlfence-after-load=yes— controls whether the assembler generateslfenceafter load instructions.-mlfence-after-load=yesgenerateslfence.-mlfence-after-load=nodoesn't generatelfence, which is the default 💫-mlfence-before-indirect-branch=none,-mlfence-before-indirect-branch=all,-mlfence-before-indirect-branch=register,-mlfence-before-indirect-branch=memory— controls whether the assembler generateslfencebefore indirect near branch instructions.-mlfence-before-indirect-branch=allgenerateslfencebefore an indirect near branch via register and issues a warning before an indirect near branch via memory. It also implicitly sets-mlfence-before-ret=shlwhen there's no explicit-mlfence-before-ret=.-mlfence-before-indirect-branch=registergenerateslfencebefore an indirect near branch via register.-mlfence-before-indirect-branch=memoryissues a warning before an indirect near branch via memory.-mlfence-before-indirect-branch=nonewon't generatelfencenor issue a warning, which is the default. Note thatlfencewon't be generated before an indirect near branch via register with-mlfence-after-load=yes, sincelfencegets generated after loading the branch target register 👑-mlfence-before-ret=none,-mlfence-before-ret=shl,-mlfence-before-ret=or,-mlfence-before-ret=yes,-mlfence-before-ret=not— controls whether the assembler generateslfencebeforeret.-mlfence-before-ret=orgenerates a generateorinstruction withlfence.-mlfence-before-ret=shl/yesgenerates ashlinstruction withlfence.-mlfence-before-ret=notgenerates anotinstruction withlfence.-mlfence-before-ret=nonewon't generatelfence, which is the default 🦋-mx86-used-note=no,-mx86-used-note=yes— controls whether the assembler generatesGNU_PROPERTY_X86_ISA_1_USEDandGNU_PROPERTY_X86_FEATURE_2_USEDGNU property notes. The default can be controlled by the--enable-x86-used-noteconfigure option 🎀-mevexrcig=rne,-mevexrcig=rd,-mevexrcig=ru,-mevexrcig=rz— controls how the assembler encodes SAE-only EVEX instructions.-mevexrcig=rneencodes the RC bits of the EVEX instruction with00, which is the default.-mevexrcig=rd,-mevexrcig=ruand-mevexrcig=rzencode SAE-only EVEX instructions with01,10and11RC bits, respectively ✨-mamd64,-mintel64— specifies that the assembler should accept only AMD64 or Intel64 ISA in 64-bit mode. The default is to accept common, Intel64 only and AMD64 ISAs 💅-O0|-O|-O1|-O2|-Os— optimize instruction encoding with smaller instruction size.-Oand-O1encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with 32-bit register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions, encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions, and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical 🔥
-O2 also stacks on everything from -O1 and, on top of that, encodes 256-bit/512-bit EVEX vector register clearing instructions using 128-bit EVEX vector register clearing instructions. In 64-bit mode, VEX encoded instructions with commutative source operands will also get their source operands swapped if that lets it use the 2-byte VEX prefix form instead of the 3-byte one. And certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST. ✨
-Os includes -O2 optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. -O0 turns off this optimization.
🌸 Ubicom IP2K series 🌸
The following options are available when as is configured for the Ubicom IP2K series.
-mip2022ext— says the extended IP2022 instructions are allowed, bestie. Go off. 💅-mip2022— restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. Back to basics, no cap.
🦋 Renesas M32C and M16C processors 🦋
The following options are available when as is configured for the Renesas M32C and M16C processors.
-m32c— assemble M32C instructions.-m16c— assemble M16C instructions (the default).-relax— enable support for link-time relaxations. chill vibes only 😌-h-tick-hex— supportH'00style hex constants in addition to0x00style.
🎀 Renesas M32R (formerly Mitsubishi M32R) series 🎀
The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series.
--m32rx— specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.--warn-explicit-parallel-conflictsor--Wp— produce warning messages when questionable parallel constructs are encountered. 👀--no-warn-explicit-parallel-conflictsor--Wnp— do not produce warning messages when questionable parallel constructs are encountered.
🔥 Motorola 68000 series 🔥
The following options are available when as is configured for the Motorola 68000 series.
-l— shorten references to undefined symbols, to one word instead of two.-m68000|-m68008|-m68010|-m68020|-m68030|-m68040|-m68060|-m68302|-m68331|-m68332|-m68333|-m68340|-mcpu32|-m5200— specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time.-m68881|-m68882|-mno-68881|-mno-68882— the target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor.-m68851|-mno-68851— the target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up.
For details about the PDP-11 machine dependent features options, see PDP-11-Options.
-mpic|-mno-pic— generate position-independent (or position-dependent) code. The default is-mpic.-mall-mall-extensions— enable all instruction set extensions. This is the default. all of them, periodt 💖-mno-extensions— disable all instruction set extensions.-mextension|-mno-extension— enable (or disable) a particular instruction set extension.-mcpu— enable the instruction set extensions supported by a particular CPU, and disable all other extensions.-mmachine— enable the instruction set extensions supported by a particular machine model, and disable all other extensions.
🧚 picoJava processor 🧚
The following options are available when as is configured for a picoJava processor.
-mb— generate "big endian" format output.-ml— generate "little endian" format output.
⭐ PRU processor ⭐
The following options are available when as is configured for a PRU processor.
-mlink-relax— assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LD would shorten the LDI32 instruction to a single LDI. In such case "as" will output DIFF relocations for diff expressions.-mno-link-relax— assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted.-mno-warn-regname-label— do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off.
💜 MIPS processor 💜
The following options are available when as is configured for a MIPS processor.
-G num— this option sets the largest size of an object that can be referenced implicitly with the"gp"register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is8.-EB— generate "big endian" format output.-EL— generate "little endian" format output.-mips1-mips2-mips3-mips4-mips5-mips32-mips32r2-mips32r3-mips32r5-mips32r6-mips64-mips64r2-mips64r3-mips64r5-mips64r6— generate code for a particular MIPS Instruction Set Architecture level.-mips1is an alias for-march=r3000,-mips2is an alias for-march=r6000,-mips3is an alias for-march=r4000and-mips4is an alias for-march=r8000.-mips5,-mips32,-mips32r2,-mips32r3,-mips32r5,-mips32r6,-mips64,-mips64r2,-mips64r3,-mips64r5, and-mips64r6correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively.-march=cpu— generate code for a particular MIPS CPU.-mtune=cpu— schedule and tune for a particular MIPS CPU.-mfix7000-mno-fix7000— cause nops to be inserted if the read of the destination register of anmfhiormfloinstruction occurs in the following two instructions.-mfix-rm7000-mno-fix-rm7000— cause nops to be inserted if admultordmultuinstruction is followed by a load instruction.-mfix-r5900-mno-fix-r5900— do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a"nop"instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. 💀 hardware said "no" fr fr-mdebug-no-mdebug— cause stabs-style debugging output to go into an ECOFF-style.mdebugsection instead of the standard ELF.stabssections.-mpdr-mno-pdr— control generation of".pdr"sections.-mgp32-mfp32— the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times.-mgp32controls the size of general-purpose registers and-mfp32controls the size of floating-point registers.-mgp64-mfp64— the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times.-mgp64controls the size of general-purpose registers and-mfp64controls the size of floating-point registers.-mfpxx— the register sizes are normally inferred from the ISA and ABI, but using this flag in combination with-mabi=32enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide.-modd-spreg-mno-odd-spreg— enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA.-mfpxximplies-mno-odd-spreg, otherwise the default is-modd-spreg.-mips16-no-mips16— generate code for the MIPS 16 processor. This is equivalent to putting".module mips16"at the start of the assembly file.-no-mips16turns off this option.-mmips16e2-mno-mips16e2— enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting".module mips16e2"at the start of the assembly file.-mno-mips16e2turns off this option.-mmicromips-mno-micromips— generate code for the microMIPS processor. This is equivalent to putting".module micromips"at the start of the assembly file.-mno-micromipsturns off this option. This is equivalent to putting".module nomicromips"at the start of the assembly file.-msmartmips-mno-smartmips— enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting".module smartmips"at the start of the assembly file.-mno-smartmipsturns off this option.-mips3d-no-mips3d— generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions.-no-mips3dturns off this option.-mdmx-no-mdmx— generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions.-no-mdmxturns off this option.-mdsp-mno-dsp— generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions.-mno-dspturns off this option.-mdspr2-mno-dspr2— generate code for the DSP Release 2 Application Specific Extension. This option implies-mdsp. This tells the assembler to accept DSP Release 2 instructions.-mno-dspr2turns off this option.-mdspr3-mno-dspr3— generate code for the DSP Release 3 Application Specific Extension. This option implies-mdspand-mdspr2. This tells the assembler to accept DSP Release 3 instructions.-mno-dspr3turns off this option.-mmsa-mno-msa— generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions.-mno-msaturns off this option.-mxpa-mno-xpa— generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions.-mno-xpaturns off this option.-mmt-mno-mt— generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions.-mno-mtturns off this option.
okay bestie we're still deep in the MIPS section and there's more coming, don't you dare scroll away 💜
-mmcu,-mno-mcu— bestie, this one makes code for the MCU Application Specific Extension. It tells the assembler "yes, accept MCU instructions please 💖". And-mno-mcu? turns that whole thing off.-mcrc,-mno-crc— generates code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. It tells the assembler to accept CRC instructions.-mno-crcswitches it off again, slay.-mginv,-mno-ginv— code for the Global INValidate (GINV) Application Specific Extension. Tells the assembler to accept GINV instructions.-mno-ginvturns this option off.-mloongson-mmi,-mno-loongson-mmi— code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. Tells the assembler to accept MMI instructions.-mno-loongson-mmiturns off this option.-mloongson-cam,-mno-loongson-cam— code for the Loongson Content Address Memory (CAM) instructions. Tells the assembler to accept Loongson CAM instructions.-mno-loongson-camturns off this option.-mloongson-ext,-mno-loongson-ext— code for the Loongson EXTensions (EXT) instructions. Tells the assembler to accept Loongson EXT instructions.-mno-loongson-extturns off this option.-mloongson-ext2,-mno-loongson-ext2— code for the Loongson EXTensions R2 (EXT2) instructions. Heads up: this option implies-mloongson-ext✨. It tells the assembler to accept Loongson EXT2 instructions.-mno-loongson-ext2turns off this option.-minsn32,-mno-insn32— only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions, no cap. It's equivalent to putting.set insn32at the start of the assembly file.-mno-insn32turns off this option, and it's equivalent to putting.set noinsn32at the start of the assembly file. By default-mno-insn32is selected, so all instructions are allowed 💅.--construct-floats,--no-construct-floats—--no-construct-floatsdisables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default--construct-floatsis selected, which allows construction of these floating point constants 🫶.--relax-branch,--no-relax-branch—--relax-branchenables the relaxation of out-of-range branches. By default--no-relax-branchis selected, which means any out-of-range branches just produce an error. periodt.-mignore-branch-isa,-mno-ignore-branch-isa— ignore branch checks for invalid transitions between ISA modes. The semantics of branches doesn't provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. That's why GAS has checks implemented that verify, in branch assembly, that the two ISA modes match.-mignore-branch-isadisables these checks. By default-mno-ignore-branch-isais selected, so any invalid branch requiring a transition between ISA modes produces an error 😭.-mnan=encoding— pick between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format. The legacy one is the default.--emulation=name— this option was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so ngl, the option now serves little purpose. It's retained for backwards compatibility only 🙈.
The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferred options instead 💖.
-nocpp—asignores this option. It's just accepted for compatibility with the native tools, it's giving legacy support.--trap,--no-trap,--break,--no-break— control how to deal with multiplication overflow and division by zero.--trapor--no-break(they're synonyms) take a trap exception, and those only work for Instruction Set Architecture level 2 and higher.--breakor--no-trap(also synonyms, and this is the default) take a break exception.-n— when this option is used,aswill issue a warning every time it generates anopinstruction from a macro. Very "not me, not the nop" energy 💀.
The following options are available when as is configured for a LoongArch processor.
-fpic,-fPIC— generate position-independent code ✨-fno-pic— don't generate position-independent code (default)
The following options are available when as is configured for a Meta processor.
-mcpu=metac11— generate code for Meta 1.1.-mcpu=metac12— generate code for Meta 1.2.-mcpu=metac21— generate code for Meta 2.1.-mfpu=metac21— allow code to use FPU hardware of Meta 2.1.
See the info pages for documentation of the MMIX-specific options. (iykyk, bestie 📖)
The following options are available when as is configured for a NDS32 processor.
-O1— optimize for performance.-Os— optimize for space.-EL— produce little endian data output.-EB— produce little endian data output.
Okay so yes, both-ELand-EBsay "little endian data output" in the original. Not me editing that, we keep it exactly as written 💅
-mpic— generate PIC.-mno-fp-as-gp-relax— suppress fp-as-gp relaxation for this file.-mb2bb-relax— back-to-back branch optimization.-mno-all-relax— suppress all relaxation for this file.-march=<arch name>— assemble for architecture<arch name>which could bev3,v3j,v3m,v3f,v3s,v2,v2j,v2f,v2s.-mbaseline=<baseline>— assemble for baseline<baseline>which could bev2,v3,v3m.-mfpu-freg=FREG— specify a FPU configuration.
0 8 SP / 4 DP registers
1 16 SP / 8 DP registers
2 32 SP / 16 DP registers
3 32 SP / 32 DP registers-mabi=abi— specify a abi version<abi>could bev1,v2,v2fp,v2fpp.-m[no-]mac— enable/disable Multiply instructions support.-m[no-]div— enable/disable Divide instructions support.-m[no-]16bit-ext— enable/disable 16-bit extension-m[no-]dx-regs— enable/disable d0/d1 registers-m[no-]perf-ext— enable/disable Performance extension-m[no-]perf2-ext— enable/disable Performance extension 2-m[no-]string-ext— enable/disable String extension-m[no-]reduced-regs— enable/disable Reduced Register configuration (GPR16) option-m[no-]audio-isa-ext— enable/disable AUDIO ISA extension-m[no-]fpu-sp-ext— enable/disable FPU SP extension-m[no-]fpu-dp-ext— enable/disable FPU DP extension-m[no-]fpu-fma— enable/disable FPU fused-multiply-add instructions-mall-ext— turn on all extensions and instructions support. literally all of them 🔥
The following options are available when as is configured for a PowerPC processor.
-a32— generate ELF32 or XCOFF32.-a64— generate ELF64 or XCOFF64.-K PIC— setEF_PPC_RELOCATABLE_LIBin ELF flags.-mpwrx|-mpwr2— generate code for POWER/2 (RIOS2).-mpwr— generate code for POWER (RIOS1)-m601— generate code for PowerPC 601.-mppc,-mppc32,-m603,-m604— generate code for PowerPC 603/604.-m403,-m405— generate code for PowerPC 403/405.-m440— generate code for PowerPC 440. BookE and some 405 instructions.-m464— generate code for PowerPC 464.-m476— generate code for PowerPC 476.-m7400,-m7410,-m7450,-m7455— generate code for PowerPC 7400/7410/7450/7455.-m750cl,-mgekko,-mbroadway— generate code for PowerPC 750CL/Gekko/Broadway.-m821,-m850,-m860— generate code for PowerPC 821/850/860.-mppc64,-m620— generate code for PowerPC 620/625/630.-me200z2,-me200z4— generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.-me300— generate code for PowerPC e300 family.-me500,-me500x2— generate code for Motorola e500 core complex.-me500mc— generate code for Freescale e500mc core complex.-me500mc64— generate code for Freescale e500mc64 core complex.-me5500— generate code for Freescale e5500 core complex.-me6500— generate code for Freescale e6500 core complex.-mlsp— enable LSP instructions. (Disables SPE and SPE2.)-mspe— generate code for Motorola SPE instructions. (Disables LSP.)-mspe2— generate code for Freescale SPE2 instructions. (Disables LSP.)-mtitan— generate code for AppliedMicro Titan core complex.-mppc64bridge— generate code for PowerPC 64, including bridge insns.-mbooke— generate code for 32-bit BookE.-ma2— generate code for A2 architecture.-maltivec— generate code for processors with AltiVec instructions.-mvle— generate code for Freescale PowerPC VLE instructions.-mvsx— generate code for processors with Vector-Scalar (VSX) instructions.-mhtm— generate code for processors with Hardware Transactional Memory instructions.-mpower4,-mpwr4— generate code for Power4 architecture.-mpower5,-mpwr5,-mpwr5x— generate code for Power5 architecture.-mpower6,-mpwr6— generate code for Power6 architecture.-mpower7,-mpwr7— generate code for Power7 architecture.-mpower8,-mpwr8— generate code for Power8 architecture.-mpower9,-mpwr9— generate code for Power9 architecture.-mpower10,-mpwr10— generate code for Power10 architecture.-mpower11,-mpwr11— generate code for Power11 architecture.-mfuture— generate code for 'future' architecture. main character energy, honestly 👑-mcell— generate code for Cell Broadband Engine architecture.
Bestie, -mcell is listed twice in the original page. We're not deleting that, we're respecting the dupe 🙈
-mcom— generate code Power/PowerPC common instructions.-many— generate code for any architecture (PWR/PWRX/PPC).-mregnames— allow symbolic names for registers.-mno-regnames— do not allow symbolic names for registers.-mrelocatable— support for GCC's-mrelocatableoption.-mrelocatable-lib— support for GCC's-mrelocatable-liboption.-memb— setPPC_EMBbit in ELF flags.-mlittle,-mlittle-endian,-le— generate code for a little endian machine.-mbig,-mbig-endian,-be— make code for a big endian machine, periodt.-msolaris— generate code for Solaris.-mno-solaris— do not generate code for Solaris, bestie.-nops=count— if an alignment directive goes and inserts more than count nops, then it puts a branch at the very beginning to skip running all those nops. efficiency queen 💅
✨ RISC-V o'clock 💜
The following options are available when as is configured for a RISC-V processor.
-fpic,-fPIC— generate position-independent code.-fno-pic— don't generate position-independent code. this is the default, fyi.-march=ISA— pick the base isa, exactly as given by ISA. like, for example-march=rv32ima. If this option and the architecture attributes aren't set, then the assembler will go check the default configure setting--with-arch=ISA. 🫶-misa-spec=ISAspec— select the default isa spec version. If the version of ISA isn't set by-march, then the assembler helps set the version according to the default chosen spec. If this option isn't set, then the assembler checks the default configure setting--with-isa-spec=ISAspec.-mpriv-spec=PRIVspec— select the privileged spec version. We can decide whether the CSR is valid or not based on the chosen spec. If this option and the privilege attributes aren't set, then the assembler will check the default configure setting--with-priv-spec=PRIVspec.-mabi=ABI— selects the ABI, which is either"ilp32"or"lp64", optionally followed by"f","d", or"q"to signal single-precision, double-precision, or quad-precision floating-point calling convention, ornoneor"e"to signal the soft-float calling convention ("e"means a soft-float RVE ABI). so many letters bestie 😭-mrelax— take advantage of linker relaxations to reduce the number of instructions needed to materialize symbol addresses. default, iconic behavior.-mno-relax— don't do linker relaxations.-march-attr— generate the default contents for the riscv elf attribute section if the.attributedirectives aren't set. This section is what records the info that a linker or runtime loader needs to check compatibility. The info includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification.-mno-arch-attr— don't generate the default riscv elf attribute section if the.attributedirectives aren't set.-mcsr-check— enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions. no cap.-mno-csr-check— don't do CSR checking.-mlittle-endian— generate code for a little endian machine.-mbig-endian— generate code for a big endian machine.
See the info pages for documentation of the RX-specific options. 📖
✨ s390 processor family ✨ 👑
The following options are available when as is configured for the s390 processor family.
-m31,-m64— select the word size, either 31/32 bits or 64 bits.-mesa,-mzarch— select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).-march=processor— specify which s390 processor variant is the target:g5(orarch3),g6,z900(orarch5),z990(orarch6),z9-109,z9-ec(orarch7),z10(orarch8),z196(orarch9),zEC12(orarch10),z13(orarch11),z14(orarch12),z15(orarch13),z16(orarch14), orarch15. that's a whole timeline fr fr 🦋-mregnames,-mno-regnames— allow or disallow symbolic names for registers.-mwarn-areg-zero— warn whenever the operand for a base or index register has been specified but evaluates to zero. 👀-mwarn-regtype-mismatch=strict,-mwarn-regtype-mismatch=relaxed,-mwarn-regtype-mismatch=no,-mno-warn-regtype-mismatch— controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type. The default (which you can restore by using the relaxed argument) is to perform relaxed register name type checks, which allow floating point register (FPR) names%f0to%f15to be specified as argument to vector register (VR) operands and vector register (VR) names%v0to%v15to be specified as argument to floating point register (FPR) operands. This is acceptable because the FPR are embedded into the lower half of the VR, bestie, it's giving convenient 💅. Using the strict argument, strict register name type checks are performed. The no argument, which is equivalent to-mno-warn-regtype-mismatch, disables any register name type checks.
✨ TMS320C6000 ✨ 🎀
The following options are available when as is configured for a TMS320C6000 processor.
-march=arch— enable (only) instructions from architecture arch. By default, all instructions are permitted.
The following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x".
-mdsbt,-mno-dsbt— the-mdsbtoption makes the assembler generate the"Tag_ABI_DSBT"attribute with a value of1, indicating the code is using DSBT addressing. The-mno-dsbtoption, the default, makes the tag have a value of0, indicating the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. 🚨-mpid=no,-mpid=near,-mpid=far— the-mpid=option makes the assembler generate the"Tag_ABI_PID"attribute with a value indicating the form of data addressing used by the code.-mpid=no, the default, indicates position-dependent data addressing,-mpid=nearindicates position-independent addressing with GOT accesses using near DP addressing, and-mpid=farindicates position-independent addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together. 😭-mpic,-mno-pic— the-mpicoption makes the assembler generate the"Tag_ABI_PIC"attribute with a value of1, indicating the code is using position-independent code addressing, The"-mno-pic"option, the default, makes the tag have a value of0, indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together.-mbig-endian,-mlittle-endian— generate code for the specified endianness. The default is little-endian.
✨ TILE-Gx 💜
The following options are available when as is configured for a TILE-Gx processor.
-m32|-m64— select the word size, either 32 bits or 64 bits.-EB|-EL— select the endianness, either big-endian (-EB) or little-endian (-EL).
✨ Visium 🌸
The following option is available when as is configured for a Visium processor.
-mtune=arch— this option specifies the target architecture. If an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. rude but valid 💀
The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
✨ Xtensa processor ✨ 🦋
The following options are available when as is configured for an Xtensa processor.
--text-section-literals|--no-text-section-literals— control the treatment of literal pools. The default is--no-text-section-literals, which places literals in separate sections in the output file. This lets the literal pool be placed in a data RAM/ROM. With--text-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the"L32R"instructions in the text section. Literals are grouped into pools following.literal_positiondirectives or precedingENTRYinstructions. These options only affect literals referenced via PC-relative"L32R"instructions; literals for absolute mode"L32R"instructions are handled separately.--auto-litpools|--no-auto-litpools— control the treatment of literal pools. The default is--no-auto-litpools, which in the absence of--text-section-literalsplaces literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With--auto-litpools, the literals are interspersed in the text section in order to keep them as close as possible to their references, explicit.literal_positiondirectives are not required. This may be necessary for very large functions, where single literal pool at the beginning of the function may not be reachable by"L32R"instructions at the end. These options only affect literals referenced via PC-relative"L32R"instructions; literals for absolute mode"L32R"instructions are handled separately. When used together with--text-section-literals,--auto-litpoolstakes precedence. 👑--absolute-literals|--no-absolute-literals— indicate to the assembler whether"L32R"instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute"L32R"relocations. Otherwise, only the PC-relative"L32R"relocations can be used.--target-align|--no-target-align— enable or disable automatic alignment to reduce branch penalties at some expense in code size. This optimization is enabled by default. Note that the assembler will always align instructions like"LOOP"that have fixed alignment requirements.--longcalls|--no-longcalls— enable or disable transformation of call instructions to allow calls across a greater range of addresses. This option should be used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. The default is--no-longcalls. 💅--transform|--no-transform— enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The default is--transform;--no-transformshould only be used in the rare cases when the instructions must be exactly as specified in the assembly source. Using--no-transformcauses out of range instruction operands to be errors. 🚨--rename-section oldname=newname— renames theoldnamesection tonewname. bestie you can drop this one as many times as you want to rename a whole lil collection of sections 💅--trampolines/--no-trampolines— turns on/off the transformation of jump instructions so jumps can reach across a bigger range of addresses. use this when jump targets might be out of range. if there are no such jumps, this option changes literally nothing about code size or performance. default is--trampolines. 🦋--abi-windowed/--abi-call0— picks which ABI tag gets written into the".xtensa.info"section. the ABI tag says what ABI the assembly code is using. the linker will pop a warning at you if you try to link object files with inconsistent ABI tags. the default ABI is chosen by the Xtensa core configuration. 👑
The following options are available when as is configured for an Z80 processor.
@chapter Z80 Dependent Features
✨ Z80 DEPENDENT FEATURES ✨
🌸 Command-line Options 🌸
-march=CPU[-EXT...][+EXT...]— says which target processor we're doing this for. if you try to assemble an instruction that won't actually run on that processor, the assembler will hit you with an error message, no cap. here are the processor names it recognizes:"z80","z180","ez80","gbz80","z80n","r800". and on top of the basic instruction set, you can tell the assembler to accept some extension mnemonics too. for example,-march=z180+sli+infcextends z180 with SLI instructions and IN F,(C). the extensions currently supported are:"full"(all known instructions),"adl"(ADL CPU mode by default, eZ80 only),"sli"(the instruction known as SLI, SLL or SL1),"xyhl"(instructions with halves of index registers: IXL, IXH, IYL, IYH),"xdcb"(instructions like RotOp (II+d),R and BitOp n,(II+d),R),"infc"(instruction IN F,(C) or IN (C)),"outc0"(instruction OUT (C),0). ✨
ok and here's the little plot twist: instead of extending a basic instruction set, extension mnemonics starting with-revoke that functionality. so-march=z80-full+xyhlfirst removes all the default extensions, then adds support for index register halves only. sneaky but iconic.
if you don't specify this option at all, -march=z80+xyhl+infc is what you get. 💖
-local-prefix=prefix— marks every label with the specified prefix as local. but like… such a label can still be marked global explicitly in the code, so it's not a forever thing. this option does not change the default local label prefix.L, it just adds a new one. 🎀-colonless— accepts colonless labels. all symbols at the beginning of a line get treated as labels. 🫶-sdcc— accepts assembler code produced by SDCC. 🙈-fp-s=FORMAT— single precision floating point numbers format. default:ieee754(32 bit). 💜-fp-d=FORMAT— double precision floating point numbers format. default:ieee754(64 bit). 💜
👀 SEE ALSO 👀
gcc(1), ld(1), and the Info entries for binutils and ld. go read those too bestie, they're the whole friend group 🌈
📜 COPYRIGHT 📜
Copyright (c) 1991-2025 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".
and that's a wrap on the whole page, periodt 🎀 this little masterpiece is binutils-2.44, dated 2025-03-28, and it's the AS(1) man page — go assemble something cute 💅✨
📦 where this page comes from
- debian trixie: binutils-mingw-w64-ucrt64 2.44-3+12+b1
- 💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms