AS(1)

📦 version 2.45, in ubuntu questing

✨ AS(1) — GNU Development Tools ✨

Okay bestie, this is the manual for as, the GNU assembler 💖 It lives in the GNU Development Tools family, and it's the one that's built to be portable across a bunch of different chip architectures 🧚

🌸 NAME 🌸

AS is the portable GNU assembler, and honestly it's giving "works everywhere" energy ✨

💅 SYNOPSIS 💅

Here's the full lineup of ways you can call it. Don't panic, most of these are optional 🙈

as [-a[cdghilns][=file]]
 [--alternate]
 [--compress-debug-sections] [--nocompress-debug-sections]
 [-D]
 [--dump-config]
 [--debug-prefix-map old=new]
 [--defsym sym=val]
 [--elf-stt-common=[no|yes]]
 [--emulation=name]
 [-f]
 [-g] [--gstabs] [--gstabs+]
 [--gdwarf-<N>] [--gdwarf-sections]
 [--gdwarf-cie-version=VERSION]
 [--generate-missing-build-notes=[no|yes]]
 [--gsframe] [--gsframe=[no|yes]]
 [--hash-size=N]
 [--help] [--target-help]
 [--info] [--no-info]
 [-I dir]
 [-J]
 [-K]
 [--keep-locals]
 [-L]
 [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM]
 [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM]
 [--multibyte-handling=[allow|warn|warn-sym-only]]
 [--no-pad-sections]
 [-o objfile] [-R]
 [--scfi=experimental]
 [--sectname-subst]
 [--size-check=[error|warning]]
 [--statistics]
 [-v] [--verbose]
 [-version] [--version]
 [-W] [--no-warn] [--warn] [--fatal-warnings]
 [-w] [-x]
 [-Z] [@FILE]
 [target-options]
 [--|files ...]

🦋 TARGET 🦋

Okay so here's the thing: every chip family has its own extra options 💜 The ones below only matter when you're targeting that specific architecture, so pick your chip and go, no cap ✨

🌈 Target AArch64 options

[-EB|-EL]
[-mabi=ABI]

🍓 Target Alpha options

[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]

🧚 Target ARC options

[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]

🫶 Target ARM options

[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
 -mapcs-reentrant]
[-mthumb-interwork] [-k]

🎀 DESCRIPTION 🎀

okay so GNU as is really a whole family of assemblers 💅 if you've used the GNU assembler on one architecture, you'll feel right at home on another one ✨ each version shares a ton with the others, like object file formats, most assembler directives (aka pseudo-ops) and the general assembler syntax 🦋

as is mainly built to assemble the output of the GNU C compiler, gcc, so the linker, ld, can use it 🫶 that said, we really tried to make as assemble correctly everything that other assemblers for the same machine would assemble. any exceptions are written down explicitly, so no surprises 🙈 BUT it doesn't mean as always uses the exact same syntax as another assembler for the same architecture. for example, we know of several incompatible versions of 680x0 assembly language syntax. chaotic, I know 💀

each time you run as, it assembles exactly one source program 🌸 that program is made up of one or more files. (the standard input counts as a file too, btw 🧚)

you give as a command line with zero or more input file names. the input files get read from left to right 👑 any command-line argument (in any position) that doesn't have a special meaning gets treated as an input file name ✨

if you don't give as any file names, it tries to read one input file from the as standard input, which is normally your terminal 💻 you might have to type ctl-D to tell as there's no more program to assemble 😭

if you need to explicitly name the standard input file on your command line, use -- 🍓

if the source is empty, as produces a small, empty object file. tiny, but valid 🥺

as may write warnings and error messages to the standard error file (usually your terminal too) 🔥 this shouldn't happen when a compiler runs as automatically 💅 warnings tell you about an assumption as made so it could keep assembling a flawed program. errors tell you about a grave problem that stops the assembly dead 💀

if you're invoking as through the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler 🦋 the assembler arguments have to be separated from each other (and from the -Wa) by commas, no spaces ✨ for example:

gcc -c -g -O -Wa,-alh,-L file.c

this passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table) 🌈

usually you don't need the -Wa thing, because the compiler automatically passes lots of its own command-line options along to the assembler for you 🫶 if you're curious, you can call the GNU compiler driver with the -v option to see exactly what options it passes to each compilation pass, including the assembler 🔍

✨ OPTIONS ✨

  • @file — okay so this one reads command-line options from file 📜 the options it reads get slotted in right where the original @file option was. if file doesn't exist or can't be read, then the option gets treated literally and doesn't get removed 🙈

options inside file are separated by whitespace 🫧 if you need a whitespace character inside an option, wrap the whole option in single or double quotes. any character (including a backslash) can be included by putting a backslash in front of it 🦋 the file can even contain more @file options of its own, and those get processed recursively 🌀

  • -a[cdghilmns] — turns on listings, in any of a bunch of different ways 📝
    • -ac omits false conditionals
    • -ad omits debugging directives
    • -ag includes general information, like the as version and the options passed
    • -ah includes high-level source
    • -al includes assembly
    • -ali includes assembly with ginsn
    • -am includes macro expansions
    • -an omits forms processing
    • -as includes symbols
    • =file sets the name of the listing file

you can mix these together! for example, -aln gives you an assembly listing without forms processing 💅 the =file option, if you use it, has to be the last one 🎀 and by itself, -a defaults to -ahls 💖

  • --alternate — begins in alternate macro mode 🌸
  • --compress-debug-sections — compresses DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI 🗜️ heads up: the resulting object file might not be compatible with older linkers and object file utilities 💀 also, if compression would make a given section larger, it doesn't get compressed. smart 🧠
  • --compress-debug-sections=none, --compress-debug-sections=zlib, --compress-debug-sections=zlib-gnu, --compress-debug-sections=zlib-gabi, --compress-debug-sections=zstd — these control how DWARF debug sections get compressed 🎀
    • --compress-debug-sections=none is the same as --nocompress-debug-sections
    • --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are the same as plain --compress-debug-sections
    • --compress-debug-sections=zlib-gnu compresses DWARF debug sections using the obsoleted zlib-gnu format 🥀 the debug sections get renamed so they begin with .zdebug
    • --compress-debug-sections=zstd compresses DWARF debug sections using zstd ⚡
note: if compression would actually make a section larger, then it's not compressed nor renamed 👀
  • --nocompress-debug-sections — does not compress DWARF debug sections 🙅‍♀️ this is usually the default for all targets except x86/x86_64, but a configure time option can be used to override that ⚙️
  • -D — enables debugging in target specific backends, if they support it 🔧 otherwise it's ignored. even if it's ignored, this option is still accepted, for script compatibility with calls to other assemblers 🫶
  • --debug-prefix-map old=new — when assembling files in directory old, debugging information describing them gets recorded as if they were in new instead 🗺️
  • --defsym sym=value — defines the symbol sym to be value before the input file gets assembled ✨ value has to be an integer constant. just like in C, a leading 0x means hexadecimal and a leading 0 means octal 🔢 you can override the symbol's value inside a source file with the .set pseudo-op 💅
  • --dump-config — displays how the assembler is configured, and then exits 🧾
  • --elf-stt-common=no, --elf-stt-common=yes — these control whether the ELF assembler should generate common symbols with the STT_COMMON type 🦋 the default can be controlled by the --enable-elf-stt-common configure option 🛠️
  • --emit-local-absolute — emits even pre-defined (local) absolute symbols to the outgoing symbol table 📤 heads up: this isn't the exact opposite of --strip-local-absolute, so don't treat them as mirror images 🙃
  • --emulation=name — if the assembler is configured to support multiple different target configurations, this option lets you pick the one you want 🎯
  • -f — "fast"! 🏎️ skips whitespace and comment preprocessing, assuming the source is compiler output 🤖
  • -g, --gen-debug — generates debugging information for each assembler source line, using whichever debug format the target prefers 🐛 right now that means either STABS, ECOFF or DWARF2 🌈 when the format is DWARF, a .debug_info and .debug_line section only gets emitted when the assembly file doesn't generate one itself 💖
  • --gstabs — generates stabs debugging information for each assembler line 🔍 this might help you debug assembler code, if your debugger can handle it 🙏
  • --gstabs+ — generates stabs debugging information for each assembler line too, but with GNU extensions that probably only gdb can handle 💀 other debuggers might crash or refuse to read your program because of them 😭 this might help debug assembler code. right now, the only GNU extension is the location of the current working directory at assembling time 📍
  • --gdwarf-2 — generates DWARF2 debugging information for each assembler line 🦋 this might help debug assembler code, if your debugger can handle it. note: this option is only supported by some targets, not all of them 🎯
  • --gdwarf-3 — basically the same as --gdwarf-2, except it allows for the possibility of extra debug information as per version 3 of the DWARF specification 📚 heads up: turning this on doesn't guarantee any extra information gets generated. that choice is made per target 🤷‍♀️
  • --gdwarf-4 — basically the same as --gdwarf-2, except it allows for the possibility of extra debug information as per version 4 of the DWARF specification 📚 again, turning this on doesn't guarantee any extra information, since the choice is made on a per target basis 🎀
  • --gdwarf-5 — basically the same as --gdwarf-2, except it allows for the possibility of extra debug information as per version 5 of the DWARF specification 📚 yep, same deal: no guarantees, and it depends on the target 💅
  • --gdwarf-sections — instead of creating a .debug_line section, this creates a series of .debug_line.foo sections, where foo is the name of the matching code section 🧩 for example, a code section called .text.func gets its DWARF line number information placed into a section called .debug_line.text.func. if the code section is just called .text, the debug line section still gets called just .debug_line, no suffix 🌸
  • --gdwarf-cie-version=version — controls which version of DWARF Common Information Entries (CIEs) get produced 🧾 if you don't specify this flag, the default is version 1, though some targets can change that default. other possible values for version are 3 or 4 🔢
  • --generate-missing-build-notes=yes, --generate-missing-build-notes=no — these control whether the ELF assembler should generate GNU Build attribute notes when none are in the input sources 🏗️ the default can be controlled by the --enable-generate-build-notes configure option ⚙️
  • --gsframe, --gsframe, --gsframe=no, --gsframe=yes — creates a .sframe section from CFI directives 🪄 the explicit --gsframe=yes behaves the same as --gsframe, and you can suppress generation with --gsframe=no 🙅‍♀️
  • --hash-size N — ignored! 🫠 it's only supported so the command line stays compatible with other assemblers 🫶
  • --help — prints a summary of the command-line options and then exits 📋
  • --target-help — prints a summary of all the target specific options and then exits 🎯
  • --info — doesn't suppress informational messages 📢
  • --no-info — suppresses informational messages 🤫
  • -I dir — adds directory dir to the search list for .include directives 📂
  • -J — don't warn about signed overflow 🙈

okay so the options list keeps going, bestie, and it's getting spicy 🌶️✨

  • -K — 🚨 this one warns you when difference tables get altered for long displacements. Keep an eye out for it 👀
  • -L, --keep-locals — keeps local symbols in the symbol table 🗝️ These are the ones that start with the system's local label prefix, which is usually .L on ELF systems or L on traditional a.out systems.
  • --listing-lhs-width=number — sets the max width, in words, of the output data column in an assembler listing to number 📏
  • --listing-lhs-width2=number — same vibe as above, but for the continuation lines in a listing 🧚
  • --listing-rhs-width=number — caps how wide an input source line can be when it shows up in a listing, at number bytes 💅
  • --listing-cont-lines=number — limits how many lines get printed in a listing for one line of input. The cap is number + 1 🌸
  • --multibyte-handling=allow, --multibyte-handling=warn, --multibyte-handling=warn-sym-only, --multibyte-handling=warn_sym_only — decides how the assembler deals with multibyte characters in your input 🌈 Default is allow, which lets them through with zero drama, and you can get that back any time by using allow. warn makes the assembler complain every single time it spots a multibyte character 😭 warn-sym-only is the chill version: it only warns when a symbol gets defined with a multibyte name. (Referencing an undefined symbol won't trigger a warning, fyi.) Note that warn_sym_only is also accepted, just spelled with underscores instead of dashes 🫶
  • --no-pad-sections — tells the assembler to stop padding the ends of output sections out to the section's alignment. Padding is the default, but it can waste space you actually need on targets with tight memory constraints 🥺
  • -o objfile — names the object-file output from as as objfile 🎀
  • -R — folds the data section into the text section 🍓
  • --reduce-memory-overheads — literally does nothing ("ignored") 🙈 It's only here so tools that pass the same option to both the assembler and the linker don't get upset.
  • --scfi=experimental — this one is a whole mood 🔮 It controls whether the assembler should synthesize CFI for hand-written input. If your input already has some synthesizable CFI directives, the assembler ignores them and emits a warning. Also, --scfi=experimental is NOT meant for compiler-generated code, inline assembly included. It's still work in progress, and only the System V AMD64 ABI is supported right now.

Every input function in assembly has to start with the .type directive, and ideally gets closed off with a .size directive. When you use SCFI, each .type directive makes GAS start a brand new FDE (a.k.a. Function Descriptor Entry). That means each .type basically finalises whatever block of instructions came before it as its own distinct FDE 🧠✨

  • --sectname-subst — honors substitution sequences in section names 💖
  • --size-check=error, --size-check=warning — throws an error or a warning for an invalid ELF .size directive. Pick your fighter 🥊
  • --statistics — prints the maximum space (in bytes) and the total time (in seconds) the assembly used 📊
  • --strip-local-absolute — removes local absolute symbols from the outgoing symbol table 🧹
  • -v, --verbose — prints the as version 🦋
  • --version, -version — prints the as version and then exits 👑
  • -W, --no-warn — suppresses warning messages. Shh 🤫
  • --warn — doesn't suppress warnings, and doesn't treat them as errors either. Just vibes 🌷
  • --fatal-warnings — treats warnings as errors. No second chances 💀
  • -w — ignored 🙃
  • -x — also ignored 🙃
  • -Z — generates an object file even after errors. Chaotic good energy 🌪️
  • -- | files ... — the input is either standard input or source files to assemble 📥

🌈 AArch64 options

These are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). ARM girlies, this is for you 🫶

  • -EB — marks the output as encoded for a big-endian processor 🌊
  • -EL — marks the output as encoded for a little-endian processor 🌊
  • -mabi=abi — tells the assembler which ABI your source code uses. The recognized arguments are "ilp32" and "lp64", which decide whether the generated object file is ELF32 or ELF64. The default is "lp64" 🧁
  • -mcpu=processor[+extension...] — picks the target processor. If you try to assemble an instruction that won't run on that processor, the assembler will throw an error at you 🚫 These processor names are recognized: "cortex-a34", "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73", "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77", "cortex-a78", "cortex-a78ae", "cortex-a78c", "cortex-a510", "cortex-a520", "cortex-a710", "cortex-a720", "ares", "exynos-m1", "falkor", "neoverse-n1", "neoverse-n2", "neoverse-e1", "neoverse-v1", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1", "xgene2", "cortex-r82", "cortex-x1", "cortex-x2", "cortex-x3", and "cortex-x4". The special name "all" lets the assembler accept instructions valid for any supported processor, including every optional extension 🤯

Beyond the basic instruction set, you can tell the assembler to accept, or restrict, various extension mnemonics that extend the processor ✨

If some implementations of a processor can have an extension, those extensions get switched on automatically. So you usually won't need to specify extra extensions yourself 💅

  • -march=architecture[+extension...] — picks the target architecture. Same deal as -mcpu: the assembler errors out if you try to assemble something that won't execute on that architecture 🛑 These architecture names are recognized: "armv8-a", "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a", "armv8.5-a", "armv8.6-a", "armv8.7-a", "armv8.8-a", "armv8.9-a", "armv8-r", "armv9-a", "armv9.1-a", "armv9.2-a", "armv9.3-a", "armv9.4-a", and "armv9.5-a" 🌸

If you specify both -mcpu and -march, the assembler goes with the -mcpu setting. If you specify neither, it defaults to -mcpu=all 🫠

The architecture option can be extended with the same instruction set extension options as -mcpu. The difference is that extensions aren't always enabled by default for -march 🦋

  • -mverbose-error — turns on verbose error messages for AArch64 gas. This one is on by default 📣
  • -mno-verbose-error — turns verbose error messages off for AArch64 gas 🤐
  • -menable-sysreg-checking — turns on error messages for when you try to assemble a system register access that won't execute on the target architecture 🧐

🍄 Alpha options

These are available when as is configured for an Alpha processor 🌙

  • -mcpu — picks the target processor. If you try to assemble an instruction that won't run on it, the assembler might either expand the instruction as a macro or throw an error. This option is equivalent to the .arch directive 🪄 These processor names are recognized: 21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6", "ev67", and "ev68". The special name "all" lets the assembler accept instructions valid for any Alpha processor 🌟

Here's the tea ☕ For existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (like 21064) enable the processor-specific PALcode instructions. The "electro-vlasic" names (like "ev4") do not 🤓

  • -mdebug, -no-mdebug — enables or disables generating .mdebug encapsulation for stabs directives and procedure descriptors. By default .mdebug switches on automatically once the first stabs directive shows up 🔍
  • -relax — forces all relocations to be put into the object file, instead of saving space by resolving some of them at assembly time. Heads up: this doesn't propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. It can still be useful in specific applications though 🧩
  • -replace, -noreplace — enables or disables optimizing procedure calls, both at assemblage and at link time. These are only available for VMS targets, and -replace is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual 📚
  • -g — used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels have to get passed through to the object file. Otherwise this option does nothing 🤷‍♀️
  • -Gsize — a local common symbol bigger than size gets placed in ".bss", while smaller ones go into ".sbss" 🧸
  • -F, -32addr — ignored, kept around for backward compatibility 🕰️

🌿 ARC options

These are available when as is configured for an ARC processor 🐚

  • -mcpu=cpu — selects the core processor variant 🧬
  • -EB | -EL — picks big-endian (-EB) or little-endian (-EL) output 🌊
  • -mcode-density — enables the Code Density extension instructions 🍬

🤖 ARM options

These are available when as is configured for the ARM processor family 💜

  • -mcpu=processor[+extension...] — specifies which ARM processor variant is the target 🎯
  • -march=architecture[+extension...] — specifies which ARM architecture variant the target uses 🏛️
  • -mfpu=floating-point-format — selects which Floating Point architecture is the target 🔢
  • -mfloat-abi=abi — selects which floating point ABI is in use 🧮
  • -mthumb — enables Thumb-only instruction decoding 🌙
  • -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant — selects which procedure calling convention is in use 📞
  • -EB | -EL — picks big-endian (-EB) or little-endian (-EL) output 🌊
  • -mthumb-interwork — says the code was generated with interworking between Thumb and ARM code in mind 🤝
  • -mccs — turns on CodeComposer Studio assembly syntax compatibility mode 🎛️
  • -k — specifies that PIC code has been generated 🧩

The following options are available when as is configured for the Blackfin processor family, so if you're working on Blackfin stuff, these are your besties 💜

  • -mcpu=processor[-sirevision] — okay so this picks the target processor 🎯 The optional sirevision part does nothing in the assembler 🙈 It's just there so GCC can pass its -mcpu= option straight down without any drama. If you try to assemble an instruction that won't run on your target processor, the assembler will throw an error at you 💀 These are the processor names it recognises: bf504, bf506, bf512, bf514, bf516, bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf535 (not implemented yet), bf536, bf537, bf538, bf539, bf542, bf542m, bf544, bf544m, bf547, bf547m, bf548, bf548m, bf549, bf549m, bf561, and bf592 ✨
  • -mfdpic — assemble for the FDPIC ABI 🦋
  • -mno-fdpic, -mnopic — turns -mfdpic off again 🙅‍♀️

The following options are available when as is configured for the Linux kernel BPF processor family.

@chapter BPF Dependent Features

✨ BPF Options ✨

  • -EB — big-endian eBPF output, bestie 🍓
  • -EL — little-endian eBPF output 💜
  • -mdialect=dialect — picks the assembly language dialect the assembler recognises while it's working 🧚 It supports normal and pseudoc 🫶
  • -misa-spec=spec — sets the version of the BPF instruction set to use when assembling 🔥 The BPF ISA versions it supports are v1 v2, v3 and v4 👑

The value xbpf can be specified to recognise extra instructions that GCC uses for testing purposes. But beware, this is not valid BPF 💀

  • -mno-relax — tells the assembler to not relax instructions 🌸

Note that if no endianness option is specified on the command line, the host endianness gets used 🌈 See the info pages for documentation of the CRIS-specific options 📚

The following options are available when as is configured for the C-SKY processor family.

  • -march=archname — assemble for architecture archname 🎀 The --help option lists valid values for archname 💅
  • -mcpu=cpuname — assemble for architecture cpuname 🎀 The --help option lists valid values for cpuname ✨
  • -EL, -mlittle-endian — generates little-endian output 💖
  • -EB, -mbig-endian — generates big-endian output 💖
  • -fpic, -pic — generates position-independent code 🦋
  • -mljump, -mno-ljump — enables or disables turning the short branch instructions jbf, jbt, and jbr into jmpi 🔥 This option is for V2 processors only. It gets ignored on CK801 and CK802 targets, since those don't support the jmpi instruction, and it's enabled by default for other processors 🙈
  • -mbranch-stub, -mno-branch-stub — passes R_CKCORE_PCREL_IMM26BY2 relocations for bsr instructions through to the linker 🧚

This option is only available for bare-metal C-SKY V2 ELF targets, where it's enabled by default. It cannot be used in code that will be dynamically linked against shared libraries 😭

  • -force2bsr, -mforce2bsr, -no-force2bsr, -mno-force2bsr — enables or disables turning jbsr instructions into bsr 💅 This option is always enabled (and -mno-force2bsr gets ignored) for CK801/CK802 targets. It's also always enabled when -mbranch-stub is in effect 👑
  • -jsri2bsr, -mjsri2bsr, -no-jsri2bsr, -mno-jsri2bsr — enables or disables turning jsri instructions into bsr ✨ This one's enabled by default 🌈
  • -mnolrw, -mno-lrw — enables or disables turning lrw instructions into a movih/ori pair 🦋
  • -melrw, -mno-elrw — enables or disables extended lrw instructions 💜 This option is enabled by default for CK800-series processors 🍓
  • -mlaf, -mliterals-after-func, -mno-laf, -mno-literals-after-func — enables or disables placing literal pools after each function 🎀
  • -mlabr, -mliterals-after-br, -mno-labr, -mnoliterals-after-br — enables or disables placing literal pools after unconditional branches 🌸 This option is enabled by default 💖
  • -mistack, -mno-istack — enables or disables interrupt stack instructions ⭐ This option is enabled by default on CK801, CK802, and CK802 processors 🫶

The following options explicitly enable certain optional instructions. Heads up: these features also get switched on automatically when you use -mcpu= to specify a processor that supports them 🫶

  • -mhard-float — enables hard float instructions 🔥
  • -mmp — enables multiprocessor instructions 👑
  • -mcp — enables coprocessor instructions 🌈
  • -mcache — enables the cache prefetch instruction 🧚
  • -msecurity — enables C-SKY security instructions 🔒
  • -mtrust — enables C-SKY trust instructions 💜
  • -mdsp — enables DSP instructions ✨
  • -medsp — enables enhanced DSP instructions 💅
  • -mvdsp — enables vector DSP instructions 🦋

The following options are available when as is configured for an Epiphany processor.

  • -mepiphany — the both 32 and 16 bit instructions are allowed here 🌈 This is the default behaviour 🫶
  • -mepiphany16 — restricts the permitted instructions to just the 16 bit set 🙈

The following options are available when as is configured for an H8/300 processor. @chapter H8/300 Dependent Features

✨ Options ✨

The Renesas H8/300 version of as has one machine-dependent option 💅

  • -h-tick-hex — supports H'00 style hex constants alongside 0x00 style 🍓
  • -mach=name — sets the H8300 machine variant 🎀 The following machine names are recognised: h8300h, h8300hn, h8300s, h8300sn, h8300sx and h8300sxn ✨

The following options are available when as is configured for an i386 processor.

  • --32 | --x32 | --64 — selects the word size, either 32 bits or 64 bits 💖 --32 implies the Intel i386 architecture, while --x32 and --64 imply the AMD x86-64 architecture with 32-bit or 64-bit word size respectively 🦋

These options are only available with the ELF object file format, and they need the necessary BFD support to be included. On a 32-bit platform, you have to add --enable-64-bit-bfd to configure to enable 64-bit usage, and use x86-64 as the target platform 🤓

  • -n — by default, x86 GAS swaps out multiple nop instructions used for alignment within code sections for multi-byte nop instructions, like leal 0(%esi,1),%esi 🌸 This switch disables that optimisation if a single byte nop (0x90) is explicitly specified as the fill byte for alignment 🙅‍♀️
  • --divide — on SVR4-derived platforms, the character / is treated as a comment character, so it can't be used in expressions 😭 The --divide option turns / into a normal character 🎀 It doesn't disable / at the beginning of a line starting a comment, and it doesn't affect using # for starting a comment 💅
  • -march=CPU[+EXTENSION...] — this picks the target processor 🎯 The assembler will throw an error if you try to assemble an instruction that won't run on the target processor 💀 These processor names are recognised: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, znver5, btver1, btver2, generic32 and generic64 ✨

Besides the basic instruction set, the assembler can be told to accept extra extension mnemonics 🧚 For example, -march=i686+sse4+vmx extends i686 with sse4 and vmx 🔥 These extensions are currently supported: 8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb, avx10.1, avx10.1/512, avx10.1/256, avx10.1/128, user_msr, msr_imm, apx_f, avx10.2, avx10.2/512, avx10.2/256, avx10.2/128, movrs, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8 amx_movrs, amx_avx512, amx_tile, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, snp, invlpgb, tlbsync, rmpquery, rmpread, svme, gmism2, gmiccs, padlockrng2, padlockphe2, padlockxmodx and padlock 🌈 Note that these extension mnemonics can be prefixed with no to revoke the respective (and any dependent) functionality 💅 Also, the suffixes permitted on -march=avx10.<N> enforce a vector length restriction. So even though these are otherwise "enabling" options, using these suffixes will disable all insns with wider vector or mask register operands 🙈

When the .arch directive is used with -march, the .arch directive will take precedent 👑

  • -mtune=CPU — this option picks a processor to optimise for 🎯 When it's used together with the -march option, only instructions of the processor specified by the -march option will be generated 💖

Valid CPU values are identical to the processor list of -march=CPU 🫶

These flags are where the assembler gets picky about instruction operands, SSE, AVX, and encoding details, so pay attention bestie 🦋

  • -moperand-check=none, -moperand-check=warning, -moperand-check=error — These decide whether the assembler bothers checking certain instruction operands or operand combos 🔍 The classic example is an instruction where the operand size can't be figured out from the operands, and you didn't spell it out with an instruction suffix. none skips the checks entirely. warning (the default ✨) throws a warning when a check fails. error makes a failed check a full-on error 🙅‍♀️
  • -msse2avx — Tells the assembler to encode SSE instructions with a VEX prefix, which means AVX has to be available 🌈 SSE instructions that use extended GPRs get encoded with an EVEX prefix instead, and that one needs AVX512 or AVX10 to be available 💅
  • -muse-unaligned-vector-move — Makes the assembler encode aligned vector moves as unaligned vector moves 🫶
  • -msse-check=none, -msse-check=warning, -msse-check=error — These control whether the assembler checks SSE instructions at all 👀 none is the default, so no checking happens unless you ask for it. warning gives you a warning for any SSE instruction, and error gives you an error for any SSE instruction 💀
  • -mavxscalar=128, -mavxscalar=256 — Decides how scalar AVX instructions get encoded 🎀 128 (the default) encodes them with a 128-bit vector length, and 256 uses a 256-bit vector length 🌸
WARNING: Don't use this for production code 🚨 Because of CPU errata, the resulting code may not work on certain models. Not the vibe for real projects, bestie 😭
  • -mvexwig=0, -mvexwig=1 — Controls how the assembler encodes VEX.W-ignored (WIG) VEX instructions 🦋 0 (the default) encodes them with vex.w = 0. 1 encodes WIG EVEX instructions with vex.w = 1 🧚
WARNING: Don't use this for production code 🚨 Due to CPU errata, the resulting code may not work on certain models. Seriously, keep this one out of your real stuff 💀
  • -mevexlig=128, -mevexlig=256, -mevexlig=512 — Picks the vector length for length-ignored (LIG) EVEX instructions 💜 128 is the default ✨ 256 and 512 encode them with a 256-bit or 512-bit vector length, respectively 🌈
  • -mevexwig=0, -mevexwig=1 — Controls how the assembler encodes w-ignored (WIG) EVEX instructions 🍓 0 (the default) encodes them with evex.w = 0, and 1 encodes them with evex.w = 1 🫶
  • -mmnemonic=att, -mmnemonic=intel — Picks the instruction mnemonic used for matching instructions 🔥 Heads up: the .att_mnemonic and .intel_mnemonic directives take priority over this flag 👑
  • -msyntax=att, -msyntax=intel — Picks the instruction syntax used when processing instructions 💅 The .att_syntax and .intel_syntax directives win over this one, so keep that in mind 🙈
  • -mnaked-reg — Lets you skip the % prefix on registers 🌸 Same deal as before: the .att_syntax and .intel_syntax directives take precedence over it ✨
  • -madd-bnd-prefix — Forces the assembler to slap a BND prefix on every branch 🎀 Even if you never wrote one in your source code, it's getting added anyway 🧚
  • -mno-shared — Okay, this one's a little spicy 🌶️ On ELF targets, the assembler normally optimizes away non-PLT relocations against defined non-weak global branch targets that have default visibility. -mshared tells the assembler to generate code that could end up in a shared library, where those non-weak global branch targets with default visibility can be preempted 🦋 The downside is that the resulting code is slightly bigger. And this option only affects branch instructions, nothing else 💜
  • -mbig-obj — On PE/COFF targets, this forces the big object file format 🌈 That format lets you have more than 32768 sections, so it's giving "I need a lot of sections" energy 📦
  • -momit-lock-prefix=no, -momit-lock-prefix=yes — These control how the assembler encodes the lock prefix 🔒 It's really a workaround for processors that choke on the lock prefix 🙈 yes omits all lock prefixes, and no encodes the lock prefix as usual (the default ✨)
WARNING: This option can only be safely used with single-core, single-thread computers 🚨 Don't try it on anything fancier, bestie 😭
  • -mfence-as-lock-add=no, -mfence-as-lock-add=yes — These control how lfence, mfence and sfence get encoded 🍓 yes encodes all three as lock addl $0x0, (%rsp) in 64-bit mode and as lock addl $0x0, (%esp) in 32-bit mode 🧚 no encodes them as usual, which is the default 💅
  • -mrelax-relocations=no, -mrelax-relocations=yes — Controls whether the assembler generates relax relocations ✨ In 32-bit mode that means R_386_GOT32X, and in 64-bit mode it means R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX 🌈 yes generates relax relocations, and no doesn't 🫶 The default can be changed with the configure option --enable-x86-relax-relocations 🔥
  • -mtls-check=no, -mtls-check=yes — Controls whether the assembler checks TLS relocations 🔍 yes checks them, no skips the check 🙅‍♀️ The default can be set with the configure option --enable-x86-tls-check 👑
  • -malign-branch-boundary=NUM — Decides how the assembler aligns branches that have segment prefixes or NOPs 🦋 NUM has to be a power of 2, and it should be 0 or at least 16 💜 Branches get aligned within a NUM byte boundary 🌸 The default is -malign-branch-boundary=0, which means branches don't get aligned at all 🙈
  • -malign-branch=TYPE[+TYPE...] — Picks which types of branches get aligned 🧚 TYPE can be a combo of jcc (conditional jumps), fused (fused conditional jumps), jmp (unconditional jumps), call (calls), ret (rets), and indirect (indirect jumps and calls) 🎀 The default is -malign-branch=jcc+fused+jmp ✨
  • -malign-branch-prefix-size=NUM — Sets the maximum number of prefixes an instruction can have and still get its branch aligned 🌈 NUM should be between 0 and 5, and the default NUM is 5 💅
  • -mbranches-within-32B-boundaries — This one's a whole package deal 📦 It aligns conditional jumps, fused conditional jumps and unconditional jumps within a 32 byte boundary, with up to 5 segment prefixes on an instruction 💖 It's equivalent to -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5, so you can skip typing all that out 🫶 The default doesn't align branches 🙈
  • -mlfence-after-load=no, -mlfence-after-load=yes — Controls whether the assembler generates lfence after load instructions 🔥 yes generates it, and no doesn't, which is the default 💀
  • -mlfence-before-indirect-branch=none, -mlfence-before-indirect-branch=all, -mlfence-before-indirect-branch=register, -mlfence-before-indirect-branch=memory — Controls whether the assembler generates lfence before indirect near branch instructions 🛡️ all generates lfence before an indirect near branch via register and issues a warning before an indirect near branch via memory 👑 It also implicitly sets -mlfence-before-ret=shl when there's no explicit -mlfence-before-ret= 🌈 register generates lfence before an indirect near branch via register 🫶 memory issues a warning before an indirect near branch via memory 🙈 none doesn't generate lfence or issue any warning, and it's the default ✨
Heads up: lfence won't be generated before an indirect near branch via register when you use -mlfence-after-load=yes, since the lfence gets generated after the branch target register is loaded 🧠
  • -mlfence-before-ret=none, -mlfence-before-ret=shl, -mlfence-before-ret=or, -mlfence-before-ret=yes, -mlfence-before-ret=not — Controls whether the assembler generates lfence before ret 💜 or generates an or instruction with lfence 🌸 shl and yes both generate a shl instruction with lfence 🎀 not generates a not instruction with lfence 💅 none doesn't generate lfence, and it's the default 🦋
  • -mx86-used-note=no, -mx86-used-note=yes — Controls whether the assembler generates the GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes 🧚 The default can be controlled with the --enable-x86-used-note configure option ✨
  • -mevexrcig=rne, -mevexrcig=rd, -mevexrcig=ru, -mevexrcig=rz — These decide how SAE-only EVEX instructions get encoded 🌈 rne encodes the RC bits of the EVEX instruction as 00, and it's the default ✨ rd, ru and rz encode the SAE-only EVEX instructions with 01, 10 and 11 RC bits, respectively 💖
  • -mamd64, -mintel64 — Tells the assembler to accept only the AMD64 or Intel64 ISA in 64-bit mode 👑 By default, it accepts the common ISA, plus the Intel64 only and AMD64 ISAs 🫶
  • -O0 | -O | -O1 | -O2 | -Os — Optimizes instruction encoding for smaller instruction size 🍓 -O and -O1 do a bunch of cute stuff: they encode 64-bit register load instructions with a 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bit immediates 💅 They encode 64-bit register clearing instructions as 32-bit register clearing instructions 🌸 They encode 256-bit/512-bit VEX/EVEX vector register clearing instructions as 128-bit VEX vector register clearing instructions 🦋 They encode 128-bit/256-bit EVEX vector register load/store instructions as VEX vector register load/store instructions 🧚 And they encode 128-bit/256-bit EVEX packed integer logical instructions as 128-bit/256-bit VEX packed integer logical instructions 💜

-O2 is where things get spicy 🔥 It includes everything from -O1 and also encodes 256-bit/512-bit EVEX vector register clearing instructions, plus 128-bit EVEX vector register clearing instructions. In 64-bit mode, VEX encoded instructions with commutative source operands also get their source operands swapped, but only if that lets them use the 2-byte VEX prefix form instead of the 3-byte one 🧚 Certain forms of AND, plus OR with the same (register) operand specified twice, also get switched over to TEST ✨

  • -Os — bestie, this one includes -O2 optimization and also encodes 16-bit, 32-bit and 64-bit register tests with an immediate as an 8-bit register test with an immediate 💅 -O0 turns this optimization off 🙈

🦋 Ubicom IP2K series

These options show up when as is configured for the Ubicom IP2K series 🌸

  • -mip2022ext — specifies that the extended IP2022 instructions are allowed ✨
  • -mip2022 — restores the default behaviour, which limits the permitted instructions to just the basic IP2022 ones 💖

🎀 Renesas M32C and M16C processors

These options show up when as is configured for the Renesas M32C and M16C processors 💜

  • -m32c — assemble M32C instructions 🍓
  • -m16c — assemble M16C instructions (this is the default) 👑
  • -relax — enables support for link-time relaxations 🌈
  • -h-tick-hex — supports H'00 style hex constants in addition to 0x00 style 🫶

🌸 Renesas M32R (formerly Mitsubishi M32R) series

These options show up when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series 🦋

  • --m32rx — specifies which processor in the M32R family is the target 🔥 The default is normally the M32R, but this option switches it to the M32RX ✨
  • --warn-explicit-parallel-conflicts or --Wp — produces warning messages whenever questionable parallel constructs show up 👀
  • --no-warn-explicit-parallel-conflicts or --Wnp — does not produce warning messages when questionable parallel constructs show up 🙅‍♀️

💅 Motorola 68000 series

These options show up when as is configured for the Motorola 68000 series 🧚

  • -l — shortens references to undefined symbols to one word instead of two 💫
  • -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 — specifies which processor in the 68000 family is the target 🎀 The default is normally the 68020, but this can be changed at configuration time ⭐
  • -m68881 | -m68882 | -mno-68881 | -mno-68882 — tells it whether the target machine does (or does not) have a floating-point coprocessor 🌈 The default is to assume a coprocessor for the 68020, 68030, and cpu32 🍓 The basic 68000 isn't compatible with the 68881, but you can specify a combo of the two, since it's possible to emulate the coprocessor instructions with the main processor 🤓
  • -m68851 | -mno-68851 — tells it whether the target machine does (or does not) have a memory-management unit coprocessor 💜 The default is to assume an MMU for the 68020 and up ✨

For details about the PDP-11 machine dependent features options, see PDP-11-Options 👀

  • -mpic | -mno-pic — generates position-independent (or position-dependent) code 🦋 The default is -mpic 💖
  • -mall or -mall-extensions — enables all instruction set extensions. This is the default 🔥
  • -mno-extensions — disables all instruction set extensions 🙅‍♀️
  • -mextension | -mno-extension — enables (or disables) one particular instruction set extension 🫶
  • -mcpu — enables the instruction set extensions supported by a particular CPU, and disables all other extensions 👑
  • -mmachine — enables the instruction set extensions supported by a particular machine model, and disables all other extensions 💅

🧚 picoJava processor

These options show up when as is configured for a picoJava processor 🌸

  • -mb — generates "big endian" format output 🍓
  • -ml — generates "little endian" format output 💜

🌈 PRU processor

These options show up when as is configured for a PRU processor ✨

  • -mlink-relax — assumes that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression 🧐 If they are all zeros, LD would shorten the LDI32 instruction to a single LDI 💀 In that case, "as" will output DIFF relocations for diff expressions 🫶
  • -mno-link-relax — assumes that LD would not optimize LDI32 instructions 🙈 As a consequence, DIFF relocations will not be emitted 💔
  • -mno-warn-regname-label — does not warn if a label name matches a register name 🎀 Assembler programmers usually want this warning to be emitted, but C compilers may want to turn it off 💅

🦋 MIPS processor

These options show up when as is configured for a MIPS processor 🌈

  • -G num — sets the largest size of an object that can be referenced implicitly with the "gp" register 🔥 It's only accepted for targets that use ECOFF format, such as a DECstation running Ultrix 🖥️ The default value is 8 ✨
  • -EB — generates "big endian" format output 🍓
  • -EL — generates "little endian" format output 💜
  • -mips1 | -mips2 | -mips3 | -mips4 | -mips5 | -mips32 | -mips32r2 | -mips32r3 | -mips32r5 | -mips32r6 | -mips64 | -mips64r2 | -mips64r3 | -mips64r5 | -mips64r6 — generates code for a particular MIPS Instruction Set Architecture level 👑 -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000, and -mips4 is an alias for -march=r8000 💫 -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively 🤯
  • -march=cpu — generates code for a particular MIPS CPU 🎀
  • -mtune=cpu — schedules and tunes for a particular MIPS CPU 🧠
  • -mfix7000 | -mno-fix7000 — causes nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions 🙈
  • -mfix-rm7000 | -mno-fix-rm7000 — causes nops to be inserted if a dmult or dmultu instruction is followed by a load instruction 🫠
  • -mfix-r5900 | -mno-fix-r5900 — does not try to schedule the preceding instruction into the delay slot of a branch placed at the end of a short loop of six instructions or fewer. It always schedules a "nop" instruction there instead 🛑 The short loop bug can, under certain conditions, make loops run only once or twice, thanks to a hardware bug in the R5900 chip 😭
⚠️ The short loop bug is a real hardware issue on the R5900 chip, so keep -mfix-r5900 in mind if your loops are acting weird 🙃
  • -mdebug | -no-mdebug — causes stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections 🧚
  • -mpdr | -mno-pdr — controls generation of ".pdr" sections 💅
  • -mgp32 | -mfp32 — register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times 📏 -mgp32 controls the size of general-purpose registers, and -mfp32 controls the size of floating-point registers 💜
  • -mgp64 | -mfp64 — register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times 📏 -mgp64 controls the size of general-purpose registers, and -mfp64 controls the size of floating-point registers 🌈
  • -mfpxx — register sizes are normally inferred from the ISA and ABI, but using this flag in combination with -mabi=32 enables an ABI variant that operates correctly with floating-point registers that are 32 or 64 bits wide 🦋
  • -modd-spreg | -mno-odd-spreg — enables use of floating-point operations on odd-numbered single-precision registers when the ISA supports it 🔥 -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg ✨
  • -mips16 | -no-mips16 — generates code for the MIPS 16 processor 🎀 This is equivalent to putting ".module mips16" at the start of the assembly file 📝 -no-mips16 turns this option off 🙅‍♀️
  • -mmips16e2 | -mno-mips16e2 — enables the use of MIPS16e2 instructions in MIPS16 mode 💫 This is equivalent to putting ".module mips16e2" at the start of the assembly file 📝 -mno-mips16e2 turns this option off 🙅‍♀️
  • -mmicromips | -mno-micromips — generates code for the microMIPS processor 🌸 This is equivalent to putting ".module micromips" at the start of the assembly file 📝 -mno-micromips turns this option off 🙅‍♀️ This is equivalent to putting ".module nomicromips" at the start of the assembly file 🤔
  • -msmartmips | -mno-smartmips — enables the SmartMIPS extension to the MIPS32 instruction set 💜 This is equivalent to putting ".module smartmips" at the start of the assembly file 📝 -mno-smartmips turns this option off 🙅‍♀️
  • -mips3d | -no-mips3d — generates code for the MIPS-3D Application Specific Extension 🧚 This tells the assembler to accept MIPS-3D instructions 🫶 -no-mips3d turns this option off 🙅‍♀️
  • -mdmx | -no-mdmx — generates code for the MDMX Application Specific Extension 🌈 This tells the assembler to accept MDMX instructions 🫶 -no-mdmx turns this option off 🙅‍♀️
  • -mdsp | -mno-dsp — generates code for the DSP Release 1 Application Specific Extension 🎀 This tells the assembler to accept DSP Release 1 instructions 🫶 -mno-dsp turns this option off 🙅‍♀️
  • -mdspr2 | -mno-dspr2 — generates code for the DSP Release 2 Application Specific Extension ✨ This option implies -mdsp, and it tells the assembler to accept DSP Release 2 instructions 🫶 -mno-dspr2 turns this option off 🙅‍♀️
  • -mdspr3 | -mno-dspr3 — generates code for the DSP Release 3 Application Specific Extension 🔥 This option implies -mdsp and -mdspr2, and it tells the assembler to accept DSP Release 3 instructions 🫶 -mno-dspr3 turns this option off 🙅‍♀️
  • -mmsa | -mno-msa — generates code for the MIPS SIMD Architecture Extension 🦋 This tells the assembler to accept MSA instructions 🫶 -mno-msa turns this option off 🙅‍♀️
  • -mxpa | -mno-xpa — generates code for the MIPS eXtended Physical Address (XPA) Extension 🌸 This tells the assembler to accept XPA instructions 🫶 -mno-xpa turns this option off 🙅‍♀️
  • -mmt | -mno-mt — generates code for the MT Application Specific Extension 💖 This tells the assembler to accept MT instructions 🫶 -mno-mt turns this option off 🙅‍♀️
  • -mmcu, -mno-mcu — okay so this one turns on the MCU Application Specific Extension 💖. It tells the assembler to accept MCU instructions, and -mno-mcu turns it back off 🙅‍♀️
  • -mcrc, -mno-crc — this generates code for the MIPS cyclic redundancy check (CRC) Application Specific Extension ✨. It tells the assembler to accept CRC instructions, and -mno-crc switches it off 🦋
  • -mginv, -mno-ginv — this one is for the Global INValidate (GINV) Application Specific Extension 🧚. It tells the assembler to accept GINV instructions, and -mno-ginv turns it off 💅
  • -mloongson-mmi, -mno-loongson-mmi — this is the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension 🎀. It tells the assembler to accept MMI instructions, and -mno-loongson-mmi turns it off 🌸
  • -mloongson-cam, -mno-loongson-cam — generates code for the Loongson Content Address Memory (CAM) instructions 🍓. It tells the assembler to accept Loongson CAM instructions, and -mno-loongson-cam turns this option off 🫶
  • -mloongson-ext, -mno-loongson-ext — this one covers the Loongson EXTensions (EXT) instructions ⭐. It tells the assembler to accept Loongson EXT instructions, and -mno-loongson-ext turns it off 🔥
  • -mloongson-ext2, -mno-loongson-ext2 — this is the Loongson EXTensions R2 (EXT2) instructions 👑. This option implies -mloongson-ext. It tells the assembler to accept Loongson EXT2 instructions, and -mno-loongson-ext2 turns this option off 💜
  • -minsn32, -mno-insn32 — okay this one is giving strict 🙈. Only 32-bit instruction encodings get used when generating code for the microMIPS processor, so no 16-bit instructions at all. It's equivalent to putting .set insn32 at the start of the assembly file. -mno-insn32 turns it off, and that's equivalent to putting .set noinsn32 at the start of the assembly file. By default -mno-insn32 is selected, so every instruction is fair game 🌈
  • --construct-floats, --no-construct-floats — --no-construct-floats disables building double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register 🧁. By default --construct-floats is selected, so those floating point constants can be constructed ✨
  • --relax-branch, --no-relax-branch — --relax-branch turns on relaxation of out-of-range branches 🦄. By default --no-relax-branch is selected, which means any out-of-range branches produce an error 💀
  • -mignore-branch-isa, -mno-ignore-branch-isa — ignores branch checks for invalid transitions between ISA modes 🙃. The semantics of branches doesn't provide for an ISA mode switch, so in most cases the ISA mode a branch was encoded for has to match the ISA mode of the branch's target label. That's why GAS has checks that verify in branch assembly that the two ISA modes match. -mignore-branch-isa disables these checks. By default -mno-ignore-branch-isa is selected, so any invalid branch that needs a transition between ISA modes produces an error 🚫
  • -mnan=encoding — pick between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format 🧠. The latter is the default 💅
  • --emulation=name — this one used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both 🕰️. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. It's kept around for backwards compatibility 🫠

The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself has no effect now, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are the preferred options instead 💖

  • -nocpp — as ignores this one 🙄. It's only accepted for compatibility with the native tools 🧚
  • --trap, --no-trap, --break, --no-break — these control how to deal with multiplication overflow and division by zero 💥. --trap or --no-break (which are synonyms) take a trap exception, and they only work for Instruction Set Architecture level 2 and higher. --break or --no-trap (also synonyms, and the default) take a break exception 🎀
  • -n — when you use this, as will issue a warning every time it generates a nop instruction from a macro ⚠️

The following options are available when as is configured for a LoongArch processor. 🌸

  • -fpic, -fPIC — generates position-independent code 🦋
  • -fno-pic — doesn't generate position-independent code (this is the default) 🙅‍♀️

The following options are available when as is configured for a Meta processor. 🧚

  • -mcpu=metac11 — generates code for Meta 1.1 ✨
  • -mcpu=metac12 — generates code for Meta 1.2 🍓
  • -mcpu=metac21 — generates code for Meta 2.1 💜
  • -mfpu=metac21 — lets code use the FPU hardware of Meta 2.1 🔥

See the info pages for documentation of the MMIX-specific options. 📚

The following options are available when as is configured for a NDS32 processor. 🌈

  • -O1 — optimizes for performance 🏎️
  • -Os — optimizes for space 📦
  • -EL — produces little endian data output 💫
  • -EB — produces little endian data output (yes, the original page says little endian for this one too, so I'm keeping it exactly like that 🙈)
  • -mpic — generates PIC 🫶
  • -mno-fp-as-gp-relax — suppresses fp-as-gp relaxation for this file 🚫
  • -mb2bb-relax — back-to-back branch optimization 🔁
  • -mno-all-relax — suppresses all relaxation for this file 🙅‍♀️
  • -march=<arch name> — assembles for the architecture arch name, which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, or v2s 🏛️
  • -mbaseline=<baseline> — assembles for the baseline baseline, which could be v2, v3, or v3m 🧱
  • -mfpu-freg=FREG — specifies an FPU configuration 🎛️
    • 0 — 8 SP / 4 DP registers
    • 1 — 16 SP / 8 DP registers
    • 2 — 32 SP / 16 DP registers
    • 3 — 32 SP / 32 DP registers
  • -mabi=abi — specifies an ABI version, where abi could be v1, v2, v2fp, or v2fpp 👑
  • -m[no-]mac — enables or disables multiply instructions support 🔢
  • -m[no-]div — enables or disables divide instructions support ➗
  • -m[no-]16bit-ext — enables or disables 16-bit extension 🧩
  • -m[no-]dx-regs — enables or disables the d0/d1 registers 🗂️
  • -m[no-]perf-ext — enables or disables the Performance extension 🏃‍♀️
  • -m[no-]perf2-ext — enables or disables the Performance extension 2 🏃‍♀️🏃‍♀️
  • -m[no-]string-ext — enables or disables the String extension 🧵
  • -m[no-]reduced-regs — enables or disables the Reduced Register configuration (GPR16) option 🪶
  • -m[no-]audio-isa-ext — enables or disables the AUDIO ISA extension 🎶
  • -m[no-]fpu-sp-ext — enables or disables the FPU SP extension 🔢
  • -m[no-]fpu-dp-ext — enables or disables the FPU DP extension 🔢🔢
  • -m[no-]fpu-fma — enables or disables the FPU fused-multiply-add instructions 🧮
  • -mall-ext — turns on support for all extensions and instructions 🌟

The following options are available when as is configured for a PowerPC processor. 💅

  • -a32 — generates ELF32 or XCOFF32 📏
  • -a64 — generates ELF64 or XCOFF64 📐
  • -K PIC — sets EF_PPC_RELOCATABLE_LIB in ELF flags 🏷️
  • -mpwrx, -mpwr2 — generates code for POWER/2 (RIOS2) 🛰️
  • -mpwr — generates code for POWER (RIOS1) 🚀
  • -m601 — generates code for PowerPC 601 🕹️
  • -mppc, -mppc32, -m603, -m604 — generates code for PowerPC 603/604 💿
  • -m403, -m405 — generates code for PowerPC 403/405 📼
  • -m440 — generates code for PowerPC 440, BookE and some 405 instructions 📀
  • -m464 — generates code for PowerPC 464 🎞️
  • -m476 — generates code for PowerPC 476 🎬
  • -m7400, -m7410, -m7450, -m7455 — generates code for PowerPC 7400/7410/7450/7455 📺
  • -m750cl, -mgekko, -mbroadway — generates code for PowerPC 750CL/Gekko/Broadway 🎮
  • -m821, -m850, -m860 — generates code for PowerPC 821/850/860 🖨️
  • -mppc64, -m620 — generates code for PowerPC 620/625/630 🧠
  • -me200z2, -me200z4 — generates code for e200 variants, where e200z2 comes with LSP and e200z4 comes with SPE 🚗
  • -me300 — generates code for the PowerPC e300 family 🚙
  • -me500, -me500x2 — generates code for the Motorola e500 core complex 🏍️
  • -me500mc — generates code for the Freescale e500mc core complex 🛵
  • -me500mc64 — generates code for the Freescale e500mc64 core complex 🛺
  • -me5500 — generates code for the Freescale e5500 core complex 🚐
  • -me6500 — generates code for the Freescale e6500 core complex 🚌
  • -mlsp — enables LSP instructions (this disables SPE and SPE2) 🔕
  • -mspe — generates code for Motorola SPE instructions (this disables LSP) 🔇
  • -mspe2 — generates code for Freescale SPE2 instructions (this disables LSP) 🔇
  • -mtitan — generates code for the AppliedMicro Titan core complex 🗻
  • -mppc64bridge — generates code for PowerPC 64, including bridge insns 🌉
  • -mbooke — generates code for 32-bit BookE 📖
  • -ma2 — generates code for the A2 architecture 🧪
  • -maltivec — generates code for processors with AltiVec instructions 🎹
  • -mvle — generates code for Freescale PowerPC VLE instructions 🧾
  • -mvsx — generates code for processors with Vector-Scalar (VSX) instructions 📈
  • -mhtm — generates code for processors with Hardware Transactional Memory instructions 🧾
  • -mpower4, -mpwr4 — generates code for the Power4 architecture 🌀
  • -mpower5, -mpwr5, -mpwr5x — generates code for the Power5 architecture 🌀🌀
  • -mpower6, -mpwr6 — generates code for the Power6 architecture ⚡
  • -mpower7, -mpwr7 — generates code for the Power7 architecture ⚡⚡
  • -mpower8, -mpwr8 — generates code for the Power8 architecture 🌟
  • -mpower9, -mpwr9 — generates code for the Power9 architecture 🌟🌟
  • -mpower10, -mpwr10 — generates code for the Power10 architecture 💫
  • -mpower11, -mpwr11 — generates code for the Power11 architecture 🌠
  • -mfuture — generates code for the 'future' architecture 🔮
  • -mcell — generates code for the Cell Broadband Engine architecture 🎱
  • -mcom — generates code for Power/PowerPC common instructions 🤝
  • -many — generates code for any architecture (PWR/PWRX/PPC) 🌍
  • -mregnames — allows symbolic names for registers 🏷️
  • -mno-regnames — does not allow symbolic names for registers 🙅‍♀️
  • -mrelocatable — supports GCC's -mrelocatable option 🧭
  • -mrelocatable-lib — supports GCC's -mrelocatable-lib option 🧭🧭
  • -memb — sets the PPC_EMB bit in ELF flags 🧷
  • -mlittle, -mlittle-endian, -le — generates code for a little endian machine 💖

Okay, the RISC-V stuff is next, so let's get into it 🌈

  • -mbig, -mbig-endian, -be — generates code for a big endian machine 🌸
  • -msolaris — generates code for Solaris ✨
  • -mno-solaris — nope, does NOT generate code for Solaris 🙅‍♀️
  • -nops=count — if an alignment directive would insert more than count nops, it puts a branch at the beginning so the nops get skipped and never actually run 🧚

🌈 RISC-V 🌈

Okay, these only show up when as is configured for a RISC-V processor, so keep that in mind, bestie 🦋

  • -fpic, -fPIC — generates position-independent code 💖
  • -fno-pic — doesn't generate position-independent code. This is the default 🙈
  • -march=ISA|Profiles|Profiles_ISA — picks the base isa, whether you pass it as ISA, Profiles, or Profies_ISA. For example: -march=rv32ima, -march=RVI20U64, -march=RVI20U64_d. If this option and the architecture attributes aren't set, the assembler checks the default configure setting --with-arch=ISA instead 🔥
  • -misa-spec=ISAspec — picks the default isa spec version. If the ISA version isn't set by -march, the assembler helps out by setting the version based on the default spec it chose. If this option isn't set, the assembler checks the default configure setting --with-isa-spec=ISAspec 📜
  • -mpriv-spec=PRIVspec — picks the privileged spec version. This decides whether a CSR is valid or not based on the spec you chose. If this option and the privilege attributes aren't set, the assembler checks the default configure setting --with-priv-spec=PRIVspec 👑
  • -mabi=ABI — selects the ABI, which is either "ilp32" or "lp64". You can optionally tack on "f", "d", or "q" to say you want the single-precision, double-precision, or quad-precision floating-point calling convention. Or you can use none of those, or "e", to get the soft-float calling convention ("e" means a soft-float RVE ABI) 💅
  • -mrelax — takes advantage of linker relaxations to cut down the number of instructions needed to materialize symbol addresses. This is the default ✨
  • -mno-relax — no linker relaxations for you 🙅‍♀️
  • -march-attr — generates the default contents for the riscv elf attribute section, but only if the .attribute directives aren't set. This section records the info a linker or runtime loader needs to check compatibility. That includes the ISA string, the stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of the privileged spec 🧠
  • -mno-arch-attr — doesn't generate the default riscv elf attribute section if the .attribute directives aren't set 🫶
  • -mcsr-check — enables CSR checking for the ISA-dependent CRS and the read-only CSR. ISA-dependent CSRs are only valid when the specific ISA is set. Read-only CSRs can't be written by the CSR instructions 🔒
  • -mno-csr-check — no CSR checking, bestie 🙃
  • -mlittle-endian — generates code for a little endian machine 🌷
  • -mbig-endian — generates code for a big endian machine 🌸

For the RX-specific options, go check the info pages, because they've got the full tea on those 📚

🧚 s390 🧚

These options are available when as is configured for the s390 processor family 💜

  • -m31, -m64 — picks the word size, either 31/32 bits or 64 bits 🔥
  • -mesa, -mzarch — picks the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch) 🏛️
  • -march=processor — tells it which s390 processor variant is the target. You can choose g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or z17 (or arch15) ⭐
  • -mregnames, -mno-regnames — allows or disallows symbolic names for registers 🎀
  • -mwarn-areg-zero — warns whenever the operand for a base or index register has been specified but evaluates to zero ⚠️
  • -mwarn-regtype-mismatch=strict, -mwarn-regtype-mismatch=relaxed, -mwarn-regtype-mismatch=no, -mno-warn-regtype-mismatch — controls whether the assembler does register name type checks and throws a warning when there's a mismatch with the operand register type. The default, which you can get back with the relaxed argument, does relaxed checks. Those let floating point register (FPR) names %f0 to %f15 be used as arguments for vector register (VR) operands, and vector register (VR) names %v0 to %v15 be used for floating point register (FPR) operands. That's fine because the FPRs are embedded in the lower half of the VR 🫧. With the strict argument, the strict register name type checks happen. The no argument, which is the same as -mno-warn-regtype-mismatch, turns off all register name type checks 🙈

🦋 TMS320C6000 🦋

These options are available when as is configured for a TMS320C6000 processor 🧁

  • -march=arch — only enables instructions from architecture arch. By default, all instructions are allowed 💖

The accepted values of arch are "c62x", "c64x", "c64x+", "c67x", "c67x+", and "c674x" ✨

  • -mdsbt, -mno-dsbt — the -mdsbt option makes the assembler generate the "Tag_ABI_DSBT" attribute with a value of 1, which means the code uses DSBT addressing. The -mno-dsbt option, the default, makes the tag have a value of 0, which means the code doesn't use DSBT addressing. The linker will warn you if objects of different type (DSBT and non-DSBT) get linked together ⚠️
  • -mpid=no, -mpid=near, -mpid=far — the -mpid= option makes the assembler generate the "Tag_ABI_PID" attribute, with a value showing what kind of data addressing the code uses. -mpid=no, the default, means position-dependent data addressing. -mpid=near means position-independent addressing with GOT accesses using near DP addressing. -mpid=far means position-independent addressing with GOT accesses using far DP addressing. The linker will warn you if objects built with different settings of this option get linked together 🌈
  • -mpic, -mno-pic — the -mpic option makes the assembler generate the "Tag_ABI_PIC" attribute with a value of 1, meaning the code uses position-independent code addressing. The "-mno-pic" option, the default, gives the tag a value of 0, meaning position-dependent code addressing. The linker will warn you if objects of different type (position-dependent and position-independent) get linked together 🔗
  • -mbig-endian, -mlittle-endian — generates code for the endianness you specify. The default is little-endian 🌷

🐉 TILE-Gx 🐉

These options are available when as is configured for a TILE-Gx processor 💅

  • -m32 | -m64 — picks the word size, either 32 bits or 64 bits 🔥
  • -EB | -EL — picks the endianness, either big-endian (-EB) or little-endian (-EL) 🫶

🛸 Visium 🛸

This option is available when as is configured for a Visium processor 👽

  • -mtune=arch — specifies the target architecture. If you try to assemble an instruction that won't execute on the target architecture, the assembler throws an error message at you 😭

The names it recognizes are "mcm24", "mcm", "gr5", and "gr6" 💜

🌙 Xtensa 🌙

These options are available when as is configured for an Xtensa processor 🌟

  • --text-section-literals, --no-text-section-literals — controls how literal pools get treated. The default is --no-text-section-literals, which puts literals in separate sections in the output file, so the literal pool can live in data RAM/ROM. With --text-section-literals, the literals get interspersed in the text section so they stay as close as possible to their references. You might need this for big assembly files, where the literals would otherwise be out of range of the "L32R" instructions in the text section. Literals get grouped into pools following ".literal_position" directives or right before "ENTRY" instructions. These options only affect literals referenced via PC-relative "L32R" instructions. Literals for absolute mode "L32R" instructions are handled separately 🧩
  • --auto-litpools, --no-auto-litpools — also controls how literal pools get treated. The default is --no-auto-litpools, which, when --text-section-literals isn't used, puts literals in separate sections in the output file so the literal pool can live in data RAM/ROM. With --auto-litpools, the literals get interspersed in the text section to stay as close as possible to their references, and you don't need explicit ".literal_position" directives. This can be necessary for very large functions, where one literal pool at the beginning of the function might not be reachable by "L32R" instructions at the end. These options only affect literals referenced via PC-relative "L32R" instructions. Literals for absolute mode "L32R" instructions are handled separately. When you use it together with --text-section-literals, --auto-litpools takes precedence 👑
  • --absolute-literals, --no-absolute-literals — tells the assembler whether "L32R" instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute "L32R" relocations. Otherwise, only the PC-relative "L32R" relocations can be used 📍
  • --target-align, --no-target-align — enables or disables automatic alignment to reduce branch penalties, at some expense in code size. This optimization is on by default. Note that the assembler will always align instructions like "LOOP" that have fixed alignment requirements 🏃‍♀️
  • --longcalls, --no-longcalls — enables or disables transforming call instructions so calls can reach a greater range of addresses. Use this when call targets might be out of range. It may hurt both code size and performance, but the linker can usually optimize away the unnecessary overhead when a call ends up within range. The default is --no-longcalls 📞
  • --transform, --no-transform — enables or disables all assembler transformations of Xtensa instructions, including both relaxation and optimization. The default is --transform. Only use --no-transform in the rare cases when the instructions must be exactly as you wrote them in the assembly source. Using --no-transform makes out of range instruction operands into errors 🚨

the rename option: --rename-section oldname=newname. Rename the oldname section to newname, and you can repeat this one as many times as you need to rename several sections. 🎀

  • --trampolines | --no-trampolines: Turns on (or off) rewriting of jump instructions so they can reach a wider range of addresses. Reach for this when jump targets might be out of range. If there are no such jumps, it doesn't change code size or performance at all. The default is --trampolines. 🦋
  • --abi-windowed | --abi-call0: Picks the ABI tag that gets written into the .xtensa.info section, which tells everyone what ABI the assembly code uses. The linker will warn you if you try to link object files with mismatched ABI tags, so be careful, bestie 😭. If you don't choose, the default comes from the Xtensa core configuration. 💜

The following options are available when as is configured for a Z80 processor. ✨

@chapter Z80 Dependent Features

✨ Command-line Options ✨

  • -march=CPU[-EXT...][+EXT...]: Picks the target processor. If you try to assemble an instruction that won't run on that processor, the assembler throws an error at you 💀. These processor names are recognised: "z80", "z180", "ez80", "gbz80", "z80n", "r800". Beyond the basic instruction set, you can also ask for some extension mnemonics. For example, -march=z180+sli+infc extends z180 with SLI instructions and IN F,(C). These extensions are currently supported:
    • "full" (all known instructions)
    • "adl" (ADL CPU mode by default, eZ80 only)
    • "sli" (instruction known as SLI, SLL or SL1)
    • "xyhl" (instructions with halves of index registers: IXL, IXH, IYL, IYH)
    • "xdcb" (instructions like RotOp (II+d),R and BitOp n,(II+d),R)
    • "infc" (instruction IN F,(C) or IN (C))
    • "outc0" (instruction OUT (C),0)

Quick heads up: instead of adding onto a basic set, extensions starting with - revoke that functionality 🙈. For example, -march=z80-full+xyhl first strips out all default extensions, then adds support for index register halves only.

If you don't specify this option, the assembler assumes -march=z80+xyhl+infc. 🌸

  • -local-prefix=prefix: Marks every label starting with the given prefix as local. You can still explicitly mark one of those labels as global in your code, though 🧚. This doesn't change the default local label prefix .L, it just adds a new one alongside it.
  • -colonless: Accepts labels without colons. Every symbol at the start of a line gets treated as a label ✨.
  • -sdcc: Accepts assembler code produced by SDCC 🍓.
  • -fp-s=FORMAT: Sets the format for single precision floating point numbers. The default is ieee754 (32 bit).
  • -fp-d=FORMAT: Sets the format for double precision floating point numbers. The default is ieee754 (64 bit).

✨ SEE ALSO ✨

gcc(1), ld(1), and the Info entries for binutils and ld. Go poke around those if you want more 🔥.

Copyright (c) 1991-2025 Free Software Foundation, Inc. 💖

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". 🫶

That's the whole AS page, bestie! You're officially a manual-reading legend now 👑💅 binutils 2.45, December 2025, no cap ✨🌈

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