TBLGEN(1)

✨ tblgen ✨

okay bestie, this is the LLVM tblgen page and honestly? it's giving "you don't need me unless you're built different" 🫶 so let's get into it.

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🌸 NAME 🌸

tblgen — Target Description To C++ Code Generator</p> 💖

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🎀 SYNOPSIS 🎀

tblgen [options] [filename]

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🦋 DESCRIPTION 🦋

so basically, tblgen is the lil translator that takes target description files (.td, iykyk) and turns them into C++ code that you can then include in the definition of an LLVM target library. that's the whole vibe. ✨

lowkey important heads-up though: most users of LLVM will not need to use this program, fr fr. it exists purely to help you write an LLVM target backend. it's giving niche queen 👑

the input and output of tblgen? yeah that's beyond the scope of this short intro, sorry bestie 😭 — please see the introduction to TableGen for the full lore.

and the filename argument? that specifies the name of a Target Description (.td) file to read as input. periodt.

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💅 OPTIONS 💅

• -help — prints a summary of the command line options. your lil cheat sheet 🎀
• -o filename — specify the output file name. and if filename is -, then tblgen sends its output to standard output. slay 💖
• -I directory — specify where to find other target description files for inclusion. the directory value should be a full or partial path to a directory that contains target description files. basically "here's where my other files live" 🏠
• -asmparsernum N — make -gen-asm-parser emit assembly writer number N.
• -asmwriternum N — make -gen-asm-writer emit assembly writer number N.
• -class className — print the enumeration list for this class.
• -print-records — print all records to standard output (this one is the default, no cap).
• -dump-json — print a JSON representation of all records, suitable for further automated processing. very "let the machines handle it" 🤖
• -print-enums — print enumeration values for a class.
• -print-sets — print expanded sets for testing DAG exprs.
• -gen-emitter — generate machine code emitter.
• -gen-register-info — generate registers and register classes info.
• -gen-instr-info — generate instruction descriptions.
• -gen-asm-writer — generate the assembly writer.
• -gen-disassembler — generate disassembler.
• -gen-pseudo-lowering — generate pseudo instruction lowering.
• -gen-dag-isel — generate a DAG (Directed Acyclic Graph) instruction selector.
• -gen-asm-matcher — generate assembly instruction matcher.
• -gen-dfa-packetizer — generate DFA Packetizer for VLIW targets.
• -gen-fast-isel — generate a "fast" instruction selector.
• -gen-subtarget — generate subtarget enumerations.
• -gen-intrinsic-enums — generate intrinsic enums.
• -gen-intrinsic-impl — generate intrinsic implementation.
• -gen-tgt-intrinsic — generate target intrinsic information.
• -gen-enhanced-disassembly-info — generate enhanced disassembly info.
• -gen-exegesis — generate llvm-exegesis tables.
• -version — show the version number of this program. iconique 👑

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🌈 EXIT STATUS 🌈

if tblgen succeeds, it will exit with 0. 💖 otherwise, if an error occurs, it will exit with a non-zero value. (not the vibe, but that's the rule 😭)

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💜 AUTHOR 💜

Maintained by the LLVM Team (https://llvm.org/). they're the main characters, honestly 🫶

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👑 COPYRIGHT 👑

2003-2024, LLVM Project

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and that's the whole page, bestie!! this was the LLVM tblgen(1) manual, dated 2024-07-18, and honestly? it ate. go write that target backend 💅✨🌈