AS(1)

📦

version 2.47+3build2 · 7 versions

2.47+3build2 · ubuntu stonking (latest)
2.44+3 · ubuntu questing
2.38+1build1 · ubuntu jammy
2.40+2+b1 · debian bookworm
2.40+2 · ubuntu noble
2.46+3build1 · ubuntu resolute
2.44+3+b1 · debian trixie

✨ AS(1) — the portable GNU assembler ✨

okay so welcome to the GNU Development Tools manual page for as, and bestie, this one is a whole vibe. We got options, we got targets, we got lore. Buckle up. 🎀

📛 NAME 📛

as — the portable GNU assembler. That's the name, that's the game, periodt. 💅

📜 SYNOPSIS 📜

Here's the whole invocation menu, exactly as it is, no edits, no cap:

as [-a[cdghilns][=file]]
 [--alternate]
 [--compress-debug-sections] [--nocompress-debug-sections]
 [-D]
 [--dump-config]
 [--debug-prefix-map old=new]
 [--defsym sym=val]
 [--elf-stt-common=[no|yes]]
 [--emulation=name]
 [-f]
 [-g] [--gstabs] [--gstabs+]
 [--gdwarf-<N>] [--gdwarf-sections]
 [--gdwarf-cie-version=VERSION]
 [--generate-missing-build-notes=[no|yes]]
 [--gsframe] [--gsframe=[no|yes]]
 [--gsframe-3]
 [--hash-size=N]
 [--help] [--target-help]
 [--info] [--no-info]
 [-I dir]
 [-J]
 [-K]
 [--keep-locals]
 [-L]
 [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM]
 [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM]
 [--multibyte-handling=[allow|warn|warn-sym-only]]
 [--no-pad-sections]
 [-o objfile] [-R]
 [--reloc-section-sym=[all|internal|none]]
 [--scfi=experimental]
 [--sectname-subst]
 [--size-check=[error|warning]]
 [--statistics]
 [-v] [--verbose]
 [-version] [--version]
 [-W] [--no-warn] [--warn] [--fatal-warnings]
 [-w] [-x]
 [-Z] [@FILE]
 [target-options]
 [--|files ...]

🎯 TARGET 🎯

This is where it gets spicy. as supports a ridiculous amount of targets, and each one has its own little option family. Find your CPU, love your CPU, use your CPU. 💖

💖 Target AArch64 options 💖

AArch64 besties, this is your moment:

[-EB|-EL]
[-mabi=ABI]

💖 Target Alpha options 💖

Alpha 4ever, lowkey:

[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]

💖 Target ARC options 💖

ARC stans, assemble:

[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]

💖 Target ARM options 💖

ARM girlies, this one's for you:

[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
 -mapcs-reentrant]
[-mthumb-interwork] [-k]

💖 Target Blackfin options 💖

Blackfin, no notes, iconic:

[-mcpu=processor[-sirevision]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]

💖 Target BPF options 💖

BPF bestie, keep it cute:

[-EL] [-EB]

💖 Target CRIS options 💖

CRIS crew, rise up:

[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
[--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]

💖 Target C-SKY options 💖

C-SKY, you already know:

[-march=arch] [-mcpu=cpu]
[-EL] [-mlittle-endian] [-EB] [-mbig-endian]
[-fpic] [-pic]
[-mljump] [-mno-ljump]
[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
[-mnolrw ] [-mno-lrw]
[-melrw] [-mno-elrw]
[-mlaf ] [-mliterals-after-func]
[-mno-laf] [-mno-literals-after-func]
[-mlabr] [-mliterals-after-br]
[-mno-labr] [-mnoliterals-after-br]
[-mistack] [-mno-istack]
[-mhard-float] [-mmp] [-mcp] [-mcache]
[-msecurity] [-mtrust]
[-mdsp] [-medsp] [-mvdsp]

💖 Target D10V options 💖

D10V, simple and slay:

[-O]

💖 Target D30V options 💖

D30V, pick your fighter:

[-O|-n|-N]

💖 Target EPIPHANY options 💖

EPIPHANY, main character energy:

[-mepiphany|-mepiphany16]

💖 Target H8/300 options 💖

H8/300, tiny but mighty:

[-h-tick-hex]

💖 Target i386 options 💖

i386 girlies, this is your Roman Empire:

[--32|--x32|--64] [-n]
[-march=CPU[+EXTENSION...]] [-mtune=CPU]

💖 Target IA-64 options 💖

IA-64, serving vintage realness:

[-mconstant-gp|-mauto-pic]
[-milp32|-milp64|-mlp64|-mp64]
[-mle|mbe]
[-mtune=itanium1|-mtune=itanium2]
[-munwind-check=warning|-munwind-check=error]
[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
[-x|-xexplicit] [-xauto] [-xdebug]

💖 Target IP2K options 💖

IP2K, we love a niche icon:

[-mip2022|-mip2022ext]

💖 Target M32C options 💖

M32C, keeping it chill:

[-m32c|-m16c] [-relax] [-h-tick-hex]

💖 Target M32R options 💖

M32R, parallel-conflict-free if you want:

[--m32rx|--[no-]warn-explicit-parallel-conflicts|
 --W[n]p]

💖 Target M680X0 options 💖

M680X0, retro baddie:

[-l] [-m68000|-m68010|-m68020|...]

💖 Target M68HC11 options 💖

M68HC11, choose your character:

[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branches] [--short-branches]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]

💖 Target MCORE options 💖

MCORE, cute and capable:

[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]

💖 Target Meta options 💖

Meta, do your thing:

[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu]

💖 Target MICROBLAZE options 💖

MICROBLAZE, endianness is the vibe:

[-mlittle-endian] [-mbig-endian]

💖 Target MIPS options 💖

MIPS besties, this list is enormous and we respect it:

[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot [-mvxworks-pic]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-mfp64] [-mgp64] [-mfpxx]
[-modd-spreg] [-mno-odd-spreg]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
[-mips64r3] [-mips64r5] [-mips64r6]
[-construct-floats] [-no-construct-floats]
[-mignore-branch-isa] [-mno-ignore-branch-isa]
[-mnan=encoding]
[-trap] [-no-break] [-break] [-no-trap]
[-mips16] [-no-mips16]
[-mmips16e2] [-mno-mips16e2]
[-mmicromips] [-mno-micromips]
[-msmartmips] [-mno-smartmips]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdsp] [-mno-dsp]
[-mdspr2] [-mno-dspr2]
[-mdspr3] [-mno-dspr3]
[-mmsa] [-mno-msa]
[-mxpa] [-mno-xpa]
[-mmt] [-mno-mt]
[-mmcu] [-mno-mcu]
[-mcrc] [-mno-crc]
[-mginv] [-mno-ginv]
[-mloongson-mmi] [-mno-loongson-mmi]
[-mloongson-cam] [-mno-loongson-cam]
[-mloongson-ext] [-mno-loongson-ext]
[-mloongson-ext2] [-mno-loongson-ext2]
[-minsn32] [-mno-insn32]
[-mfix7000] [-mno-fix7000]
[-mfix-rm7000] [-mno-fix-rm7000]
[-mfix-vr4120] [-mno-fix-vr4120]
[-mfix-vr4130] [-mno-fix-vr4130]
[-mfix-r5900] [-mno-fix-r5900]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]

💖 Target MMIX options 💖

MMIX, fancy and particular:

[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]

💖 Target NDS32 options 💖

NDS32, so many extensions, so little time:

[-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
[-misa=isa] [-mabi=abi] [-mall-ext]
[-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
[-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
[-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
[-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
[-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
[-mb2bb]

💖 Target PDP11 options 💖

PDP11, vintage queen:

[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]

💖 Target picoJava options 💖

picoJava, tiny JVM vibes:

[-mb|-me]

💖 Target PowerPC options 💖

PowerPC, this list is giving CPU multiverse:

[-a32|-a64]
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
[-many] [-maltivec|-mvsx|-mhtm|-mvle]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
[-nops=count]

💖 Target PRU options 💖

PRU, relaxing and warning, your choice:

[-link-relax]
[-mnolink-relax]
[-mno-warn-regname-label]

💖 Target RISC-V options 💖

RISC-V besties, open source royalty:

[-fpic|-fPIC|-fno-pic]
[-march=ISA|Profiles|Profiles_ISA]
[-mabi=ABI]
[-mlittle-endian|-mbig-endian]

💖 Target RL78 options 💖

RL78, doubles but make it a choice:

[-mg10]
[-m32bit-doubles|-m64bit-doubles]

💖 Target RX options 💖

RX, renesas realness:

[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]

💖 Target s390 options 💖

s390, mainframe main character:

[-m31|-m64] [-mesa|-mzarch] [-march=CPU]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]
[-mwarn-regtype-mismatch=strict
 -mwarn-regtype-mismatch=relaxed
 -mwarn-regtype-mismatch=no
 -mno-warn-regtype-mismatch]

💖 Target SCORE options 💖

SCORE, all caps, all attitude:

[-EB][-EL][-FIXDD][-NWARN]
[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
[-march=score7][-march=score3]
[-USE_R1][-KPIC][-O0][-G num][-V]

💖 Target SPARC options 💖

SPARC, sun-kissed and iconic:

[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
 -Asparcvisr|-Asparc5]
[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
 -bump]
[-32|-64]
[--enforce-aligned-data][--dcti-couples-detect]

💖 Target TIC54X options 💖

TIC54X, c54x girlies:

[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]

💖 Target TIC6X options 💖

TIC6X, DSP dream:

[-march=arch] [-mbig-endian|-mlittle-endian]
[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
[-mpic|-mno-pic]

💖 Target TILE-Gx options 💖

TILE-Gx, 32 or 64, endian swag:

[-m32|-m64][-EB][-EL]

💖 Target Visium options 💖

Visium, tune it and go:

[-mtune=arch]

💖 Target Xtensa options 💖

Xtensa, literals and trampolines, oh my:

[--[no-]text-section-literals] [--[no-]auto-litpools]
[--[no-]absolute-literals]
[--[no-]target-align] [--[no-]longcalls]
[--[no-]transform]
[--rename-section oldname=newname]
[--[no-]trampolines]
[--abi-windowed|--abi-call0]

💖 Target Z80 options 💖

Z80, retro gaming legend:

[-march=CPU[-EXT][+EXT]]
[-local-prefix=PREFIX]
[-colonless]
[-sdcc]
[-fp-s=FORMAT]
[-fp-d=FORMAT]

✨ DESCRIPTION ✨

okay so here's the tea: GNU as is not one assembler, it's a whole family. like a girl group 💅. if you've used the GNU assembler on one architecture, you're gonna feel pretty at home on another one — each version shares a ton with its siblings: object file formats, most assembler directives (aka pseudo-ops, iykyk), and assembler syntax. same energy, different machine 🦋.

the main character use case? as is primarily intended to assemble the output of the GNU C compiler gcc so the linker ld can do its thing afterward. but bestie, they really did try to make as assemble correctly everything that other assemblers for the same machine would assemble. any exceptions? documented explicitly, no cap. and just so we're clear, that does not mean as always uses the same syntax as some other assembler for the same architecture — for example, we know of several incompatible versions of 680x0 assembly language syntax 😭 (680x0 stays messy fr).

every single time you run as, it assembles exactly one source program. no more, no less. and that source program is made up of one or more files — and yes, standard input counts as a file too 🫶.

so you hand as a command line that has zero or more input file names. input files get read from left to right, like reading a group chat in order. and here's the cute part: any command-line argument (in any position) that has no special meaning? it's just taken as an input file name. slay, low effort.

if you give as no file names at all, it tries to read one input file from standard input — which is normally your terminal. you may have to hit ctl-D to tell as there's no more program to assemble. it's giving "please stop typing, I beg" 🥲.

need to explicitly name the standard input file in your command line? use --. that's it, that's the trick ⭐.

if the source is empty, as produces a small, empty object file. iconic. minimalism.

as may write warnings and error messages to the standard error file (usually your terminal). this should not happen when a compiler runs as automatically, so if you're seeing it, something is going on 👀. warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly. very demure, very "we can't fix this one."

if you're invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. the assembler arguments must be separated from each other (and from the -Wa) by commas. commas!! not spaces!! 🎀 for example:

gcc -c -g -O -Wa,-alh,-L file.c

this passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain internal symbols in the symbol table). two for one, bestie 🙈.

usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (and if you're nosy — which, same — you can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler. forensic queen behavior 🔥.)

🌸 OPTIONS 🌸

@file — read command-line options from file. the options that get read are inserted right in place of the original @file option. if file doesn't exist, or can't be read, then the option is treated literally, and not removed. yep, it just sits there 💀.

options inside file are separated by whitespace. wanna include a whitespace character inside an option? surround the entire option in either single or double quotes. wanna include any character (including a backslash)? prefix the character you want to include with a backslash. and the file may itself contain additional @file options — those get processed recursively. it's giving inception 🌈.

-a[cdghilmns] — turn on listings, in any of a variety of ways:
- -ac — omit false conditionals
- -ad — omit debugging directives
- -ag — include general information, like as version and options passed
- -ah — include high-level source
- -al — include assembly
- -ali — include assembly with ginsn
- -am — include macro expansions
- -an — omit forms processing
- -as — include symbols
- =file — set the name of the listing file

you may combine these options; for example, use -aln for assembly listing without forms processing. the =file option, if used, must be the last one. by itself, -a defaults to -ahls. mix and match, it's a build-your-own-listing situation 💅.

--alternate — begin in alternate macro mode ✨.
--compress-debug-sections — compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. heads up: the resulting object file may not be compatible with older linkers and object file utilities 👀. also note, if compression would make a given section larger, then it is not compressed. no point, periodt.
--compress-debug-sections=none, --compress-debug-sections=zlib, --compress-debug-sections=zlib-gnu, --compress-debug-sections=zlib-gabi, --compress-debug-sections=zstd — these options control how DWARF debug sections get compressed.
- --compress-debug-sections=none is equivalent to --nocompress-debug-sections.
- --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to --compress-debug-sections.
- --compress-debug-sections=zlib-gnu compresses DWARF debug sections using the obsoleted zlib-gnu format. the debug sections are renamed to begin with .zdebug.
- --compress-debug-sections=zstd compresses DWARF debug sections using zstd.

note — if compression would actually make a section larger, then it is neither compressed nor renamed 🦋.

--nocompress-debug-sections — do not compress DWARF debug sections. this is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this. (x86/x86_64 really be doing the most 😭.)
-D — enable debugging in target specific backends, if supported. otherwise ignored. and even if it's ignored, this option is still accepted for script compatibility with calls to other assemblers. it's basically a polite little wave 👋.
--debug-prefix-map old=new — when assembling files in directory old, record debugging information describing them as in new instead. glow-up for file paths ✨.
--defsym sym=value — define the symbol sym to be value before assembling the input file. value must be an integer constant. as in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. the value of the symbol can be overridden inside a source file via the use of a .set pseudo-op. so it's a suggestion, not a promise, bestie 🫶.
--dump-config — displays how the assembler is configured and then exits. show us the receipts 📋.
--elf-stt-common=no, --elf-stt-common=yes — these options control whether the ELF assembler should generate common symbols with the "STT_COMMON" type. the default can be controlled by a configure option --enable-elf-stt-common.
--emit-local-absolute — emit even pre-defined (local) absolute symbols to the outgoing symbol table. note that this isn't the exact opposite of --strip-local-absolute. they're not nemeses, okay?? 💀
--emulation=name — if the assembler is configured to support multiple different target configurations, then this option can be used to select the desired form. pick your fighter 👑.
-f — "fast" — skip whitespace and comment preprocessing (assume source is compiler output). zoom zoom 🔥.
-g, --gen-debug — generate debugging information for each assembler source line using whichever debug format is preferred by the target. this currently means either STABS, ECOFF or DWARF2. when the debug format is DWARF then a .debug_info and .debug_line section is only emitted when the assembly file doesn't generate one itself.
--gstabs — generate stabs debugging information for each assembler line. this may help debugging assembler code, if the debugger can handle it. conditional support, we love that 🙈.
--gstabs+ — generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program 😭. this may help debugging assembler code. currently the only GNU extension is the location of the current working directory at assembling time. exclusive, highkey.
--gdwarf-2 — generate DWARF2 debugging information for each assembler line. this may help debugging assembler code, if the debugger can handle it. note — this option is only supported by some targets, not all of them. not everybody gets an invite 🎀.
--gdwarf-3 — this option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. note — enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis. it's giving "we'll see" ✨.
--gdwarf-4 — this option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. note — enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis.
--gdwarf-5 — this option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. note — enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis. five!! the numbers keep climbing 🦋.
--gdwarf-sections — instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. for example a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. if the code section is just called .text then the debug line section will still be called just .debug_line without any suffix. one for each, so organized 💅.
--gdwarf-cie-version=version — control which version of DWARF Common Information Entries (CIEs) are produced. when this flag is not specified the default is version 1, though some targets can modify this default. other possible values for version are 3 or 4.
--generate-missing-build-notes=yes, --generate-missing-build-notes=no — these options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. the default can be controlled by the --enable-generate-build-notes configure option.
--gsframe — create .sframe section from CFI directives. the explicit --gsframe=yes option behaves the same as --gsframe. generation can be suppressed with --gsframe=no. the default can be controlled by a configure option --enable-default-sframe. the current version of the emitted SFrame stack trace data is SFRAME_VERSION_3.
--gsframe — (yes, it's listed again, we don't make the rules 🌸)
--gsframe=no — suppress .sframe generation.
--gsframe=yes — same behavior as plain --gsframe.
--gsframe-3 — generate SFrame stack trace information as per Version 3 of the specification.
--hash-size N — ignored. supported for command line compatibility with other assemblers. it's just there for the vibes 🫶.
--help — print a summary of the command-line options and exit. your little cheat sheet 💖.
--target-help — prints you a lil summary of all the target-specific options and then dips out. ✨
--info — bestie, do NOT suppress the informational messages. let them speak. 💬
--no-info — okay actually, suppress the informational messages. shhh. 🙈
-I dir — adds the directory dir to the search list for .include directives, so as knows where to go looking. 🗂️
-J — don't warn about signed overflow. it's giving unbothered. 💅
-K — issue warnings when difference tables get altered for long displacements. 👀
-L, --keep-locals — keeps the internal symbols in the symbol table. these bad boys start with system-specific local label prefixes, typically .L for ELF systems, or L for traditional a.out systems. 🏷️
*--listing-lhs-width=number* — sets the max width, in words, of the output data column for an assembler listing to number. 📏
*--listing-lhs-width2=number* — same vibe, but for the continuation lines in an assembler listing: max width of the output data column, in words, is number. 📐
*--listing-rhs-width=number* — max width of an input source line as shown in a listing, measured in number bytes. 📊
*--listing-cont-lines=number* — max number of lines printed in a listing for a single line of input is set to number + 1. (yes, plus one, don't come for me.) 🔢
--multibyte-handling=allow, --multibyte-handling=warn, --multibyte-handling=warn-sym-only, --multibyte-handling=warn_sym_only — this one controls how the assembler handles multibyte characters in the input.
- the default (which you can bring back any time with the allow argument) is to just allow those characters, no complaints, no drama.
- warn makes the assembler generate a warning message whenever any multibyte character shows up.
- warn-sym-only only triggers a warning when a symbol gets defined with a name containing multibyte characters. (references to undefined symbols will NOT generate a warning — so don't stress about those.) ⚠️
--no-pad-sections — stops the assembler from padding the ends of output sections to that section's alignment. the default is to pad them, but lowkey that can waste space, and some targets have tight memory constraints so that space matters. 🧷
-o objfile — names the object-file output from as objfile. 💾
-R — folds the data section into the text section. one section, no notes. 🫂
--reduce-memory-overheads — ignored. it's only here for compatibility with tools that pass the same option to both the assembler and the linker. it's just vibing. 🧘
--reloc-section-sym=all, --reloc-section-sym=internal, --reloc-section-sym=none — controls whether relocations referencing local binding symbols get adjusted to use section symbols instead.
- all (the default) converts relocations against all eligible local binding symbols.
- internal converts only relocations against internal labels, a.k.a. symbols matching the .L prefix.
- none does zero conversions, we're not touching a thing. 🚫
--scfi=experimental — this option controls whether the assembler should synthesize CFI for hand-written input.
- if the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning.
- note that --scfi=experimental is not intended to be used for compiler-generated code, including inline assembly. this experimental support is work in progress, bestie. also, only the System V AMD64 ABI is supported. 🧪
- each input function in assembly must begin with the .type directive, and should ideally be closed off using a .size directive.
- when using SCFI, each .type directive prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry). which means with every .type directive, a previous block of instructions (if there is one) gets finalised as a distinct FDE. 🗃️
--sectname-subst — honors substitution sequences in section names. 🪄
--size-check=error, --size-check=warning — issues an error or a warning for an invalid ELF .size directive. pick your fighter. 🥊
--statistics — prints the maximum space (in bytes) and total time (in seconds) used by assembly. the receipts. 🧾
--strip-local-absolute — removes local absolute symbols from the outgoing symbol table. ✂️
-v, --verbose — prints the as version. hi bestie 👋
--version, -version — prints the as version and exits. it said what it said and left. 🚪
-W, --no-warn — suppresses warning messages. 🔇
--warn — don't suppress warning messages, and don't treat them as errors either. let them be heard. 🗣️
--fatal-warnings — treats warnings as errors. it's serious now. 💀
-w — ignored. 🫥
-x — ignored. 🫥
-Z — generates an object file even after errors. (bold. chaotic. iconic.) 🔥
-- | files ... — standard input, or source files to assemble. the actual main characters of the whole operation ngl. 📥

okay so the following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). 💜

-EB — specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. 🐘
-EL — specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. 🐭
-mabi=abi — specifies which ABI the source code uses. the recognized arguments are: "ilp32" and "lp64", which decide the generated object file is in ELF32 and ELF64 format respectively. the **default is "lp64". 🧬
-mcpu=processor[+extension...] — specifies the target processor. the assembler will issue an error message if you attempt to assemble an instruction that will not execute on the target processor. the following processor names are recognized: "cortex-a34", "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73", "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77", "cortex-a78", "cortex-a78ae", "cortex-a78c", "cortex-a510", "cortex-a520", "cortex-a710", "cortex-a720", "ares", "exynos-m1", "falkor", "neoverse-n1", "neoverse-n2", "neoverse-e1", "neoverse-v1", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1" "xgene2", "cortex-r82", "cortex-x1", "cortex-x2", "cortex-x3", and "cortex-x4". the special name "all" may be used to let the assembler accept instructions valid for any supported processor, including all optional extensions.
- on top of the basic instruction set, the assembler can be told to accept (or restrict) various extension mnemonics that extend the processor.
- if some implementations of a particular processor can have an extension, then those extensions are automatically enabled. so you will not normally have to specify any additional extensions. 🎁
-march=architecture[+extension...] — specifies the target architecture. again, the assembler will issue an error message if you attempt to assemble an instruction that will not execute on the target architecture. the following architecture names are recognized: "armv8-a", "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a", "armv8.6-a", "armv8.7-a", "armv8.8-a", "armv8.9-a", "armv8-r", "armv9-a", "armv9.1-a", "armv9.2-a", "armv9.3-a", "armv9.4-a" and "armv9.5-a".
- if both -mcpu and -march are specified, the assembler will use the setting for -mcpu. if neither is specified, the assembler defaults to -mcpu=all.
- the architecture option can be extended with the same instruction set extension options as the -mcpu option. unlike -mcpu, though, extensions are not always enabled by default. 🚨
-mbig-obj — on a PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. so many sections. 🐋
-mverbose-error — enables verbose error messages for AArch64 gas. this option is enabled by default. 📢
-mno-verbose-error — disables verbose error messages in AArch64 gas. 🤐
-menable-sysreg-checking — enables error messages that get issued if you attempt to assemble a system register access that will not execute on the target architecture. 🕵️

and these ones are available when as is configured for an Alpha processor. 🌈

-mcpu — specifies the target processor. if you attempt to assemble an instruction that will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. this option is equivalent to the .arch directive.
- the following processor names are recognized: 21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6", "ev67", "ev68". the special name "all" may be used to allow the assembler to accept instructions valid for any Alpha processor. (yes "ev5" is in the list twice. that's just how it is. 🫶)
- in order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. "ev4") do not. ⚡
-mdebug, -no-mdebug — enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. the default is to automatically enable .mdebug when the first stabs directive is seen. 🐛
-relax — forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. heads up though: this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. still, the option can be useful in specific applications. 😌
-replace, -noreplace — enables or disables the optimization of procedure calls, both at assemblage and at link time. these options are only available for VMS targets, and -replace is the default. see section 1.4.1 of the OpenVMS Linker Utility Manual. 📖
-g — used when the compiler generates debug information. when gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. otherwise this option has no effect. 🎀
-G size — a local common symbol larger than size gets placed in .bss, while smaller symbols get placed in .sbss. 📦
-F, -32addr — these options are ignored for backward compatibility. legacy behaviour, we respect it. 🫡

and finally (for this part, anyway), the following options are available when as is configured for an ARC processor. 🦋

*-mcpu=cpu* — selects the core processor variant. 🧠
-EB | -EL — select either big-endian (-EB) or little-endian (-EL) output. 🌍
-mcode-density — enables Code Density extension instructions. compact, efficient, slay. ✨

🌈 ARM vibes 💖

okay so when your as was built for the ARM processor family, bestie, these are your options:

-mcpu=processor[+extension...] — tells the assembler which ARM processor variant we're targeting ✨
-march=architecture[+extension...] — says which ARM architecture variant the target is using 💅
-mfpu=floating-point-format — picks which Floating Point architecture is the target 🎀
-mfloat-abi=abi — selects which floating point ABI is in use 🦋
-mthumb — turns on Thumb only instruction decoding 😤
-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant — choose which procedure calling convention is in use 🌸
-EB | -EL — pick big-endian (-EB) or little-endian (-EL) output, your call 👑
-mthumb-interwork — declares that the code was generated with interworking between Thumb and ARM code in mind 🫶
-mccs — turns on CodeComposer Studio assembly syntax compatibility mode, fancy ✨
-k — states that PIC code has been generated 💜

🖤 Blackfin bestie corner

and when as is built for the Blackfin processor family, these are the ones:

-mcpu=processor[-sirevision] — specifies the target processor. The optional sirevision is not used in the assembler — it's literally just here so GCC can easily pass down its own -mcpu= option, iykyk. The assembler will throw an error message if you try to assemble an instruction that won't execute on the target processor 😭. The recognized processor names are: bf504, bf506, bf512, bf514, bf516, bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf535 (not implemented yet 🙈), bf536, bf537, bf538, bf539, bf542, bf542m, bf544, bf544m, bf547, bf547m, bf548, bf548m, bf549, bf549m, bf561, and bf592.
-mfdpic — assemble for the FDPIC ABI 💅
-mno-fdpic / -mnopic — disables -mfdpic, periodt 💀

🌟 BPF (Linux kernel) squad

when as is configured for the Linux kernel BPF processor family, we get these:

✨ BPF Options ✨

-EB — this option specifies that the assembler should emit big-endian eBPF.
-EL — this option specifies that the assembler should emit little-endian eBPF.
-mdialect=dialect — specifies the assembly language dialect to recognize while assembling. The assembler supports normal and pseudoc.
-misa-spec=spec — specifies the version of the BPF instruction set to use when assembling. The BPF ISA versions supported are v1, v2, v3 and v4. The value xbpf can be specified to recognize extra instructions that are used by GCC for testing purposes. But beware — this is not valid BPF, bestie, no cap 🚨
-mno-relax — tells the assembler to not relax instructions 🧚

Heads up: if no endianness option is specified in the command line, the host endianness is used. See the info pages for documentation of the CRIS-specific options 💜

🦋 C-SKY cuties

when as is built for the C-SKY processor family, these are available:

-march=archname — assemble for architecture archname. The --help option lists valid values for archname ✨
-mcpu=cpuname — assemble for architecture cpuname. The --help option lists valid values for cpuname ✨
-EL / -mlittle-endian — generate little-endian output 🎀
-EB / -mbig-endian — generate big-endian output 🎀
-fpic / -pic — generate position-independent code 💅
-mljump / -mno-ljump — enable/disable transformation of the short branch instructions jbf, jbt, and jbr to jmpi. This option is for V2 processors only. It is ignored on CK801 and CK802 targets, which do not support the jmpi instruction, and is enabled by default for other processors 👑
-mbranch-stub / -mno-branch-stub — pass through R_CKCORE_PCREL_IMM26BY2 relocations for bsr instructions to the linker. This option is only available for bare-metal C-SKY V2 ELF targets, where it is enabled by default. It cannot be used in code that will be dynamically linked against shared libraries. 💀
-force2bsr / -mforce2bsr / -no-force2bsr / -mno-force2bsr — enable/disable transformation of jbsr instructions to bsr. This option is always enabled (and -mno-force2bsr is ignored) for CK801/CK802 targets. It is also always enabled when -mbranch-stub is in effect 😤
-jsri2bsr / -mjsri2bsr / -no-jsri2bsr / -mno-jsri2bsr — enable/disable transformation of jsri instructions to bsr. This option is enabled by default 🌸
-mnolrw / -mno-lrw — enable/disable transformation of lrw instructions into a movih/ori pair 🫶
-melrw / -mno-elrw — enable/disable extended lrw instructions. This option is enabled by default for CK800-series processors 💜
-mlaf / -mliterals-after-func / -mno-laf / -mno-literals-after-func — enable/disable placement of literal pools after each function ✨
-mlabr / -mliterals-after-br / -mno-labr / -mnoliterals-after-br — enable/disable placement of literal pools after unconditional branches. This option is enabled by default 🎀
-mistack / -mno-istack — enable/disable interrupt stack instructions. This option is enabled by default on CK801, CK802, and CK802 processors (yes, it literally says CK802 twice, that's what the page says, I don't make the rules 😭)

The following options explicitly enable certain optional instructions. These features are also enabled implicitly by using -mcpu= to specify a processor that supports it. So convenient, we love that for us 💅

-mhard-float — enable hard float instructions 🔥
-mmp — enable multiprocessor instructions 👑
-mcp — enable coprocessor instructions ⭐
-mcache — enable cache prefetch instruction 🌈
-msecurity — enable C-SKY security instructions 🛡️
-mtrust — enable C-SKY trust instructions 🫶
-mdsp — enable DSP instructions 🎧
-medsp — enable enhanced DSP instructions 🎧✨
-mvdsp — enable vector DSP instructions 🌟

🧚 Epiphany energy

when as is configured for an Epiphany processor:

-mepiphany — specifies that both 32 and 16 bit instructions are allowed. This is the default behavior 🎀
-mepiphany16 — restricts the permitted instructions to just the 16 bit set 😤

🌸 H8/300 hive

when as is configured for an H8/300 processor...

Options

The Renesas H8/300 version of as has one machine-dependent option:

-h-tick-hex — supports H'00 style hex constants in addition to 0x00 style 💅
-mach=name — sets the H8300 machine variant. The following machine names are recognised: h8300h, h8300hn, h8300s, h8300sn, h8300sx and h8300sxn ✨

💀 i386 icons

when as is configured for an i386 processor, here's the menu:

--32 | --x32 | --64 — select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively. These options are only available with the ELF object file format, and they require that the necessary BFD support has been included — on a 32-bit platform you have to add --enable-64-bit-bfd to configure to enable 64-bit usage and use x86-64 as target platform 👑
-n — by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment 💅
--divide — on SVR4-derived platforms, the character / is treated as a comment character, which means that it cannot be used in expressions. The --divide option turns / into a normal character. This does not disable / at the beginning of a line starting a comment, and it does not affect using # for starting a comment 🎀
-march=CPU[+EXTENSION...] — specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor 😭. The following processor names are recognized: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, znver5, znver6, btver1, btver2, generic32 and generic64 🔥

Alsooo — plot twist — the basic instruction set isn't the whole menu. You can tell the assembler to accept a bunch of extension mnemonics too. Like, -march=i686+sse4+vmx is you taking i686 and going "yeah and also sse4 and vmx, thank you". 🫶

And the extensions currently supported are... okay bestie, sit down, this is a whole roster:

8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4
avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset
avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, avx512_bmm, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb
avx10.1, avx10.1/512, avx10.1/256, avx10.1/128, user_msr, msr_imm, apx_f, apx_nci, apx_ndd, apx_nf, apx_nci_ndd_nf, avx10.2, avx10.2/512, avx10.2/256, avx10.2/128, movrs
amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8, amx_movrs, amx_avx512, amx_tile
vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5
snp, invlpgb, tlbsync, rmpquery, rmpread, svme, gmism2, gmiccs, padlockrng2, padlockphe2, padlockxmodx and padlock

That's the whole squad. 💅 And here's the little trick: you can slap a no in front of any of these extension mnemonics to revoke that functionality — and anything that depends on it, bestie. Gone. ✨

Also note (another note, I know, iconic): the suffixes allowed on -march=avx10.<N> enforce a vector length restriction. So even though these look like the most "enabling" options ever, using those suffixes will actually disable all insns with wider vector or mask register operands. The way that "yes" means "no" here is giving villain era. 💀

And when the .arch directive is used together with -march, the .arch directive takes precedent. Periodt, .arch wins.

-mtune=CPU — tells the assembler which processor to optimize for. When you use it alongside -march, only instructions of the processor you named in -march get generated.

The valid CPU values are literally identical to the processor list of -march=CPU. Same list, no notes.

-moperand-check=none, -moperand-check=warning, -moperand-check=error — these control whether the assembler checks certain instruction operands or operand combos. Think of an instruction where the operand size can't be inferred from its operands and also wasn't specified by way of an instruction suffix — that's the vibe under inspection here.
- -moperand-check=none → the assembler does not do these checks.
- -moperand-check=warning → issues a warning when the checks fail. This one is the default.
- -moperand-check=error → issues an error when the checks fail.
-msse2avx — says the assembler should encode SSE instructions with VEX prefix, which requires AVX to be available. SSE instructions using extended GPRs get encoded with EVEX prefix, which requires AVX512 or AVX10 to be available. ✨
-muse-unaligned-vector-move — says the assembler should encode aligned vector move as unaligned vector move. Yes bestie, it does what it says. 🦋
-msse-check=none, -msse-check=warning, -msse-check=error — these control whether the assembler checks SSE instructions.
- -msse-check=none → doesn't check SSE instructions at all. This is the default.
- -msse-check=warning → issues a warning for any SSE instruction.
- -msse-check=error → issues an error for any SSE instruction.
-mavxscalar=128, -mavxscalar=256 — these control how the assembler encodes scalar AVX instructions.
- -mavxscalar=128 → encodes scalar AVX instructions with 128bit vector length. Default, bestie.
- -mavxscalar=256 → encodes scalar AVX instructions with 256bit vector length.

WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models. 🚨 I'm serious, this is not the moment for main character energy.

-mvexwig=0, -mvexwig=1 — these control how the assembler encodes VEX.W-ignored (WIG) VEX instructions.
- -mvexwig=0 → encodes WIG VEX instructions with vex.w = 0. That's the default.
- -mvexwig=1 → encodes WIG EVEX instructions with vex.w = 1.

WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models. 🙈

-mevexlig=128, -mevexlig=256, -mevexlig=512 — these control how the assembler encodes length-ignored (LIG) EVEX instructions.
- -mevexlig=128 → encodes LIG EVEX instructions with 128bit vector length. The default, obviously.
- -mevexlig=256 → encodes them with 256bit vector length.
- -mevexlig=512 → encodes them with 512bit vector length. Respectively. 💅
-mevexwig=0, -mevexwig=1 — these control how the assembler encodes w-ignored (WIG) EVEX instructions.
- -mevexwig=0 → encodes WIG EVEX instructions with evex.w = 0. Default vibe.
- -mevexwig=1 → encodes WIG EVEX instructions with evex.w = 1.
-mmnemonic=att, -mmnemonic=intel — specifies the instruction mnemonic for matching instructions. The .att_mnemonic and .intel_mnemonic directives will take precedent. 👑
-msyntax=att, -msyntax=intel — specifies instruction syntax when processing instructions. The .att_syntax and .intel_syntax directives will take precedent. Again: directives win, no cap.
-mnaked-reg — specifies that registers don't require a % prefix. Just like the above two, the .att_syntax and .intel_syntax directives will take precedent. 🎀
-madd-bnd-prefix — forces the assembler to add BND prefix to all branches, even if that prefix wasn't explicitly specified in the source code. Bold move. We love a commitment.
-mno-shared — on ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The -mshared option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted — the resulting code is slightly bigger. This option only affects the handling of branch instructions. 🌸
-mbig-obj — on PE/COFF target this forces the use of big object file format, which allows more than 32768 sections. Big. Object. Energy. 💖
-momit-lock-prefix=no, -momit-lock-prefix=yes — these control how the assembler encodes the lock prefix. This option is intended as a workaround for processors that fail on lock prefix.
- -momit-lock-prefix=yes → omits all lock prefixes.
- -momit-lock-prefix=no → encodes lock prefix as usual. Default.

🚨 This option can only be safely used with single-core, single-thread computers. Like, that's the whole deal. Single. Core. Single. Thread.

-mfence-as-lock-add=no, -mfence-as-lock-add=yes — these control how the assembler encodes lfence, mfence and sfence.
- -mfence-as-lock-add=yes → encodes lfence, mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock addl $0x0, (%esp) in 32-bit mode.
- -mfence-as-lock-add=no → encodes lfence, mfence and sfence as usual. Default, bestie.
-mrelax-relocations=no, -mrelax-relocations=yes — these control whether the assembler should generate relax relocations, R_386_GOT32X in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX in 64-bit mode.
- -mrelax-relocations=yes → generates relax relocations.
- -mrelax-relocations=no → does not generate relax relocations.
-mtls-check=no, -mtls-check=yes — these control whether the assembler checks tls relocation.
- -mtls-check=yes → checks tls relocation.
- -mtls-check=no → does not check tls relocation.

The default can be controlled by a configure option --enable-x86-tls-check. ✨

-malign-branch-boundary=NUM — controls how the assembler should align branches with segment prefixes or NOP. NUM must be a power of 2. It should be 0 or no less than 16. Branches will be aligned within NUM byte boundary. -malign-branch-boundary=0, which is the default, doesn't align branches. Math class but make it assembly. 🧚
-malign-branch=TYPE[+TYPE...] — specifies the types of branches to align. TYPE is a combination of:
- jcc, which aligns conditional jumps
- fused, which aligns fused conditional jumps
- jmp, which aligns unconditional jumps
- call, which aligns calls
- ret, which aligns rets
- indirect, which aligns indirect jumps and calls

The default is -malign-branch=jcc+fused+jmp. 🫶

-malign-branch-prefix-size=NUM — specifies the maximum number of prefixes on an instruction to align branches. NUM should be between 0 and 5. The default NUM is 5.
-mbranches-within-32B-boundaries — aligns conditional jumps, fused conditional jumps and unconditional jumps within 32 byte boundary with up to 5 segment prefixes on an instruction. It's equivalent to:

-malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5

The default doesn't align branches. (Noted twice because it matters twice, okay? 💅)

-mlfence-after-load=no, -mlfence-after-load=yes — these control whether the assembler should generate lfence after load instructions.
- -mlfence-after-load=yes → generates lfence.
- -mlfence-after-load=no → doesn't generate lfence. This is the default. 🙈
-mlfence-before-indirect-branch=all — generates lfence before indirect near branch via register, and throws a warning before indirect near branch via memory. It also implicitly sets -mlfence-before-ret=shl when there's no explicit -mlfence-before-ret= hanging around.
-mlfence-before-indirect-branch=register — generates lfence before indirect near branch via register. that's it, that's the girl.
-mlfence-before-indirect-branch=memory — issues a warning before indirect near branch via memory.
-mlfence-before-indirect-branch=none — generates no lfence and issues no warning. this is the default, bestie.

heads up tho 💀: lfence will not be generated before indirect near branch via register when -mlfence-after-load=yes is in play, because in that case lfence gets generated after loading the branch target register. it's giving "we already handled it downstream."

-mlfence-before-ret=none — generates no lfence. default behaviour, no notes.
-mlfence-before-ret=shl — generates a shl instruction with lfence. (same energy as yes, see below 🫶)
-mlfence-before-ret=or — generates an or instruction with lfence.
-mlfence-before-ret=yes — same as shl: generates a shl instruction with lfence.
-mlfence-before-ret=not — generates a not instruction with lfence.

-mx86-used-note=no
-mx86-used-note=yes

these two control whether the assembler generates the GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes ✨. the default is set by the --enable-x86-used-note configure option, so it's a build-time vibe check.

-mevexrcig=rne — encodes the RC bits of an SAE-only EVEX instruction with 00. this is the default 💅
-mevexrcig=rd — encodes SAE-only EVEX instructions with 01 RC bits.
-mevexrcig=ru — encodes SAE-only EVEX instructions with 10 RC bits.
-mevexrcig=rz — encodes SAE-only EVEX instructions with 11 RC bits.

(yes bestie, rd, ru and rz map to 01, 10 and 11 respectively — the girlies go in order.)

-mamd64, -mintel64 — tells the assembler to accept only AMD64 or Intel64 ISA when it's in 64-bit mode. the default is way more chill: accept the common, Intel64 only and AMD64 ISAs 🌈

-O0 | -O | -O1 | -O2 | -Os — optimize instruction encoding so the instruction size gets smaller. let's break it down because this one's a whole saga:

-O and -O1 encode:

64-bit register load instructions with 64-bit immediate → as 32-bit register load instructions with 31-bit or 32-bits immediates
64-bit register clearing instructions → as 32-bit register clearing instructions
256-bit/512-bit VEX/EVEX vector register clearing instructions → as 128-bit VEX vector register clearing instructions
128-bit/256-bit EVEX vector register load/store instructions → as VEX vector register load/store instructions
128-bit/256-bit EVEX packed integer logical instructions → as 128-bit/256-bit VEX packed integer logical

-O2 is -O1 plus it encodes 256-bit/512-bit EVEX vector register clearing instructions as 128-bit EVEX vector register clearing instructions ✨. And in 64-bit mode, VEX encoded instructions with commutative source operands will also have their source operands swapped if that lets it use the 2-byte VEX prefix form instead of the 3-byte one. Certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST. iconic.

-Os is -O2 plus it encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. maximal optimisation, minimal bytes.

-O0 turns off this optimization. bye 👋

🦋 the following options are available when `as` is configured for the Ubicom IP2K series

-mip2022ext — says the extended IP2022 instructions are allowed.
-mip2022 — restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. back to basics bestie.

🍓 the following options are available when `as` is configured for the Renesas M32C and M16C processors

-m32c — assemble M32C instructions.
-m16c — assemble M16C instructions (the default).
-relax — enable support for link-time relaxations.
-h-tick-hex — support H'00 style hex constants in addition to 0x00 style.

💜 the following options are available when `as` is configured for the Renesas M32R (formerly Mitsubishi M32R) series

--m32rx — specify which processor in the M32R family is the target. the default is normally the M32R, but this option changes it to the M32RX.
--warn-explicit-parallel-conflicts or --Wp — produce warning messages when questionable parallel constructs are encountered 👀
--no-warn-explicit-parallel-conflicts or --Wnp — do not produce warning messages when questionable parallel constructs are encountered. ignorance is bliss, periodt.

🌸 the following options are available when `as` is configured for the Motorola 68000 series

-l — shorten references to undefined symbols, to one word instead of two.
-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 — specify what processor in the 68000 family is the target. the default is normally the 68020, but this can be changed at configuration time.
-m68881 | -m68882 | -mno-68881 | -mno-68882 — the target machine does (or does not) have a floating-point coprocessor. the default is to assume a coprocessor for 68020, 68030, and cpu32. although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor. ✨ combo move
-m68851 | -mno-68851 — the target machine does (or does not) have a memory-management unit coprocessor. the default is to assume an MMU for 68020 and up.

for details about the PDP-11 machine dependent features options, see PDP-11-Options 👑

-mpic | -mno-pic — generate position-independent (or position-dependent) code. the default is -mpic.
-mall, -mall-extensions — enable all instruction set extensions. this is the default.
-mno-extensions — disable all instruction set extensions. not like other girls.
-mextension | -mno-extension — enable (or disable) a particular instruction set extension.
-mcpu — enable the instruction set extensions supported by a particular CPU, and disable all other extensions.
-mmachine — enable the instruction set extensions supported by a particular machine model, and disable all other extensions.

💖 the following options are available when `as` is configured for a picoJava processor

-mb — generate "big endian" format output.
-ml — generate "little endian" format output.

🎀 the following options are available when `as` is configured for a PRU processor

-mlink-relax — assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LD would shorten the LDI32 instruction to a single LDI. In such case "as" will output DIFF relocations for diff expressions.
-mno-link-relax — assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted. no relocation, no problem.
-mno-warn-regname-label — do not warn if a label name matches a register name. usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off.
*-mcore-revision=revision* — this option specifies the PRU core revision to assemble for. The following revisions are recognized: "V1", "V2", "V3" and "V4". The assembler defaults to "V3".

⭐ the following options are available when `as` is configured for a MIPS processor

-G num — this option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
-EB — generate "big endian" format output.
-EL — generate "little endian" format output.
-mips1, -mips2, -mips3, -mips4, -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, -mips64r6 — generate code for a particular MIPS Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. so many releases bestie 😭
*-march=cpu* — generate code for a particular MIPS CPU.
*-mtune=cpu* — schedule and tune for a particular MIPS CPU.
-mfix7000 | -mno-fix7000 — cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
-mfix-rm7000 | -mno-fix-rm7000 — cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.
-mfix-r5900 | -mno-fix-r5900 — do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a "nop" instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. 💀 hardware bug arc
-mdebug | -no-mdebug — cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections.
-mpdr | -mno-pdr — control generation of .pdr sections.
-mgp32, -mfp32 — the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.
-mgp64, -mfp64 — bestie, register sizes are normally just vibes-inferred from the ISA and the ABI, right? But these two force a specific group of registers to be treated as 64 bits wide, at all times, no takebacks. -mgp64 runs the general-purpose registers, -mfp64 runs the floating-point ones. Two separate reigns, two separate queens 👑.
-mfpxx — same deal, register sizes usually get inferred from the ISA and ABI, but if you use this flag together with -mabi=32 it unlocks an ABI variant that will operate correctly with floating-point registers that are 32 bits wide or 64 bits wide. Flexible queen behavior ✨.
-modd-spreg, -mno-odd-spreg — enables using floating-point operations on odd-numbered single-precision registers, when the ISA supports it. Heads up: -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg.
-mips16, -no-mips16 — generates code for the MIPS 16 processor. Equivalent to dropping ".module mips16" at the very start of the assembly file. -no-mips16 turns that whole thing back off.
-mmips16e2, -mno-mips16e2 — enables MIPS16e2 instructions while you're in MIPS16 mode. Equivalent to putting ".module mips16e2" at the start of the assembly file. -mno-mips16e2 flips it off.
-mmicromips, -mno-micromips — generates code for the microMIPS processor. Equivalent to putting ".module micromips" at the start of the assembly file. -mno-micromips turns it off — and that one is equivalent to putting ".module nomicromips" at the start of the assembly file.
-msmartmips, -mno-smartmips — enables the SmartMIPS extension to the MIPS32 instruction set. Equivalent to putting ".module smartmips" at the start of the assembly file. -mno-smartmips turns it off.
-mips3d, -no-mips3d — generates code for the MIPS-3D Application Specific Extension, which tells the assembler to accept MIPS-3D instructions. -no-mips3d turns it off.
-mdmx, -no-mdmx — generates code for the MDMX Application Specific Extension, telling the assembler to accept MDMX instructions. -no-mdmx turns it off.
-mdsp, -mno-dsp — generates code for the DSP Release 1 Application Specific Extension, telling the assembler to accept DSP Release 1 instructions. -mno-dsp turns it off.
-mdspr2, -mno-dspr2 — generates code for the DSP Release 2 Application Specific Extension. This one implies -mdsp, and it tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns it off.
-mdspr3, -mno-dspr3 — generates code for the DSP Release 3 Application Specific Extension. This one implies both -mdsp and -mdspr2, and it tells the assembler to accept DSP Release 3 instructions. -mno-dspr3 turns it off.
-mmsa, -mno-msa — generates code for the MIPS SIMD Architecture Extension, telling the assembler to accept MSA instructions. -mno-msa turns it off.
-mxpa, -mno-xpa — generates code for the MIPS eXtended Physical Address (XPA) Extension, telling the assembler to accept XPA instructions. -mno-xpa turns it off.
-mmt, -mno-mt — generates code for the MT Application Specific Extension, telling the assembler to accept MT instructions. -mno-mt turns it off.
-mmcu, -mno-mcu — generates code for the MCU Application Specific Extension, telling the assembler to accept MCU instructions. -mno-mcu turns it off.
-mcrc, -mno-crc — generates code for the MIPS cyclic redundancy check (CRC) Application Specific Extension, telling the assembler to accept CRC instructions. -mno-crc turns it off.
-mginv, -mno-ginv — generates code for the Global INValidate (GINV) Application Specific Extension, telling the assembler to accept GINV instructions. -mno-ginv turns it off.
-mloongson-mmi, -mno-loongson-mmi — generates code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension, telling the assembler to accept MMI instructions. -mno-loongson-mmi turns it off.
-mloongson-cam, -mno-loongson-cam — generates code for the Loongson Content Address Memory (CAM) instructions, telling the assembler to accept Loongson CAM instructions. -mno-loongson-cam turns it off.
-mloongson-ext, -mno-loongson-ext — generates code for the Loongson EXTensions (EXT) instructions, telling the assembler to accept Loongson EXT instructions. -mno-loongson-ext turns it off.
-mloongson-ext2, -mno-loongson-ext2 — generates code for the Loongson EXTensions R2 (EXT2) instructions. This one implies -mloongson-ext, and it tells the assembler to accept Loongson EXT2 instructions. -mno-loongson-ext2 turns it off.
-minsn32, -mno-insn32 — only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions, and it's equivalent to putting ".set insn32" at the start of the assembly file. -mno-insn32 turns it off, which is equivalent to putting ".set noinsn32" at the start of the assembly file. By default -mno-insn32 is selected, so literally every instruction is allowed to come to the party 💅.
--construct-floats, --no-construct-floats — --no-construct-floats disables building double-width floating point constants by loading the two halves of the value into the two single-width floating point registers that together make up the double-width register. By default --construct-floats is selected, so these floating point constants can be constructed.
--relax-branch, --no-relax-branch — --relax-branch enables the relaxation of out-of-range branches. By default --no-relax-branch is selected, which means any out-of-range branch produces an error. No chilling, just errning 😭.
-mignore-branch-isa, -mno-ignore-branch-isa — ignore branch checks for invalid transitions between ISA modes. The semantics of branches genuinely do not provide for an ISA mode switch, so in most cases the ISA mode a branch was encoded for has to be the same as the ISA mode of the branch's target label. That's why GAS has checks implemented that verify, at branch assembly time, that the two ISA modes match. -mignore-branch-isa disables those checks. By default -mno-ignore-branch-isa is selected, causing any invalid branch that needs a transition between ISA modes to produce an error.
-mnan=encoding — pick between the IEEE 754-2008 NaN encoding format (-mnan=2008) and the legacy one (-mnan=legacy). The legacy one is the default, bestie. That's just how it is.
--emulation=name — ok so this one used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. But MIPS ECOFF support was removed in GAS 2.24, so this option is kind of serving no purpose now 💀. It's retained purely for backwards compatibility.

The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively — but -EL and -EB are now the preferred options instead. Upgrade your habits, bestie.

-nocpp — as ignores this option completely. It's accepted just for compatibility with the native tools. Ghost option, honestly 👻.
--trap, --no-trap, --break, --no-break — these control how to deal with multiplication overflow and division by zero. --trap or --no-break (they're synonyms) take a trap exception — and psa, those only work for Instruction Set Architecture level 2 and higher. --break or --no-trap (also synonyms, and the default) take a break exception.
-n — when this one's used, as will issue a warning every single time it generates a nop instruction from a macro. Every. Single. Time. Very "are you sure about that" energy 🫶.

The following options are available when as is configured for a LoongArch processor.

-fpic, -fPIC — generate position-independent code.
-fno-pic — don't generate position-independent code (default).

The following options are available when as is configured for a Meta processor.

"-mcpu=metac11" — generate code for Meta 1.1.
"-mcpu=metac12" — generate code for Meta 1.2.
"-mcpu=metac21" — generate code for Meta 2.1.
"-mfpu=metac21" — allow code to use the FPU hardware of Meta 2.1.

See the info pages for documentation of the MMIX-specific options. Not my department, bestie, go read those 📖.

The following options are available when as is configured for a NDS32 processor.

"-O1" — optimize for performance.
"-Os" — optimize for space.
"-EL" — produce little endian data output.
"-EB" — produce little endian data output.
"-mpic" — generate PIC.
"-mno-fp-as-gp-relax" — suppress fp-as-gp relaxation for this file.
"-mb2bb-relax" — back-to-back branch optimization.
"-mno-all-relax" — suppress all relaxation for this file.
"-march=<arch name>" — assemble for architecture <arch name>, which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.
"-mbaseline=<baseline>" — assemble for baseline <baseline>, which could be v2, v3, v3m.
"-mfpu-freg=FREG" — specify a FPU configuration. The lineup is:

"0      8 SP /  4 DP registers"
"1     16 SP /  8 DP registers"
"2     32 SP / 16 DP registers"
"3     32 SP / 32 DP registers"

"-mabi=abi" — specify an abi version, <abi> could be v1, v2, v2fp, v2fpp.
"-m[no-]mac" — enable/disable Multiply instructions support.
"-m[no-]div" — enable/disable Divide instructions support.
"-m[no-]16bit-ext" — enable/disable 16-bit extension.
"-m[no-]dx-regs" — enable/disable d0/d1 registers.
"-m[no-]perf-ext" — enable/disable Performance extension.
"-m[no-]perf2-ext" — enable/disable Performance extension 2.
"-m[no-]string-ext" — enable/disable String extension.
"-m[no-]reduced-regs" — enable/disable Reduced Register configuration (GPR16) option.
"-m[no-]audio-isa-ext" — enable/disable AUDIO ISA extension.
"-m[no-]fpu-sp-ext" — enable/disable FPU SP extension.
"-m[no-]fpu-dp-ext" — enable/disable FPU DP extension.
"-m[no-]fpu-fma" — enable/disable FPU fused-multiply-add instructions.
"-mall-ext" — turn on all extensions and instructions support. Everything. All of it. Greedy behavior, we love it 💖.

The following options are available when as is configured for a PowerPC processor.

-a32 — generate ELF32 or XCOFF32.
-a64 — generate ELF64 or XCOFF64.
-K PIC — sets EF_PPC_RELOCATABLE_LIB in the ELF flags. tiny flag, big moves 💅
-mpwrx, -mpwr2 — generates code for POWER/2 (RIOS2). rios2 girlies rise 🫶
-mpwr — generates code for POWER (RIOS1). the original flavor, no cap 🌸
-m601 — generates code for PowerPC 601.
-mppc, -mppc32, -m603, -m604 — generates code for PowerPC 603/604.
-m403, -m405 — generates code for PowerPC 403/405.
-m440 — generates code for PowerPC 440. it's giving BookE, plus some 405 instructions ✨
-m464 — generates code for PowerPC 464.
-m476 — generates code for PowerPC 476.
-m7400, -m7410, -m7450, -m7455 — generates code for PowerPC 7400/7410/7450/7455.
-m750cl, -mgekko, -mbroadway — generates code for PowerPC 750CL/Gekko/Broadway. yes, Gekko. GameCube besties, I see you 🎀
-m821, -m850, -m860 — generates code for PowerPC 821/850/860.
-mppc64, -m620 — generates code for PowerPC 620/625/630.
-me200z2, -me200z4 — generates code for the e200 variants — e200z2 with LSP, e200z4 with SPE. two sisters, two vibes 😭
-me300 — generates code for the PowerPC e300 family.
-me500, -me500x2 — generates code for the Motorola e500 core complex.
-me500mc — generates code for the Freescale e500mc core complex.
-me500mc64 — generates code for the Freescale e500mc64 core complex.
-me5500 — generates code for the Freescale e5500 core complex.
-me6500 — generates code for the Freescale e6500 core complex.
-mlsp — enables LSP instructions. heads up tho: this disables SPE and SPE2. it's giving "you can't sit with both tables" 😤
-mspe — generates code for Motorola SPE instructions. and yes, it disables LSP.
-mspe2 — generates code for Freescale SPE2 instructions. also disables LSP. the LSP erasure is real 💀
-mtitan — generates code for the AppliedMicro Titan core complex.
-mppc64bridge — generates code for PowerPC 64, bridge insns included.
-mbooke — generates code for 32-bit BookE.
-ma2 — generates code for the A2 architecture.
-maltivec — generates code for processors with AltiVec instructions.
-mvle — generates code for Freescale PowerPC VLE instructions.
-mvsx — generates code for processors with Vector-Scalar (VSX) instructions.
-mhtm — generates code for processors with Hardware Transactional Memory instructions.
-mpower4, -mpwr4 — generates code for the Power4 architecture.
-mpower5, -mpwr5, -mpwr5x — generates code for the Power5 architecture.
-mpower6, -mpwr6 — generates code for the Power6 architecture.
-mpower7, -mpwr7 — generates code for the Power7 architecture.
-mpower8, -mpwr8 — generates code for the Power8 architecture.
-mpower9, -mpwr9 — generates code for the Power9 architecture.
-mpower10, -mpwr10 — generates code for the Power10 architecture.
-mpower11, -mpwr11 — generates code for the Power11 architecture. yes we're at 11. the pipeline never sleeps 👑
-mfuture — generates code for the 'future' architecture. literally assembling for tomorrow, main character energy fr fr 🔮
-mcell, -mcell — generates code for the Cell Broadband Engine architecture. (it's listed twice in the original, so it's listed twice here too. some things are just too iconic to say once 🎀)
-mcom — generates code for Power/PowerPC common instructions.
-many — generates code for any architecture (PWR/PWRX/PPC). the "why choose" option 💅
-mregnames — allows symbolic names for registers.
-mno-regnames — does not allow symbolic names for registers.
-mrelocatable — support for GCC's -mrelocatable option.
-mrelocatable-lib — support for GCC's -mrelocatable-lib option.
-memb — sets the PPC_EMB bit in the ELF flags.
-mlittle, -mlittle-endian, -le — generates code for a little endian machine.
-mbig, -mbig-endian, -be — generates code for a big endian machine.
-nops=count — if an alignment directive inserts more than count nops, it puts a branch at the beginning to skip execution of the nops. skipping the filler, we love efficiency 🦋

🌈 RISC-V era

The following options are available when as is configured for a RISC-V processor.

-fpic, -fPIC — generate position-independent code.
-fno-pic — don't generate position-independent code. this one's the default.
*-march=ISA*|Profiles|Profiles_ISA** — selects the base isa, as specified by *ISA* or *Profiles* or *Profies_ISA*. for example -march=rv32ima -march=RVI20U64 -march=RVI20U64_d. and if this option and the architecture attributes aren't set, then the assembler will check the default configure setting --with-arch=ISA`.
-misa-spec=ISAspec — selects the default isa spec version. if the version of ISA isn't set by -march, then the assembler helps to set the version according to the default chosen spec. if this option isn't set, then the assembler will check the default configure setting --with-isa-spec=ISAspec.
-mpriv-spec=PRIVspec — selects the privileged spec version. we can decide whether the CSR is valid or not according to the chosen spec. if this option and the privilege attributes aren't set, then the assembler will check the default configure setting --with-priv-spec=PRIVspec.
-mabi=ABI — selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or "e" to indicate the soft-float calling convention ("e" indicates a soft-float RVE ABI). so many letters, so much power ✨
-mrelax — takes advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default) — less work, same result, slay 🫶
-mno-relax — don't do linker relaxations.
-march-attr — generates the default contents for the riscv elf attribute section if the .attribute directives are not set. this section is used to record the information that a linker or runtime loader needs to check compatibility. that info includes the ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of the privileged specification.
-mno-arch-attr — don't generate the default riscv elf attribute section if the .attribute directives are not set.
-mcsr-check — enables CSR checking for the ISA-dependent CRS and the read-only CSR. the ISA-dependent CSR are only valid when the specific ISA is set. and the read-only CSR can not be written by the CSR instructions. read-only means read-only bestie, respect the boundary 😤
-mno-csr-check — don't do CSR checking.
-mlittle-endian — generates code for a little endian machine.
-mbig-endian — generates code for a big endian machine.

See the info pages for documentation of the RX-specific options. (not here, not today — go read the info pages 💅)

🧚 s390 family

The following options are available when as is configured for the s390 processor family.

-m31, -m64 — selects the word size, either 31/32 bits or 64 bits.
-mesa, -mzarch — selects the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).
-march=processor — specifies which s390 processor variant is the target: g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or z17 (or arch15). the whole family tree, in order 🌸
-mregnames, -mno-regnames — allow or disallow symbolic names for registers. pick a lane 🎀
-mwarn-areg-zero — warns whenever the operand for a base or index register has been specified but evaluates to zero. "not me passing a zero, i'm crying" 😭
-mwarn-regtype-mismatch=strict, -mwarn-regtype-mismatch=relaxed, -mwarn-regtype-mismatch=no, -mno-warn-regtype-mismatch — controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type.

The default (which can be restored by using the relaxed argument) is to perform relaxed register name type checks, which allow floating point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands, and vector register (VR) names %v0 to %v15 to be specified as argument to floating point register (FPR) operands. this is acceptable because the FPR are embedded into the lower half of the VR. nested. embedded. obsessed 💜

Using the strict argument, strict register name type checks are performed.

The no argument, which is equivalent to -mno-warn-regtype-mismatch, disables any register name type checks. no thoughts, no checks ✨

🍓 TMS320C6000 moment

The following options are available when as is configured for a TMS320C6000 processor.

-march=arch — enables (only) instructions from architecture arch. by default, all instructions are permitted.

The following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x".

-mdsbt, -mno-dsbt — the -mdsbt option causes the assembler to generate the "Tag_ABI_DSBT" attribute with a value of 1, indicating that the code is using DSBT addressing. the -mno-dsbt option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. the linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. so like, don't mix them, the linker will absolutely call it out 😭
-mpid=no, -mpid=near, -mpid=far — the -mpid= option causes the assembler to generate the "Tag_ABI_PID" attribute with a value indicating the form of data addressing used by the code. -mpid=no, the default, indicates position-dependent data addressing; -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing; and -mpid=far indicates position-independent addressing with GOT accesses using far DP addressing. the linker will emit a warning if objects built with different settings of this option are linked together. yes, another "don't mix" ✋
-mpic, -mno-pic — the -mpic option causes the assembler to generate the "Tag_ABI_PIC" attribute with a value of 1, indicating that the code is using position-independent code addressing. the "-mno-pic" option, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. the linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together. third time's the charm, keep your object types consistent bestie 💅
-mbig-endian, -mlittle-endian — generates code for the specified endianness. the default is little-endian.

🦋 TILE-Gx

The following options are available when as is configured for a TILE-Gx processor.

-m32 | -m64 — selects the word size, either 32 bits or 64 bits.
-EB | -EL — selects the endianness, either big-endian (-EB) or little-endian (-EL).

🌟 Visium

The following option is available when as is configured for a Visium processor.

-mtune=arch — this option specifies the target architecture. if an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. it WILL find out 🌈

The following names are recognized: "mcm24" "mcm" "gr5" "gr6"

The following options are available when as is configured for an Xtensa processor.

--text-section-literals, --no-text-section-literals — okay so this is the literal pool treatment dial 🎛️. Default is --no-text-section-literals, which drops the literals into separate sections in the output file — the whole point being that your literal pool can then live in a data RAM/ROM. Switch on --text-section-literals and the literals get interspersed in the text section instead, so they sit as close as possible to the references that use them. Why would you want that? Because for big assembly files the literals would otherwise be out of range of the L32R instructions in the text section, and that's awkward bestie 💀. Literals get grouped into pools following .literal_position directives, or preceding ENTRY instructions. Heads up tho: these options only touch literals referenced via PC-relative L32R instructions — literals for absolute mode L32R instructions are handled separately, no cap.
--auto-litpools, --no-auto-litpools — same literal pool treatment energy, different flavour 🦋. Default is --no-auto-litpools, which (in the absence of --text-section-literals) puts literals in separate sections in the output file, so the literal pool can be parked in a data RAM/ROM. With --auto-litpools the literals get interspersed in the text section so they stay as close as possible to their references, and you don't need explicit .literal_position directives anymore. This one matters for very large functions, where a single literal pool at the beginning of the function might not be reachable by L32R instructions at the end. Again: only PC-relative L32R literals; absolute mode L32R literals are handled separately. And when you use it together with --text-section-literals, --auto-litpools takes precedence. Periodt.
--absolute-literals, --no-absolute-literals — tells the assembler whether L32R instructions use absolute or PC-relative addressing. If your processor includes the absolute addressing option, the default is to use absolute L32R relocations. If it doesn't, then literally only the PC-relative L32R relocations can be used. That's it, that's the whole vibe check ✨.
--target-align, --no-target-align — turn automatic alignment on or off, which reduces branch penalties at some expense in code size. This optimization is enabled by default, it's giving free wins ✨. Little note tho: the assembler will always align instructions like LOOP that have fixed alignment requirements, no matter what you say.
--longcalls, --no-longcalls — enable or disable transformation of call instructions so calls can reach across a greater range of addresses. Use this when call targets can potentially be out of range. Fair warning: it may degrade both code size and performance 😭, but the linker can generally optimize away the unnecessary overhead when a call ends up within range, so it's usually fine. The default is --no-longcalls.
--transform, --no-transform — enable or disable all assembler transformations of Xtensa instructions, relaxation and optimization included. Default is --transform. --no-transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source — and know that using --no-transform causes out of range instruction operands to be errors. Not a vibe, use sparingly 🫶.
--rename-section oldname=newname — renames the oldname section to newname. You can use this option multiple times to rename multiple sections. Rename era 💅.
--trampolines, --no-trampolines — enable or disable transformation of jump instructions to allow jumps across a greater range of addresses. Reach for this when jump targets can potentially be out of range. Bonus: in the absence of such jumps, this option does not affect code size or performance. The default is --trampolines.
--abi-windowed, --abi-call0 — picks the ABI tag written to the .xtensa.info section. The ABI tag indicates the ABI of the assembly code, and the linker will issue a warning if you try to link object files with inconsistent ABI tags 👀. The default ABI is chosen by the Xtensa core configuration.

The following options are available when as is configured for an Z80 processor. (Yes, we're doing a whole new arc, bestie 🎀.)

@chapter Z80 Dependent Features 👑

Command-line Options 💖

-march=CPU[-EXT...][+EXT...] — this option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor 🚫. The following processor names are recognized: z80, z180, ez80, gbz80, z80n, r800. On top of the basic instruction set, the assembler can be told to accept some extension mnemonics. For example, -march=z180+sli+infc extends z180 with SLI instructions and IN F,(C). The following extensions are currently supported: full (all known instructions), adl (ADL CPU mode by default, eZ80 only), sli (instruction known as SLI, SLL or SL1), xyhl (instructions with halves of index registers: IXL, IXH, IYL, IYH), xdcb (instructions like RotOp (II+d),R and BitOp n,(II+d),R), infc (instruction IN F,(C) or IN (C)), outc0 (instruction OUT (C),0). Note that rather than extending a basic instruction set, the extension mnemonics starting with - revoke the respective functionality: -march=z80-full+xyhl first removes all default extensions and adds support for index registers halves only.

If this option is not specified then -march=z80+xyhl+infc is assumed.

-local-prefix=prefix — mark all labels with the specified prefix as local. But such a label can be marked global explicitly in the code. This option do not change the default local label prefix .L, it is just adds new one.
-colonless — accept colonless labels. All symbols at line begin are treated as labels. no colon no problem 💅.
-sdcc — accept assembler code produced by SDCC.
-fp-s=FORMAT — single precision floating point numbers format. Default: ieee754 (32 bit).
-fp-d=FORMAT — double precision floating point numbers format. Default: ieee754 (64 bit).

COPYRIGHT 📜

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".

and that's the whole page, bestie 🫶 this was AS(1) from binutils-2.47, dated 2026-09-19 — icon behaviour honestly, go assemble something iconic 👑💖

📦 where this page comes from

ubuntu stonking: binutils-sh-elf 2.47+3build2 · GPL-3.0-or-later
💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash on 2026-11-03: a language model's rewrite of the original, under its terms