SANCOV(1)
okay so bestie, welcome to sancov(1) β a User Command and honestly a whole LLVM-adjacent icon. π She is the Sanitizer Coverage Processing Tool, and yes she has a lot of options, and yes we are going to go through every single one of them, because that's what we do here. Grab a boba. π§
NAME
sancov β manual page for sancov 13. That's the name. Short, sweet, iconic. π
DESCRIPTION
OVERVIEW β¨
Sanitizer Coverage Processing Tool (sancov)
This tool can extract various coverage-related information from: coverage-instrumented binary files, raw .sancov files and their symbolized .symcov version. Depending on chosen action the tool expects different input files, and here's the receipts on which action wants what: π
-print-coverage-pcsβ coverage-instrumented binary files-print-coverageβ.sancovfiles<other actions>β.sancovfiles & corresponding binary files,.symcovfiles
So like, feed her the right snack for the right job or she's just gonna stand there. π
USAGE
sancov [options] <action> <binary files...> <.sancov files...> <.symcov files...>
Options first, then the action (required, we'll get to her), then your files. In that order. She's not flexible about it. π
OPTIONS
Color Options π¨
--colorβ Use colors in output (default=autodetect)
General options
Okay so this is the long part. Like, the long part. Every one of these lives here, no skips, no cuts. π
--aarch64-neon-syntax=<value>β Choose style of NEON code to emit from AArch64 backend:=genericβ Emit generic NEON assembly=appleβ Emit Apple-style NEON assembly
--aarch64-use-aaβ Enable the use of AA during codegen.--abort-on-max-devirt-iterations-reachedβ Abort when the max iterations for devirtualization CGSCC repeat pass is reached--allow-ginsert-as-artifactβ AllowG_INSERTto be considered an artifact. Hack around AMDGPU test infinite loops.--amdgpu-bypass-slow-divβ Skip 64-bit divide for dynamic 32-bit values--amdgpu-disable-loop-alignmentβ Do not align and prefetch loops--amdgpu-disable-power-schedβ Disable scheduling to minimize mAI power bursts--amdgpu-dpp-combineβ Enable DPP combiner--amdgpu-dump-hsa-metadataβ Dump AMDGPU HSA Metadata--amdgpu-enable-flat-scratchβ Use flat scratch instructions--amdgpu-enable-merge-m0β Merge and hoist M0 initializations--amdgpu-promote-alloca-to-vector-limit=<uint>β Maximum byte size to consider promote alloca to vector--amdgpu-reserve-vgpr-for-sgpr-spillβ Allocates one VGPR for future SGPR Spill--amdgpu-sdwa-peepholeβ Enable SDWA peepholer--amdgpu-use-aa-in-codegenβ Enable the use of AA during codegen.--amdgpu-verify-hsa-metadataβ Verify AMDGPU HSA Metadata--amdgpu-vgpr-index-modeβ Use GPR indexing mode instead of movrel for vector indexing--arm-add-build-attributesβ no description on the page for this one, she's just there, mysterious and silent π«₯--arm-implicit-it=<value>β Allow conditional instructions outdside of an IT block=alwaysβ Accept in both ISAs, emit implicit ITs in Thumb=neverβ Warn in ARM, reject in Thumb=armβ Accept in ARM, reject in Thumb=thumbβ Warn in ARM, emit implicit ITs in Thumb
--asm-show-instβ Emit internal instruction representation to assembly file--atomic-counter-update-promotedβ Do counter update using atomic fetch add for promoted counters only--atomic-first-counterβ Use atomic fetch add for first counter in a function (usually the entry counter)--blacklist=<string>β Blacklist file (sanitizer blacklist format).--bounds-checking-single-trapβ Use one trap block per function--cfg-hide-cold-paths=<number>β Hide blocks with relative frequency below the given value--cfg-hide-deoptimize-pathsβ no description given, just vibes π«§--cfg-hide-unreachable-pathsβ also no description given, also just vibes π«§--cost-kind=<value>β Target cost kind=throughputβ Reciprocal throughput=latencyβ Instruction latency=code-sizeβ Code size=size-latencyβ Code size and latency
Action (required) π¨
Yes bestie, you have to pick one. This is the whole point of the tool. Don't skip her.
--printβ Print coverage addresses--print-coverage-pcsβ Print coverage instrumentation points addresses.--covered-functionsβ Print all covered funcions.--not-covered-functionsβ Print all not covered funcions.--print-coverage-statsβ Print coverage statistics.--html-reportβ REMOVED. Use-symbolize&coverage-report-server.py.--symbolizeβ Produces a symbolized JSON report from binary report.--mergeβ Merges reports.
β οΈ<red>Not me being the bearer of bad news but--html-reportis REMOVED, okay? She's gone. If you want that, it's-symbolizepluscoverage-report-server.py. Do not come for me, I'm just the messenger. π
General options (continued) π¦
And we're back to the general options, because she wasn't done with you yet.
--debugify-level=<value>β Kind of debug info to add=locationsβ Locations only=location+variablesβ Locations and Variables
--debugify-quietβ Suppress verbose debugify output--demangleβ Print demangled function name.--disable-i2p-p2i-optβ Disablesinttoptr/ptrtointroundtrip optimization--disable-promote-alloca-to-ldsβ Disable promote alloca to LDS--disable-promote-alloca-to-vectorβ Disable promote alloca to vector--do-counter-promotionβ Do counter register promotion--dot-cfg-mssa=<file name for generated dot file>β file name for generated dot file--dwarf-version=<int>β Dwarf version--dwarf64β Generate debugging info in the 64-bit DWARF format--emscripten-cxx-exceptions-allowed=<string>β The list of function names in which Emscripten-style exception handling is enabled (see emscriptenEMSCRIPTEN_CATCHING_ALLOWEDoptions)--enable-cse-in-irtranslatorβ Should enable CSE in irtranslator--enable-cse-in-legalizerβ Should enable CSE in Legalizer--enable-emscripten-cxx-exceptionsβ WebAssembly Emscripten-style exception handling--enable-emscripten-sjljβ WebAssembly Emscripten-stylesetjmp/longjmphandling--enable-gvn-hoistβ Enable the GVN hoisting pass (default = off)--enable-gvn-memdepβ no description on the page, she's keeping it to herself π€«--enable-gvn-sinkβ Enable the GVN sinking pass (default = off)--enable-load-in-loop-preβ no description on the page π--enable-load-preβ no description on the page π--enable-loop-simplifycfg-term-foldingβ no description on the page π--enable-name-compressionβ Enable name/filename string compression--enable-split-backedge-in-load-preβ no description on the page π--fatal-warningsβ Treat warnings as errors--force-opaque-pointersβ Force all pointers to be opaque pointers--gpsize=<uint>β Global Pointer Addressing Size. The default size is 8.--hash-based-counter-splitβ Rename counter variable of a comdat function based on cfg hash--hot-cold-splitβ Enable hot-cold splitting pass--import-all-indexβ Import all external functions in index.--incremental-linker-compatibleβ When used withfiletype=obj, emit an object file which can be used with an incremental linker--instcombine-code-sinkingβ Enable code sinking--instcombine-guard-widening-window=<uint>β How wide an instruction window to bypass looking for another guard--instcombine-max-iterations=<uint>β Limit the maximum number of instruction combining iterations--instcombine-max-num-phis=<uint>β Maximum number phis to handle inintptr/ptrintfolding--instcombine-maxarray-size=<uint>β Maximum array size considered when doing a combine--instcombine-negator-enabledβ Should we attempt to sink negations?--instcombine-negator-max-depth=<uint>β What is the maximal lookup depth when trying to check for viability of negation sinking.--instrprof-atomic-counter-update-allβ Make all profile counter updates atomic (for testing only)--internalize-public-api-file=<filename>β A file containing list of symbol names to preserve--internalize-public-api-list=<list>β A list of symbol names to preserve--iterative-counter-promotionβ Allow counter promotion across the whole loop nest.--lto-embed-bitcode=<value>β Embed LLVM bitcode in object files produced by LTO=noneβ Do not embed=optimizedβ Embed after all optimization passes=post-merge-pre-optβ Embed post merge, but before optimizations
--lto-pass-remarks-filter=<regex>β Only record optimization remarks from passes whose names match the given regular expression--lto-pass-remarks-format=<format>β The format used for serializing remarks (default: YAML)--lto-pass-remarks-output=<filename>β Output filename for pass remarks--matrix-default-layout=<value>β Sets the default matrix layout=column-majorβ Use column-major layout=row-majorβ Use row-major layout
--max-counter-promotions=<int>β Max number of allowed counter promotions--max-counter-promotions-per-loop=<uint>β Max number counter promotions per loop to avoid increasing register pressure too much--mc-relax-allβ When used withfiletype=obj, relax all fixups in the emitted object file
And that's where part 1 lands, bestie β she keeps going. π
--merror-missing-parenthesisβ throws an error when a parenthesis is missing around predicate registers. she does not let that slide π--merror-noncontigious-registerβ errors out on register names that aren't contigious (yes, the original spells it like that, we don't gatekeep spelling here π«Ά).--mhvxβ turn on Hexagon Vector eXtensions β¨--mhvx=<value>β turn on Hexagon Vector eXtensions, but pick your flavor:=v60β Build for HVX v60=v62β Build for HVX v62=v65β Build for HVX v65=v66β Build for HVX v66=v67β Build for HVX v67=v68β Build for HVX v68
--mips-compact-branches=<value>β MIPS Specific: the compact branch policy, aka how much do we love compact branches π=neverβ Do not use compact branches if possible.=optimalβ Use compact branches where appropriate (default, bestie, this is the one you get for free).=alwaysβ Always use compact branches if possible.
--mips16-constant-islandsβ Enable mips16 constant islands. ποΈ--mips16-hard-floatβ Enable mips16 hard float.--mir-strip-debugify-onlyβ Should mir-strip-debug only strip debug info from debugified modules by default--mno-compoundβ Disable looking for compound instructions for Hexagon--mno-fixupβ Disable fixing up resolved relocations for Hexagon--mno-ldc1-sdc1β Expand double precision loads and stores to their single precision counterparts--mno-pairingβ Disable looking for duplex instructions for Hexagon--mwarn-missing-parenthesisβ warn (not error, she's being nice) for missing parenthesis around predicate registers--mwarn-noncontigious-registerβ warn for register names that arent contigious--mwarn-sign-mismatchβ warn for mismatching a signed and unsigned value π--no-deprecated-warnβ Suppress all deprecated warnings. the deprecated stuff is still deprecated though, this just shuts her up π--no-discriminatorsβ Disable generation of discriminator information.--no-type-checkβ Suppress type errors (Wasm)--no-warnβ Suppress all warnings π--nvptx-sched4regβ NVPTX Specific: schedule for register pressue (yep, "pressue", that's how it's spelled in the original, no cap)--poison-checking-function-localβ Check that returns are non-poison (for testing)--r600-ir-structurizeβ Use StructurizeCFG IR pass--rdf-dumpβ no description given in the original, she's mysterious π--rdf-limit=<uint>β also no description. silence is a vibe π--runtime-counter-relocationβ Enable relocating counters at runtime.--safepoint-ir-verifier-print-onlyβ again, no description, we love an enigma β¨--sample-profile-check-record-coverage=<N>β Emit a warning if less than N% of records in the input profile are matched to the IR.--sample-profile-check-sample-coverage=<N>β Emit a warning if less than N% of samples in the input profile are matched to the IR.--sample-profile-max-propagate-iterations=<uint>β Maximum number of iterations to go through when propagating sample block/edge weights through the CFG.--skip-dead-filesβ Do not list dead source files in reports.--skip-ret-exit-blockβ Suppress counter promotion if exit blocks contain ret.--speculative-counter-promotion-max-exiting=<uint>β The max number of exiting blocks of a loop to allow speculative counter promotion--speculative-counter-promotion-to-loopβ When the option is false, if the target block is in a loop, the promotion will be disallowed unless the promoted counter update can be further/iteratively promoted into an acyclic region.--strip_path_prefix=<string>β Strip this prefix from file paths in reports.--summary-file=<string>β The summary file to use for function importing.--tail-predication=<value>β MVE tail-predication pass options π¦=disabledβ Don't tail-predicate loops=enabled-no-reductionsβ Enable tail-predication, but not for reduction loops=enabledβ Enable tail-predication, including reduction loops=force-enabled-no-reductionsβ Enable tail-predication, but not for reduction loops, and force this which might be unsafe β οΈ=force-enabledβ Enable tail-predication, including reduction loops, and force this which might be unsafe β οΈ
okay bestie, see the word unsafe twice up there? that's not decoration. that's the original talking. force at your own risk π₯
--thinlto-assume-mergedβ Assume the input has already undergone ThinLTO function importing and the other pre-optimization pipeline changes.--threads=<int>β no description in the original. she said "figure it out" π--verify-region-infoβ Verify region info (time consuming) β she literally tells you it's slow, respect the honesty β³--vp-counters-per-site=<number>β The average number of profile counters allocated per value profiling site.--vp-static-allocβ Do static counter allocation for value profiler--x86-align-branch=<string>β Specify types of branches to align (plus separated list of types):jccβ indicates conditional jumpsfusedβ indicates fused conditional jumpsjmpβ indicates direct unconditional jumpscallβ indicates direct and indirect callsretβ indicates retsindirectβ indicates indirect unconditional jumps
--x86-align-branch-boundary=<uint>β Control how the assembler should align branches with NOP. If the boundary's size is not 0, it should be a power of 2 and no less than 32. Branches will be aligned to prevent from being across or against the boundary of specified size. The default value 0 does not align branches.--x86-branches-within-32B-boundariesβ Align selected instructions to mitigate negative performance impact of Intel's micro code update for errata skx102. May break assumptions about labels corresponding to particular instructions, and should be used with caution.
β οΈ read that again: "May break assumptions about labels corresponding to particular instructions, and should be used with caution." that is a real warning from the real page, not me being dramatic (for once) π
--x86-pad-max-prefix-size=<uint>β Maximum number of prefixes to use for padding
β¨ Generic Options β¨
the universal classics, everyone gets these π
--helpβ Display available options (--help-hiddenfor more)--help-listβ Display list of available options (--help-list-hiddenfor more)--versionβ Display the version of this program
π¦ Polly Options: Configure the polly loop optimizer π¦
she's the loop optimizer and she has OPINIONS π
--pollyβ Enable the polly optimizer (with-O1,-O2or-O3)--polly-2nd-level-tilingβ Enable a 2nd level loop of loop tiling--polly-ast-print-accessesβ Print memory access functions--polly-context=<isl parameter set>β Provide additional constraints on the context parameters--polly-dce-precise-steps=<int>β The number of precise steps between two approximating iterations. (A value of -1 schedules another approximation stage before the actual dead code elimination.--polly-delicm-max-ops=<int>β Maximum number of isl operations to invest for lifetime analysis; 0=no limit--polly-detect-full-functionsβ Allow the detection of full functions--polly-dump-afterβ Dump module after Polly transformations into a file suffixed with "-after"--polly-dump-after-file=<string>β Dump module after Polly transformations to the given file--polly-dump-beforeβ Dump module before Polly transformations into a file suffixed with "-before"--polly-dump-before-file=<string>β Dump module before Polly transformations to the given file--polly-enable-simplifyβ Simplify SCoP after optimizations--polly-ignore-func=<string>β Ignore functions that match a regex. Multiple regexes can be comma separated. Scop detection will ignore all functions that match ANY of the regexes provided.--polly-isl-arg=<argument>β Option passed to ISL--polly-on-isl-error-abortβ Abort if an isl error is encountered--polly-only-func=<string>β Only run on functions that match a regex. Multiple regexes can be comma separated. Scop detection will run on all functions that match ANY of the regexes provided.--polly-only-region=<identifier>β Only run on certain regions (The provided identifier must appear in the name of the region's entry block--polly-only-scop-detectionβ Only run scop detection, but no other optimizations--polly-optimized-scopsβ Polly - Dump polyhedral description of Scops optimized with the isl scheduling optimizer and the set of post-scheduling transformations is applied on the schedule tree--polly-parallelβ Generate thread parallel code (isl codegen only)--polly-parallel-forceβ Force generation of thread parallel code ignoring any cost model--polly-pattern-matching-based-optsβ Perform optimizations based on pattern matching--polly-pragma-based-optsβ Apply user-directed transformation from metadata--polly-process-unprofitableβ Process scops that are unlikely to benefit from Polly optimizations.--polly-register-tilingβ Enable register tiling--polly-reportβ Print information about the activities of Polly--polly-showβ bestie this one highlights the code regions that are gonna get optimized, and it's giving full glow-up energy in a (CFG BBs and LLVM-IR instructions) β¨ like it lights up the blocks and the IR instructions, no crumbs left--polly-show-onlyβ same sparkle, but lowkey more minimal: it highlights the code regions that will be optimized in a (CFG only BBs) π so CFG only, we're not doing the IR this time--polly-stmt-granularity=<value>β the algorithm to use for splitting basic blocks into multiple statements π§ pick your fighter:=bbβ one statement per basic block, periodt=scalar-indepβ the scalar independence heuristic, iykyk=storeβ store-level granularity, obsessed
--polly-target=<value>β tells it the hardware to target π=cpuβ generate CPU code, main character behavior fr fr
--polly-tilingβ enable loop tiling π₯ it's literally in the name and it's iconic--polly-vectorizer=<value>β select the vectorization strategy π choose your vibe:=noneβ no Vectorization, we're sitting this one out π=pollyβ Polly internal vectorizer, the homegrown one π«Ά=stripmineβ strip-mine outer loops for the loop-vectorizer to trigger, which is so smart of it ngl
and that's the whole page bestie, we ate and left zero crumbs π this was sancov, version 13, dated July 2023, from the SANCOV(1) manual β go forth and instrument responsibly, mwah ππ¦πΈ
π¦ where this page comes from
- ubuntu jammy: clang-tools-13 1:13.0.1-2ubuntu2.2 Β· APACHE-2-LLVM-EXCEPTIONS
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms