SANCOV(1)
πΈ NAME πΈ
sancov β manual page for sancov 12. yeah bestie, that's the whole name section, it's giving minimal. this is the man page for the Sanitizer Coverage Processing Tool, and it's sancov(1) if you're being formal about it π
π¦ DESCRIPTION π¦
β¨ OVERVIEW: Sanitizer Coverage Processing Tool (sancov) β¨
okay so picture this: sancov is your little coverage goblin π§ and what it does is extract various coverage-related information from a whole bunch of places:
- coverage-instrumented binary files
- raw
.sancovfiles - and their symbolized
.symcovversion
and here's the tea β depending on which action you pick, the tool expects different input files, so pls don't just throw everything at it and hope π
-print-coverage-pcsβ this one wants coverage-instrumented binary files-print-coverageβ this one wants.sancovfiles<other actions>β these want.sancovfiles & corresponding binary files, plus.symcovfiles
β USAGE β
sancov [options] <action> <binary files...> <.sancov files...> <.symcov files...>
π OPTIONS π
π Color Options π
--colorβ use colors in the output (default=autodetect). she's automatic about it, she just knows π
π General options π
okay this next part is LONG, like, scroll-for-days long, but every single one of these is real and we're going through all of them, no skipping, we're not cowards:
--aarch64-neon-syntax=<value>β choose which style of NEON code to emit from the AArch64 backend:=genericβ emit generic NEON assembly=appleβ emit Apple-style NEON assembly
--abort-on-max-devirt-iterations-reachedβ abort when the max iterations for the devirtualization CGSCC repeat pass is reached--amdgpu-bypass-slow-divβ skip the 64-bit divide for dynamic 32-bit values--amdgpu-disable-loop-alignmentβ do not align and prefetch loops--amdgpu-disable-power-schedβ disable scheduling to minimize mAI power bursts--amdgpu-dpp-combineβ enable DPP combiner--amdgpu-dump-hsa-metadataβ dump AMDGPU HSA Metadata--amdgpu-enable-flat-scratchβ use flat scratch instructions--amdgpu-enable-merge-m0β merge and hoist M0 initializations--amdgpu-promote-alloca-to-vector-limit=<uint>β maximum byte size to consider promote alloca to vector--amdgpu-reserve-vgpr-for-sgpr-spillβ allocates one VGPR for future SGPR Spill--amdgpu-sdwa-peepholeβ enable SDWA peepholer--amdgpu-use-aa-in-codegenβ enable the use of AA during codegen.--amdgpu-verify-hsa-metadataβ verify AMDGPU HSA Metadata--amdgpu-vgpr-index-modeβ use GPR indexing mode instead of movrel for vector indexing--arm-add-build-attributesβ (no description, she's mysterious, she contains multitudes π«Ά)--arm-implicit-it=<value>β allow conditional instructions outdside of an IT block (yes, that typo is canon, we keep it exactly as it is):=alwaysβ accept in both ISAs, emit implicit ITs in Thumb=neverβ warn in ARM, reject in Thumb=armβ accept in ARM, reject in Thumb=thumbβ warn in ARM, emit implicit ITs in Thumb
--atomic-counter-update-promotedβ do counter update using atomic fetch add for promoted counters only--atomic-first-counterβ use atomic fetch add for the first counter in a function (usually the entry counter)--blacklist=<string>β blacklist file (sanitizer blacklist format).--bounds-checking-single-trapβ use one trap block per function--cfg-hide-deoptimize-pathsβ (again, no description, we respect her privacy π)--cfg-hide-unreachable-pathsβ (same, no description given)--cost-kind=<value>β target cost kind:=throughputβ reciprocal throughput=latencyβ instruction latency=code-sizeβ code size=size-latencyβ code size and latency
π Action (required) π
bestie this bit is required, like, do not skip it, the vibe check will fail:
--printβ print coverage addresses--print-coverage-pcsβ print coverage instrumentation points addresses.--covered-functionsβ print all covered funcions. (spelling preserved, iconic, no notes)--not-covered-functionsβ print all not covered funcions.--print-coverage-statsβ print coverage statistics.--html-reportβ REMOVED. use-symbolize&coverage-report-server.py. she's gone girl, she left the chat π--symbolizeβ produces a symbolized JSON report from binary report.--mergeβ merges reports.--cvp-dont-add-nowrap-flagsβ (no description listed, lowkey a mystery π΅οΈ)--debugify-level=<value>β kind of debug info to add:=locationsβ locations only=location+variablesβ locations and variables
--debugify-quietβ suppress verbose debugify output--demangleβ print demangled function name.--disable-promote-alloca-to-ldsβ disable promote alloca to LDS--disable-promote-alloca-to-vectorβ disable promote alloca to vector--do-counter-promotionβ do counter register promotion--dot-cfg-mssa=<file name for generated dot file>β file name for generated dot file--emscripten-cxx-exceptions-allowed=<string>β the list of function names in which Emscripten-style exception handling is enabled (see emscriptenEMSCRIPTEN_CATCHING_ALLOWEDoptions)--enable-cse-in-irtranslatorβ should enable CSE in irtranslator--enable-cse-in-legalizerβ should enable CSE in Legalizer--enable-emscripten-cxx-exceptionsβ WebAssembly Emscripten-style exception handling--enable-emscripten-sjljβ WebAssembly Emscripten-stylesetjmp/longjmphandling--enable-gvn-hoistβ enable the GVN hoisting pass (default = off)--enable-gvn-memdepβ (no description given, we simply don't know her like that π)--enable-gvn-sinkβ enable the GVN sinking pass (default = off)--enable-load-in-loop-preβ (no description)--enable-load-preβ (no description)--enable-loop-simplifycfg-term-foldingβ (no description)--enable-name-compressionβ enable name/filename string compression--enable-split-backedge-in-load-preβ (no description)--gpsize=<uint>β Global Pointer Addressing Size. the default size is8.--hash-based-counter-splitβ rename counter variable of a comdat function based on cfg hash--hot-cold-splitβ enable hot-cold splitting pass--import-all-indexβ import all external functions in index.--instcombine-code-sinkingβ enable code sinking--instcombine-guard-widening-window=<uint>β how wide an instruction window to bypass looking for another guard--instcombine-max-iterations=<uint>β limit the maximum number of instruction combining iterations--instcombine-max-num-phis=<uint>β maximum number phis to handle in intptr/ptrint folding--instcombine-maxarray-size=<uint>β maximum array size considered when doing a combine--instcombine-negator-enabledβ should we attempt to sink negations?--instcombine-negator-max-depth=<uint>β what is the maximal lookup depth when trying to check for viability of negation sinking.--instcombine-unsafe-select-transformβ enable poison-unsafe select to and/or transform--instrprof-atomic-counter-update-allβ make all profile counter updates atomic (for testing only)--internalize-public-api-file=<filename>β a file containing list of symbol names to preserve--internalize-public-api-list=<list>β a list of symbol names to preserve--iterative-counter-promotionβ allow counter promotion across the whole loop nest.--lto-embed-bitcode=<value>β embed LLVM bitcode in object files produced by LTO:=noneβ do not embed=optimizedβ embed after all optimization passes=post-merge-pre-optβ embed post merge, but before optimizations
--lto-pass-remarks-filter=<regex>β only record optimization remarks from passes whose names match the given regular expression--lto-pass-remarks-format=<format>β the format used for serializing remarks (default: YAML)--lto-pass-remarks-output=<filename>β output filename for pass remarks--matrix-default-layout=<value>β sets the default matrix layout:=column-majorβ use column-major layout=row-majorβ use row-major layout
--max-counter-promotions=<int>β max number of allowed counter promotions--max-counter-promotions-per-loop=<uint>β max number counter promotions per loop to avoid increasing register pressure too much--merror-missing-parenthesisβ error for missing parenthesis around predicate registers--merror-noncontigious-registerβ error for register names that aren't contigious (again, spelling is canon, hands off β)--mhvxβ enable Hexagon Vector eXtensions--mhvx=<value>β enable Hexagon Vector eXtensions:=v60β build for HVX v60=v62β build for HVX v62=v65β build for HVX v65=v66β build for HVX v66=v67β build for HVX v67
--mips-compact-branches=<value>β MIPS Specific: Compact branch policy.=neverβ do not use compact branches if possible.=optimalβ use compact branches where appropriate (default).=alwaysβ always use compact branches if possible.
--mips16-constant-islandsβ enable mips16 constant islands.--mips16-hard-floatβ enable mips16 hard float.--mir-strip-debugify-onlyβ tellsmir-strip-debugto only strip debug info from modules that got debugified, by default. iykyk π--mno-compoundβ Hexagon stans, this one says stop looking for compound instructions.--mno-fixupβ also Hexagon: turn off the fixing-up of resolved relocations.--mno-ldc1-sdc1β expand double-precision loads and stores into their single-precision counterparts. glow-down but do it π«Ά--mno-pairingβ Hexagon again bestie: don't go looking for duplex instructions.--mwarn-missing-parenthesisβ yell at you (a warning, not a crash) when parenthesis is missing around predicate registers.--mwarn-noncontigious-registerβ warn when register names aren't contigious (yes the spelling is giving what it's giving, we don't fix it π).--mwarn-sign-mismatchβ warn when a signed and an unsigned value don't match up.--no-discriminatorsβ turn off generation of discriminator information.--nvptx-sched4regβ NVPTX Specific: schedule for register pressue. yes, pressue. iconic typo, no notes πΈ--poison-checking-function-localβ check that returns are non-poison (for testing, bestie, not for production).--r600-ir-structurizeβ use the StructurizeCFG IR pass.--rdf-dumpβ no description given. the manpage is gatekeeping π--rdf-limit=<uint>β also no description. mysterious behavior, we respect it.--runtime-counter-relocationβ enable relocating counters at runtime.--safepoint-ir-verifier-print-onlyβ no description. it's giving mystery β¨--sample-profile-check-record-coverage=<N>β emit a warning if less than N% of records in the input profile actually matched up with the IR.--sample-profile-check-sample-coverage=<N>β emit a warning if less than N% of samples in the input profile matched up with the IR.--sample-profile-max-propagate-iterations=<uint>β the maximum number of iterations to go through when propagating sample block/edge weights through the CFG.--skip-dead-filesβ do not list dead source files in reports. they're dead, let them rest πͺ¦--skip-ret-exit-blockβ suppress counter promotion if exit blocks containret.--speculative-counter-promotion-max-exiting=<uint>β the max number of exiting blocks of a loop you'll allow speculative counter promotion for.--speculative-counter-promotion-to-loopβ when this option is false, if the target block is in a loop, the promotion gets disallowed unless the promoted counter update can be further/iteratively promoted into an acyclic region.--strip_path_prefix=<string>β strip this prefix from file paths in reports.--summary-file=<string>β the summary file to use for function importing.--tail-predication=<value>β MVE tail-predication pass options:=disabledβ don't tail-predicate loops at all.=enabled-no-reductionsβ enable tail-predication, but not for reduction loops.=enabledβ enable tail-predication, reduction loops included.=force-enabled-no-reductionsβ enable tail-predication but not for reduction loops, and force it, which might be unsafe.=force-enabledβ enable tail-predication including reduction loops, and force it, which might be unsafe.
bestie those force- ones literally say "might be unsafe" in the source. they are not playing. proceed with the awareness π
--thinlto-assume-mergedβ assume the input already went through ThinLTO function importing and the other pre-optimization pipeline changes.--threads=<int>β no description. you know what it does, bestie.--verify-region-infoβ verify region info. it is time consuming, so maybe grab a snack π--vp-counters-per-site=<number>β the average number of profile counters allocated per value profiling site.--vp-static-allocβ do static counter allocation for the value profiler.--x86-align-branch=<string>β specify which types of branches to align (it's a plus-separated list of types):jccβ indicates conditional jumpsfusedβ indicates fused conditional jumpsjmpβ indicates direct unconditional jumpscallβ indicates direct and indirect callsretβ indicates retsindirectβ indicates indirect unconditional jumps
--x86-align-branch-boundary=<uint>β control how the assembler should align branches with NOP. if the boundary's size isn't0, it has to be a power of 2 and no less than32. branches get aligned so they don't end up across or against the boundary of the specified size. the default value0means no branch alignment.--x86-branches-within-32B-boundariesβ align selected instructions to soften the negative performance impact of Intel's micro code update for errataskx102. heads up: this may break assumptions about labels corresponding to particular instructions, and should be used with caution.--x86-pad-max-prefix-size=<uint>β maximum number of prefixes to use for padding.
β¨ Generic Options β¨
--helpβ display available options (--help-hiddenfor more). the moment you need it fr fr π«Ά--help-listβ display a list of available options (--help-list-hiddenfor more).--versionβ display the version of this program.
π¦ Polly Options π¦
Configure the polly loop optimizer π
--pollyβ enable the polly optimizer (only at-O3).--polly-2nd-level-tilingβ enable a 2nd level loop of loop tiling.--polly-ast-print-accessesβ print memory access functions.--polly-context=<isl parameter set>β provide extra constraints on the context parameters.--polly-dce-precise-steps=<int>β the number of precise steps between two approximating iterations. (a value of-1schedules another approximation stage before the actual dead code elimination.--polly-delicm-max-ops=<int>β maximum number of isl operations to invest in lifetime analysis;0= no limit.--polly-detect-full-functionsβ allow the detection of full functions.--polly-dump-afterβ dump the module after Polly transformations into a file suffixed with"-after".--polly-dump-after-file=<string>β dump the module after Polly transformations to the given file.--polly-dump-beforeβ dump the module before Polly transformations into a file suffixed with"-before".--polly-dump-before-file=<string>β dump the module before Polly transformations to the given file.--polly-enable-simplifyβ simplify SCoP after optimizations.--polly-ignore-func=<string>β ignore functions that match a regex. multiple regexes can be comma separated. scop detection will ignore all functions that match ANY of the regexes you provide.--polly-isl-arg=<argument>β option passed to ISL.--polly-on-isl-error-abortβ abort if an isl error is encountered.--polly-only-func=<string>β only run on functions that match a regex. multiple regexes can be comma separated. scop detection will run on all functions that match ANY of the regexes you provide.--polly-only-region=<identifier>β only run on certain regions (the identifier you provide must appear in the name of the region's entry block).--polly-only-scop-detectionβ only run scop detection, no other optimizations.--polly-optimized-scopsβ Polly β dump the polyhedral description of Scops optimized with the isl scheduling optimizer, and the set of post-scheduling transformations is applied on the schedule tree.--polly-parallelβ generate thread parallel code (isl codegen only).--polly-parallel-forceβ force generation of thread parallel code, ignoring any cost model.--polly-pattern-matching-based-optsβ perform optimizations based on pattern matching.--polly-process-unprofitableβ process scops that are unlikely to benefit from Polly optimizations.--polly-register-tilingβ enable register tiling.--polly-reportβ print information about the activities of Polly.--polly-showβ highlight the code regions that will be optimized in a (CFG BBs and LLVM-IR instructions).--polly-show-onlyβ highlight the code regions that will be optimized in a (CFG only BBs).--polly-stmt-granularity=<value>β algorithm to use for splitting basic blocks into multiple statements:=bbβ one statement per basic block=scalar-indepβ scalar independence heuristic=storeβ store-level granularity
--polly-target=<value>β the hardware to target:=cpuβ generate CPU code
--polly-tilingβ enable loop tiling.--polly-vectorizer=<value>β select the vectorization strategy:=noneβ no Vectorization=pollyβ Polly internal vectorizer=stripmineβ strip-mine outer loops for the loop-vectorizer to trigger
and that's the whole thing, bestie π you made it to the end of sancov and honestly? main character energy π
this was sancov version 12, dated February 2022, filed under SANCOV(1) β go forth and slay your coverage reports fr fr πβ¨π
π¦ where this page comes from
- ubuntu jammy: clang-tools-12 1:12.0.1-19ubuntu3 Β· APACHE-2-LLVM-EXCEPTIONS
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms