AS(1)

📦 version 2.47, in arch rolling

💅 AS(1) — the portable GNU assembler 💅

okay bestie, welcome to as, the portable GNU assembler, straight out of the GNU Development Tools friend group. she's iconic, she's portable, she's literally the assembler manual you're reading. no cap. 🫶

🌸 NAME 🌸

as / AS — the portable GNU assembler. that's the whole name. short, sweet, slay. ✨

✨ SYNOPSIS ✨

here's the full shape of the command, and yes you're gonna wanna keep every bracket exactly where it is — these brackets are load-bearing, bestie 💀

as [-a[cdghilns][=file]]
 [--alternate]
 [--compress-debug-sections] [--nocompress-debug-sections]
 [-D]
 [--dump-config]
 [--debug-prefix-map old=new]
 [--defsym sym=val]
 [--elf-stt-common=[no|yes]]
 [--emulation=name]
 [-f]
 [-g] [--gstabs] [--gstabs+]
 [--gdwarf-<N>] [--gdwarf-sections]
 [--gdwarf-cie-version=VERSION]
 [--generate-missing-build-notes=[no|yes]]
 [--gsframe] [--gsframe=[no|yes]]
 [--gsframe-3]
 [--hash-size=N]
 [--help] [--target-help]
 [--info] [--no-info]
 [-I dir]
 [-J]
 [-K]
 [--keep-locals]
 [-L]
 [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM]
 [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM]
 [--multibyte-handling=[allow|warn|warn-sym-only]]
 [--no-pad-sections]
 [-o objfile] [-R]
 [--reloc-section-sym=[all|internal|none]]
 [--scfi=experimental]
 [--sectname-subst]
 [--size-check=[error|warning]]
 [--statistics]
 [-v] [--verbose]
 [-version] [--version]
 [-W] [--no-warn] [--warn] [--fatal-warnings]
 [-w] [-x]
 [-Z] [@FILE]
 [target-options]
 [--|files ...]

🎯 TARGET 🎯

target options are where as gets to choose its little architecture outfit. the original lists them grouped by target, so that's exactly how we're serving them. all spellings below are copied exactly — do not “fix” them, bestie, these are load-bearing brackets 💀

💖 Target AArch64 options 💖

[-EB|-EL]
[-mabi=ABI]

🦋 Target Alpha options 🦋

[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]

🌸 Target ARC options 🌸

[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]

🎀 Target ARM options 🎀

[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
 -mapcs-reentrant]
[-mthumb-interwork] [-k]

💜 Target Blackfin options 💜

[-mcpu=processor[-sirevision]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]

⭐ Target BPF options ⭐

[-EL] [-EB]

🌈 Target CRIS options 🌈

[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
[--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]

🧚 Target C-SKY options 🧚

[-march=arch] [-mcpu=cpu]
[-EL] [-mlittle-endian] [-EB] [-mbig-endian]
[-fpic] [-pic]
[-mljump] [-mno-ljump]
[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
[-mnolrw ] [-mno-lrw]
[-melrw] [-mno-elrw]
[-mlaf ] [-mliterals-after-func]
[-mno-laf] [-mno-literals-after-func]
[-mlabr] [-mliterals-after-br]
[-mno-labr] [-mnoliterals-after-br]
[-mistack] [-mno-istack]
[-mhard-float] [-mmp] [-mcp] [-mcache]
[-msecurity] [-mtrust]
[-mdsp] [-medsp] [-mvdsp]

🍓 Target D10V options 🍓

[-O]

💫 Target D30V options 💫

[-O|-n|-N]

🌟 Target EPIPHANY options 🌟

[-mepiphany|-mepiphany16]

🧁 Target H8/300 options 🧁

[-h-tick-hex]

🔥 Target i386 options 🔥

[--32|--x32|--64] [-n]
[-march=CPU[+EXTENSION...]] [-mtune=CPU]

🫧 Target IA-64 options 🫧

[-mconstant-gp|-mauto-pic]
[-milp32|-milp64|-mlp64|-mp64]
[-mle|mbe]
[-mtune=itanium1|-mtune=itanium2]
[-munwind-check=warning|-munwind-check=error]
[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
[-x|-xexplicit] [-xauto] [-xdebug]

🐚 Target IP2K options 🐚

[-mip2022|-mip2022ext]

🪩 Target M32C options 🪩

[-m32c|-m16c] [-relax] [-h-tick-hex]

🎐 Target M32R options 🎐

[--m32rx|--[no-]warn-explicit-parallel-conflicts|
--W[n]p]

👑 Target M680X0 options 👑

[-l] [-m68000|-m68010|-m68020|...]

💎 Target M68HC11 options 💎

[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branches] [--short-branches]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]

🧊 Target MCORE options 🧊

[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]

🌙 Target Meta options 🌙

[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu]

🪐 Target MICROBLAZE options 🪐

[-mlittle-endian] [-mbig-endian]

🌺 Target MIPS options 🌺

[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot [-mvxworks-pic]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-mfp64] [-mgp64] [-mfpxx]
[-modd-spreg] [-mno-odd-spreg]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
[-mips64r3] [-mips64r5] [-mips64r6]
[-construct-floats] [-no-construct-floats]
[-mignore-branch-isa] [-mno-ignore-branch-isa]
[-mnan=encoding]
[-trap] [-no-break] [-break] [-no-trap]
[-mips16] [-no-mips16]
[-mmips16e2] [-mno-mips16e2]
[-mmicromips] [-mno-micromips]
[-msmartmips] [-mno-smartmips]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdsp] [-mno-dsp]
[-mdspr2] [-mno-dspr2]
[-mdspr3] [-mno-dspr3]
[-mmsa] [-mno-msa]
[-mxpa] [-mno-xpa]
[-mmt] [-mno-mt]
[-mmcu] [-mno-mcu]
[-mcrc] [-mno-crc]
[-mginv] [-mno-ginv]
[-mloongson-mmi] [-mno-loongson-mmi]
[-mloongson-cam] [-mno-loongson-cam]
[-mloongson-ext] [-mno-loongson-ext]
[-mloongson-ext2] [-mno-loongson-ext2]
[-minsn32] [-mno-insn32]
[-mfix7000] [-mno-fix7000]
[-mfix-rm7000] [-mno-fix-rm7000]
[-mfix-vr4120] [-mno-fix-vr4120]
[-mfix-vr4130] [-mno-fix-vr4130]
[-mfix-r5900] [-mno-fix-r5900]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]

🦄 Target MMIX options 🦄

[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]

🌼 Target NDS32 options 🌼

[-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
[-misa=isa] [-mabi=abi] [-mall-ext]
[-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
[-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
[-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
[-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
[-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
[-mb2bb]

🍭 Target PDP11 options 🍭

[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]

🐰 Target picoJava options 🐰

[-mb|-me]

💥 Target PowerPC options 💥

[-a32|-a64]
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
[-many] [-maltivec|-mvsx|-mhtm|-mvle]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
[-nops=count]

🧃 Target PRU options 🧃

[-link-relax]
[-mnolink-relax]
[-mno-warn-regname-label]

🛼 Target RISC-V options 🛼

[-fpic|-fPIC|-fno-pic]
[-march=ISA|Profiles|Profiles_ISA]
[-mabi=ABI]
[-mlittle-endian|-mbig-endian]

🎠 Target RL78 options 🎠

[-mg10]
[-m32bit-doubles|-m64bit-doubles]

🪞 Target RX options 🪞

[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]

🧿 Target s390 options 🧿

[-m31|-m64] [-mesa|-mzarch] [-march=CPU]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]
[-mwarn-regtype-mismatch=strict
 -mwarn-regtype-mismatch=relaxed
 -mwarn-regtype-mismatch=no
 -mno-warn-regtype-mismatch]

🎡 Target SCORE options 🎡

[-EB][-EL][-FIXDD][-NWARN]
[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
[-march=score7][-march=score3]
[-USE_R1][-KPIC][-O0][-G num][-V]

🌞 Target SPARC options 🌞

[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
 -Asparcvisr|-Asparc5]
[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
 -bump]
[-32|-64]
[--enforce-aligned-data][--dcti-couples-detect]

🍬 Target TIC54X options 🍬

[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]

🎧 Target TIC6X options 🎧

[-march=arch] [-mbig-endian|-mlittle-endian]
[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
[-mpic|-mno-pic]

🧸 Target TILE-Gx options 🧸

[-m32|-m64][-EB][-EL]

🪩 Target Visium options 🪩

[-mtune=arch]

🦋 Target Xtensa options 🦋

[--[no-]text-section-literals] [--[no-]auto-litpools]
[--[no-]absolute-literals]
[--[no-]target-align] [--[no-]longcalls]
[--[no-]transform]
[--rename-section oldname=newname]
[--[no-]trampolines]
[--abi-windowed|--abi-call0]

🕹️ Target Z80 options 🕹️

[-march=CPU[-EXT][+EXT]]
[-local-prefix=PREFIX]
[-colonless]
[-sdcc]
[-fp-s=FORMAT]
[-fp-d=FORMAT]

and that's every target option in this part, bestie — the manual keeps going in part 2, so don't move 💅

💅 DESCRIPTION 💅

okay so GNU as is literally not just one assembler — it’s a whole family of assemblers 👑. If you’ve used the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called pseudo-ops) and assembler syntax. slay.

as is primarily intended to assemble the output of the GNU C compiler gcc for use by the linker ld. Nevertheless, we’ve tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly. This doesn’t mean as always uses the same syntax as another assembler for the same architecture; for example, we know of several incompatible versions of 680x0 assembly language syntax. not me finding out assembly syntax has beef with itself 😭.

Each time you run as it assembles exactly one source program. The source program is made up of one or more files. (The standard input is also a file.) bestie, even stdin counts 💖.

You give as a command line that has zero or more input file names. The input files are read (from left file name to right). A command-line argument (in any position) that has no special meaning is taken to be an input file name.

If you give as no file names it attempts to read one input file from the as standard input, which is normally your terminal. You may have to type ctl-D to tell as there is no more program to assemble.

Use -- if you need to explicitly name the standard input file in your command line.

If the source is empty, as produces a small, empty object file. tiny icon behavior 🎀.

as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly. so warnings are like “assuming bestie, go off” and errors are like “nope, we’re done here” 💀.

If you are invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the -Wa) by commas. For example:

gcc -c -g -O -Wa,-alh,-L file.c

This passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain internal symbols in the symbol table). periodt.

Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.) iykyk, -v is the nosy bestie that tells you everything 👀.

✨ OPTIONS ✨

@file — read command-line options from file. The options read are inserted in place of the original @file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed. Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively. it’s giving options inception 🌀.
-a[cdghilmns] — turn on listings, in any of a variety of ways:
- -ac — omit false conditionals
- -ad — omit debugging directives
- -ag — include general information, like as version and options passed
- -ah — include high-level source
- -al — include assembly
- -ali — include assembly with ginsn
- -am — include macro expansions
- -an — omit forms processing
- -as — include symbols
- =file — set the name of the listing file

You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls. combo moves, iconic 💅.

--alternate — begin in alternate macro mode.
--compress-debug-sections — compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities.

note: if compression would make a given section larger, then it is not compressed. no cap, it’s not gonna bloat things just to flex.

--compress-debug-sections=none — equivalent to --nocompress-debug-sections.
--compress-debug-sections=zlib — equivalent to --compress-debug-sections.
--compress-debug-sections=zlib-gnu — compresses DWARF debug sections using the obsoleted zlib-gnu format. The debug sections are renamed to begin with .zdebug.
--compress-debug-sections=zlib-gabi — equivalent to --compress-debug-sections.
--compress-debug-sections=zstd — compresses DWARF debug sections using zstd. Note: if compression would actually make a section larger, then it is not compressed nor renamed.
--nocompress-debug-sections — do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.
-D — enable debugging in target specific backends, if supported. Otherwise ignored. Even if ignored, this option is accepted for script compatibility with calls to other assemblers. fake it till you make it energy 🫶.
--debug-prefix-map old=new — when assembling files in directory old, record debugging information describing them as in new instead.
--defsym sym=value — define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a .set pseudo-op. math bestie hours 🔥.
--dump-config — displays how the assembler is configured and then exits.
--elf-stt-common=no — control whether the ELF assembler should generate common symbols with the STT_COMMON type; this sets it to no. The default can be controlled by a configure option --enable-elf-stt-common.
--elf-stt-common=yes — control whether the ELF assembler should generate common symbols with the STT_COMMON type; this sets it to yes. The default can be controlled by a configure option --enable-elf-stt-common.
--emit-local-absolute — emit even pre-defined (local) absolute symbols to the outgoing symbol table. Note that this isn’t the exact opposite of --strip-local-absolute. not exactly twin flames, more like distant cousins 💜.
--emulation=name — if the assembler is configured to support multiple different target configurations then this option can be used to select the desired form.
-f — “fast” — skip whitespace and comment preprocessing (assume source is compiler output). lowkey speedrun mode ⭐.
-g, --gen-debug — generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a .debug_info and .debug_line section is only emitted when the assembly file doesn’t generate one itself.
--gstabs — generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
--gstabs+ — generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code.

currently the only GNU extension is the location of the current working directory at assembling time. your fave is problem-coded for other debuggers 😭💀

--gdwarf-2 — generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.

note — this option is only supported by some targets, not all of them.

--gdwarf-3 — same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification.

note: enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis. it’s giving “maybe, depends on the target’s mood” 🦋

--gdwarf-4 — same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification.

note: enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis.

--gdwarf-5 — same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification.

note: enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis.

--gdwarf-sections — instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. For example a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. If the code section is just called .text then debug line section will still be called just .debug_line without any suffix. organized bestie behavior 🎀.
--gdwarf-cie-version=version — control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specified the default is version 1, though some targets can modify this default. Other possible values for version are 3 or 4.
--generate-missing-build-notes=yes — control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources; this sets it to yes. The default can be controlled by the --enable-generate-build-notes configure option.
--generate-missing-build-notes=no — control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources; this sets it to no. The default can be controlled by the --enable-generate-build-notes configure option.
--gsframe — create .sframe section from CFI directives. (yes, the original lists --gsframe twice — we’re keeping the twin energy 👯). The default can be controlled by a configure option --enable-default-sframe. The current version of the emitted SFrame stack trace data is SFRAME_VERSION_3.
--gsframe=no — generation can be suppressed with this. no sframe for you 🙈.
--gsframe=yes — the explicit yes option behaves the same as --gsframe.
--gsframe-3 — generate SFrame stack trace information as per Version 3 of the specification.
--hash-size N — ignored. Supported for command line compatibility with other assemblers. it’s literally just here to be polite 💅.
--help — print a summary of the command-line options and exit.
--target-help — prints a summary of all target specific options and exits. That’s it, bestie. 💅
--info — don’t suppress informational messages. Let the little updates breathe. ✨
--no-info — suppress informational messages. Quiet mode activated. 🤫
-I dir — adds directory dir to the search list for .include directives. Your include girlie is found. 🎀
-J — don’t warn about signed overflow. Lowkey chill about it. 😌
-K — issue warnings when difference tables are altered for long displacements. Heads up energy. ⚠️
-L, --keep-locals — keep internal symbols in the symbol table. These symbols start with system-specific local label prefixes, typically .L for ELF systems or L for traditional a.out systems. Protect the locals! 🫶
--listing-lhs-width=number — sets the maximum width, in words, of the output data column for an assembler listing to number. Listing glow-up. ✨
--listing-lhs-width2=number — sets the maximum width, in words, of the output data column for continuation lines in an assembler listing to number. Continuation lines ate. 💅
--listing-rhs-width=number — sets the maximum width of an input source line, as displayed in a listing, to number bytes. Input line, but make it fit. 🎀
--listing-cont-lines=number — sets the maximum number of lines printed in a listing for a single line of input to number + 1. Yes, plus one. Math girlie. 🧮
--multibyte-handling=allow, --multibyte-handling=warn, --multibyte-handling=warn-sym-only, --multibyte-handling=warn_sym_only — controls how the assembler handles multibyte characters in the input. The default (which can be restored by using the allow argument) is to allow such characters without complaint. Using the warn argument makes the assembler generate a warning message whenever any multibyte character is encountered. Using the warn-sym-only argument only causes a warning when a symbol is defined with a name that contains multibyte characters. (References to undefined symbols will not generate a warning.) Multibyte bestie behavior check. 🌈
--no-pad-sections — stops the assembler from padding the ends of output sections to the alignment of that section. The default is to pad the sections, but this can waste space which might be needed on targets which have tight memory constraints. No extra padding, no extra stress. 💀
-o objfile — names the object-file output from as objfile. Name your output, bestie. 🏷️
-R — folds the data section into the text section. Merging the vibes. 🌀
--reduce-memory-overheads — ignored. Supported for compatibility with tools that pass the same option to both the assembler and the linker. It’s giving “I’m here but I’m not doing anything.” 🙈
--reloc-section-sym=all, --reloc-section-sym=internal, --reloc-section-sym=none — control whether relocations referencing local binding symbols are adjusted to use section symbols instead. With all (the default), relocations against all eligible local binding symbols are converted. With internal, only relocations against internal labels (symbols matching the .L prefix) are converted. With none, no such conversions are performed. Pick your relocation main character. 👑
--scfi=experimental — controls whether the assembler should synthesize CFI for hand-written input. If the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning. Note that --scfi=experimental is not intended to be used for compiler-generated code, including inline assembly. This experimental support is work in progress. Only System V AMD64 ABI is supported. Experimental era, handle with care. 🧪
- Each input function in assembly must begin with the .type directive, and should ideally be closed off using a .size directive.
- When using SCFI, each .type directive prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry).
- This implies that with each .type directive, a previous block of instructions, if any, is finalised as a distinct FDE.
--sectname-subst — honor substitution sequences in section names. Section names get the substitution treatment. 🪄
--size-check=error, --size-check=warning — issue an error or warning for invalid ELF .size directive. Size check, but make it dramatic. 😭
--statistics — prints the maximum space (in bytes) and total time (in seconds) used by assembly. Receipts! 🧾
--strip-local-absolute — removes local absolute symbols from the outgoing symbol table. Bye-bye, local absolutes. 👋
-v, --verbose — prints the as version. Say hi to the version. 🌸
--version, -version — prints the as version and exits. Version reveal, then peace out. 💖
-W, --no-warn — suppress warning messages. Shhh. 🤫
--warn — don’t suppress warning messages or treat them as errors. Let the warnings speak. 🗣️
--fatal-warnings — treats warnings as errors. Warning girlies are now errors, periodt. 🔥
-w — ignored. Literally ignored. 💀
-x — ignored. Also ignored. 🙈
-Z — generates an object file even after errors. Messy but still producing. 😭
-- | files ... — standard input, or source files to assemble. Feed the assembler, bestie. 🍓

The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). AArch64 era, let’s go! 🦋

-EB — this option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. Big-endian moment. 🌍
-EL — this option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. Little-endian moment. 🌱
-mabi=abi — specifies which ABI the source code uses. The recognized arguments are: "ilp32" and "lp64", which decide the generated object file in ELF32 and ELF64 format respectively. The default is "lp64". ABI check, bestie. ✅
-mcpu=processor[+extension...] — specifies the target processor. The assembler issues an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: "cortex-a34", "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73", "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77", "cortex-a78", "cortex-a78ae", "cortex-a78c", "cortex-a510", "cortex-a520", "cortex-a710", "cortex-a720", "ares", "exynos-m1", "falkor", "neoverse-n1", "neoverse-n2", "neoverse-e1", "neoverse-v1", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1" "xgene2", "cortex-r82", "cortex-x1", "cortex-x2", "cortex-x3", and "cortex-x4". The special name "all" may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions.
- In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.
- If some implementations of a particular processor can have an extension, then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions.
-march=architecture[+extension...] — specifies the target architecture. The assembler issues an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: "armv8-a", "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a", "armv8.6-a", "armv8.7-a", "armv8.8-a", "armv8.9-a", "armv8-r", "armv9-a", "armv9.1-a", "armv9.2-a", "armv9.3-a", "armv9.4-a" and "armv9.5-a".
- If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assembler will default to -mcpu=all.
- The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu, extensions are not always enabled by default.
-mbig-obj — on PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. Big object energy. 🫧
-mverbose-error — this option enables verbose error messages for AArch64 gas. This option is enabled by default. Verbose errors, but make it default. 💅
-mno-verbose-error — this option disables verbose error messages in AArch64 gas. Less yapping from errors. 🤐
-menable-sysreg-checking — this option enables error messages that are issued if an attempt is made to assemble a system register access which will not execute on the target architecture. System register vibe check. 🔍

The following options are available when as is configured for an Alpha processor. Alpha era, retro icon behavior. 🧚

-mcpu — specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the .arch directive.
- The following processor names are recognized: 21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6", "ev67", "ev68". The special name "all" may be used to allow the assembler to accept instructions valid for any Alpha processor.
- In order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. "ev4") do not.
-mdebug, -no-mdebug — enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. The default is to automatically enable .mdebug when the first stabs directive is seen. Debug encapsulation sorted. 🎀
-relax — this option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications. Relax, but with relocations. 😌
-replace, -noreplace — enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets and -replace is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual. VMS-specific behavior, iykyk. 📘
-g — this option is used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect. Debug info mode. 🐛
-Gsize — a local common symbol larger than size is placed in .bss, while smaller symbols are placed in .sbss. Size-based placement, literally. 📏
-F, -32addr — these options are ignored for backward compatibility. Old vibes, ignored. 🫠

The following options are available when as is configured for an ARC processor. ARC era, cute little processor moment. 🌿

-mcpu=cpu — this option selects the core processor variant. Pick your core. 🎯
-EB | -EL — select either big-endian (-EB) or little-endian (-EL) output. Endian choice, bestie. 🌗
-mcode-density — enable Code Density extension instructions. Density, but make it code. 🧩

okay bestie, buckle up 💖 because now we're getting into the per-processor era of this page and it's a lot. no notes, just vibes and a truly unhinged number of flags. let's go 🫶

🌸 ARM o'clock 🌸

the following options are available when as is configured for the ARM processor family. yes, all of them. yes, you need them.

-mcpu=processor[+extension...] — tells the assembler which ARM processor variant is the target. the +extension... bit is a whole thing, it's giving "add-ons," and it's yours to use.
-march=architecture[+extension...] — specifies which ARM architecture variant the target uses. slightly different from -mcpu, don't ask me to explain it in a text, just know it's the architecture one ✨
-mfpu=floating-point-format — picks which Floating Point architecture is the target, aka the floaty math situation 💅
-mfloat-abi=abi — selects which floating point ABI is in use. so like, how the floats get passed around. very "who's carrying the tray" energy.
-mthumb — enables Thumb only instruction decoding. thumb. just thumb. iconic 🎀
-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant — select which procedure calling convention is in use. four little options, one big decision 😌
-EB | -EL — select either big-endian (-EB) or little-endian (-EL) output. pick your endianness, bestie, but pick it consciously 🌈
-mthumb-interwork — specifies that the code has been generated with interworking between Thumb and ARM code in mind 🤝 literally the friendship bracelet of options
-mccs — turns on CodeComposer Studio assembly syntax compatibility mode. slay for the CCS girlies 💜
-k — specify that PIC code has been generated. yes, it's just -k. no, you don't have to explain yourself.

🦋 Blackfin bestie 🦋

the following options are available when as is configured for the Blackfin processor family.

-mcpu=processor[-sirevision] — this one specifies the target processor. here's the tea: the optional sirevision is not used in the assembler. it's literally only there so GCC can easily pass down its -mcpu= option. so it's a courtesy seat at the table 🪑 the assembler will issue an error message if you try to assemble an instruction that won't execute on the target processor. so yeah, it will tell you. loudly. 😭

the processor names it recognizes are: "bf504", "bf506", "bf512", "bf514", "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526", "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not implemented yet 🫣), "bf536", "bf537", "bf538", "bf539", "bf542", "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m", "bf549", "bf549m", "bf561", and "bf592". that's the whole roll call, no cap.

-mfdpic — assemble for the FDPIC ABI. go off 👑
-mno-fdpic and -mnopic — disable -mfdpic. two names, one job, we love a duo 💅

🐝 BPF (the Linux kernel one) 🐝

the following options are available when as is configured for the Linux kernel BPF processor family.

@chapter BPF Dependent Features

BPF Options

-EB — this option specifies that the assembler should emit big-endian eBPF.
-EL — this option specifies that the assembler should emit little-endian eBPF. pick a lane babes ✨
-mdialect=dialect — this option specifies the assembly language dialect to recognize while assembling. the assembler supports normal and pseudoc. that's it, that's the dialect menu 🍓
-misa-spec=spec — this option specifies the version of the BPF instruction set to use when assembling. the BPF ISA versions supported are v1 v2, v3 and v4. (yes, that comma is doing something weird, i'm just the messenger 💀)

the value xbpf can be specified to recognize extra instructions that are used by GCC for testing purposes. but beware — this is not valid BPF. ⚠️ so like, do not ship it, bestie. it's a test-only situation fr fr.

-mno-relax — this option tells the assembler to not relax instructions. no relaxing. no chill. no napping on the job 😤

note that if no endianness option is specified in the command line, the host endianness is used. see the info pages for documentation of the CRIS-specific options. 🧚

🎀 C-SKY cutie 🎀

the following options are available when as is configured for the C-SKY processor family. this section is long, hydrate first 🥤

-march=archname — assemble for architecture archname. the --help option lists valid values for archname, so go look, it's right there 👀
-mcpu=cpuname — assemble for architecture cpuname. yes, the page says "architecture" here too. and again, --help lists valid values for cpuname. king of pointing you at the help flag 👑
-EL and -mlittle-endian — generate little-endian output.
-EB and -mbig-endian — generate big-endian output.
-fpic and -pic — generate position-independent code. both spellings, same slay 💅
-mljump and -mno-ljump — enable/disable transformation of the short branch instructions "jbf", "jbt", and "jbr" to "jmpi". this option is for V2 processors only. it is ignored on CK801 and CK802 targets, which do not support the "jmpi" instruction, and is enabled by default for other processors.
-mbranch-stub and -mno-branch-stub — pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr" instructions to the linker.

this option is only available for bare-metal C-SKY V2 ELF targets, where it is enabled by default. it cannot be used in code that will be dynamically linked against shared libraries. so like, know your target, bestie 🫣

-force2bsr, -mforce2bsr, -no-force2bsr, -mno-force2bsr — enable/disable transformation of "jbsr" instructions to "bsr". this option is always enabled (and -mno-force2bsr is ignored) for CK801/CK802 targets. it is also always enabled when -mbranch-stub is in effect. so yeah, sometimes the off switch is decorative 💀
-jsri2bsr, -mjsri2bsr, -no-jsri2bsr, -mno-jsri2bsr — enable/disable transformation of "jsri" instructions to "bsr". this option is enabled by default.
-mnolrw and -mno-lrw — enable/disable transformation of "lrw" instructions into a "movih"/"ori" pair. two options, one instruction glow-up ✨
-melrw and -mno-elrw — enable/disable extended "lrw" instructions. this option is enabled by default for CK800-series processors.
-mlaf, -mliterals-after-func, -mno-laf, -mno-literals-after-func — enable/disable placement of literal pools after each function. four flags, one literal-pool placement question 🏊
-mlabr, -mliterals-after-br, -mno-labr, -mnoliterals-after-br — enable/disable placement of literal pools after unconditional branches. this option is enabled by default. (and yes, note the second "no" spelling is -mnoliterals-after-br, no hyphen, that's not a typo, that's the manpage 🌸)
-mistack and -mno-istack — enable/disable interrupt stack instructions. this option is enabled by default on CK801, CK802, and CK802 processors. (that's what it says, bestie. two CK802s. i don't make the rules 😭)

✨ the optional-instruction squad ✨

the following options explicitly enable certain optional instructions. these features are also enabled implicitly by using -mcpu= to specify a processor that supports it. so like, they can turn on by themselves, but you can also just ask 💅

-mhard-float — enable hard float instructions.
-mmp — enable multiprocessor instructions.
-mcp — enable coprocessor instructions.
-mcache — enable cache prefetch instruction.
-msecurity — enable C-SKY security instructions.
-mtrust — enable C-SKY trust instructions.
-mdsp — enable DSP instructions.
-medsp — enable enhanced DSP instructions.
-mvdsp — enable vector DSP instructions. vector DSP. that's the final boss 🐉

🧚 Epiphany era 🧚

the following options are available when as is configured for an Epiphany processor.

-mepiphany — specifies that both 32 and 16 bit instructions are allowed. this is the default behavior. so it's the "you're already doing it" option 💖
-mepiphany16 — restricts the permitted instructions to just the 16 bit set. tiny instructions only. small but mighty 🐜

💜 H8/300 hours 💜

the following options are available when as is configured for an H8/300 processor.

@chapter H8/300 Dependent Features

Options

the Renesas H8/300 version of "as" has one machine-dependent option... and then the page immediately gives you two things. we love consistency 🫠

-h-tick-hex — support H'00 style hex constants in addition to 0x00 style. both styles, living in harmony 🕊️
-mach=name — sets the H8300 machine variant. the following machine names are recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and "h8300sxn". spell it -mach, not -march, that's the whole gag 💀

🔥 i386 i guess 🔥

the following options are available when as is configured for an i386 processor. main character energy, honestly 👑

--32 | --x32 | --64 — select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively. get it? --x32 is x86-64 with 32-bit words. confusing? yes. iconic? also yes 😌

these options are only available with the ELF object file format, and they require that the necessary BFD support has been included. (on a 32-bit platform you have to add --enable-64-bit-bfd to configure to enable 64-bit usage and use x86-64 as target platform.) so like, if it's not working, it's probably a configure thing 🫶

-n — by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. this switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment. so: -n means "no, respect my 0x90" 💅
--divide — on SVR4-derived platforms, the character / is treated as a comment character, which means it cannot be used in expressions. the --divide option turns / into a normal character. this does not disable / at the beginning of a line starting a comment, and it does not affect using # for starting a comment. so / gets to be a math girl again, but only where it's allowed 🍓
-march=CPU[+EXTENSION...] — this option specifies the target processor. the assembler will issue an error message if you attempt to assemble an instruction which will not execute on the target processor. the following processor names are recognized: "i8086", "i186", "i286", "i386", "i486", "i586", "i686", "pentium", "pentiumpro", "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona", "core", "core2", "corei7", "iamcu", "k6", "k6_2", "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2", "bdver3", "bdver4", "znver1", "znver2", "znver3", "znver4", "znver5", "znver6", "btver1", "btver2", "generic32" and "generic64". that's the full roster, no substitutions 👯‍♀️

and that's where part 4 leaves us, bestie — more coming, don't you dare close the tab 🌈

Okay so real talk — the assembler doesn't just do the base instruction set, bestie. You can tell it to accept a whole bunch of extension mnemonics too ✨. For example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. The extensions currently supported are: 8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, avx512_bmm, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb, avx10.1, avx10.1/512, avx10.1/256, avx10.1/128, user_msr, msr_imm, apx_f, apx_nci, apx_ndd, apx_nf, apx_nci_ndd_nf, avx10.2, avx10.2/512, avx10.2/256, avx10.2/128, movrs, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8, amx_movrs, amx_avx512, amx_tile, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, snp, invlpgb, tlbsync, rmpquery, rmpread, svme, gmism2, gmiccs, padlockrng2, padlockphe2, padlockxmodx and padlock. 😮‍💨 yeah that's a lot, hydrate.

Heads up tho: you can slap a no in front of any of those extension mnemonics to revoke the respective (and any dependent) functionality. Flip side, bestie — the suffixes allowed on -march=avx10.<N> enforce a vector length restriction. Like, despite these otherwise being "enabling" options, using those suffixes will disable all insns with wider vector or mask register operands. Ironic? A little. Iconic? Absolutely. 💀

And when the .arch directive gets used together with -march, the .arch directive takes precedent. Periodt. 👑

-mtune=CPU — picks a processor to optimize for. When you pair it with the -march option, only instructions of the processor specified by the -march option get generated. The valid CPU values are identical to the processor list of -march=CPU. 🎯
-moperand-check=none, -moperand-check=warning, -moperand-check=error — these control whether the assembler checks certain instruction operands or operand combinations. Think of an example instruction where the operand size can't be inferred from its operands and also hasn't been specified by way of an instruction suffix — yeah, that vibe. -moperand-check=none means no checks at all. -moperand-check=warning means it warns you when the checks fail, and that's the default. -moperand-check=error means it straight-up errors when the checks fail. 🚨
-msse2avx — tells the assembler to encode SSE instructions with a VEX prefix, which requires AVX to be available. And SSE instructions using extended GPRs get encoded with an EVEX prefix, which requires AVX512 or AVX10 to be available. Fancy ✨
-muse-unaligned-vector-move — tells the assembler to encode an aligned vector move as an unaligned vector move. Living on the edge, love that for us 🦋
-msse-check=none, -msse-check=warning, -msse-check=error — these control whether the assembler checks SSE instructions. -msse-check=none makes it not check SSE instructions, and that's the default. -msse-check=warning makes it issue a warning for any SSE instruction. -msse-check=error makes it issue an error for any SSE instruction. 💅
-mavxscalar=128, -mavxscalar=256 — control how the assembler encodes scalar AVX instructions. -mavxscalar=128 encodes scalar AVX instructions with 128bit vector length, and that's the default. -mavxscalar=256 encodes them with 256bit vector length.

⚠️ WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. Like, fr fr, don't. 😭

-mvexwig=0, -mvexwig=1 — control how the assembler encodes VEX.W-ignored (WIG) VEX instructions. -mvexwig=0 encodes WIG VEX instructions with vex.w = 0, which is the default. -mvexwig=1 encodes WIG EVEX instructions with vex.w = 1.

⚠️ WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. This is a no-notes situation, bestie 🙈

-mevexlig=128, -mevexlig=256, -mevexlig=512 — control how the assembler encodes length-ignored (LIG) EVEX instructions. -mevexlig=128 encodes LIG EVEX instructions with 128bit vector length, which is the default. -mevexlig=256 and -mevexlig=512 encode LIG EVEX instructions with 256bit and 512bit vector length, respectively. 🌈
-mevexwig=0, -mevexwig=1 — control how the assembler encodes w-ignored (WIG) EVEX instructions. -mevexwig=0 encodes WIG EVEX instructions with evex.w = 0, which is the default. -mevexwig=1 encodes WIG EVEX instructions with evex.w = 1. 👑
-mmnemonic=att, -mmnemonic=intel — specifies the instruction mnemonic used for matching instructions. The .att_mnemonic and .intel_mnemonic directives will take precedent. 💫
-msyntax=att, -msyntax=intel — specifies the instruction syntax used when processing instructions. The .att_syntax and .intel_syntax directives will take precedent. 🎀
-mnaked-reg — says registers don't require a % prefix. The .att_syntax and .intel_syntax directives will take precedent. Naked registers, scandalous 🫣
-madd-bnd-prefix — forces the assembler to add a BND prefix to all branches, even if that prefix wasn't explicitly written in the source code. It's giving "I do what I want" 💅
-mno-shared — on ELF targets, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The -mshared option tells the assembler to generate code that may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger 😔. This option only affects the handling of branch instructions.
-mbig-obj — on PE/COFF targets this forces the use of the big object file format, which allows more than 32768 sections. Big object energy 🔥
-momit-lock-prefix=no, -momit-lock-prefix=yes — control how the assembler encodes the lock prefix. This one is intended as a workaround for processors that fail on the lock prefix. It can only be safely used with single-core, single-thread computers — -momit-lock-prefix=yes omits all lock prefixes. -momit-lock-prefix=no encodes the lock prefix as usual, which is the default. Seriously, single-core single-thread only, bestie 🫶
-mfence-as-lock-add=no, -mfence-as-lock-add=yes — control how the assembler encodes lfence, mfence and sfence. -mfence-as-lock-add=yes encodes lfence, mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no encodes lfence, mfence and sfence as usual, which is the default.
-mrelax-relocations=no, -mrelax-relocations=yes — control whether the assembler generates relax relocations: R_386_GOT32X in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX in 64-bit mode. -mrelax-relocations=yes generates them. -mrelax-relocations=no doesn't. Simple as 🌸
-mtls-check=no, -mtls-check=yes — control whether the assembler checks tls relocation. -mtls-check=yes checks tls relocation. -mtls-check=no doesn't check tls relocation. The default can be controlled by a configure option --enable-x86-tls-check. 🔍
-malign-branch-boundary=NUM — controls how the assembler aligns branches with segment prefixes or NOP. NUM must be a power of 2, and it should be 0 or no less than 16. Branches get aligned within a NUM byte boundary. -malign-branch-boundary=0, which is the default, doesn't align branches at all. 🎯
-malign-branch=TYPE[+TYPE...] — specifies the types of branches to align. TYPE is a combination of jcc (aligns conditional jumps), fused (aligns fused conditional jumps), jmp (aligns unconditional jumps), call (aligns calls), ret (aligns rets), and indirect (aligns indirect jumps and calls). The default is -malign-branch=jcc+fused+jmp. Mix and match, slay 💅
-malign-branch-prefix-size=NUM — specifies the maximum number of prefixes on an instruction to align branches. NUM should be between 0 and 5, and the default NUM is 5. ✨
-mbranches-within-32B-boundaries — aligns conditional jumps, fused conditional jumps and unconditional jumps within a 32 byte boundary with up to 5 segment prefixes on an instruction. It's equivalent to:

-malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5

The default doesn't align branches. Convenient little shortcut, iykyk 🎀

-mlfence-after-load=no, -mlfence-after-load=yes — control whether the assembler generates lfence after load instructions. -mlfence-after-load=yes generates lfence. -mlfence-after-load=no doesn't generate lfence, which is the default. 🦋
-mlfence-before-indirect-branch=none — no lfence, no warning. This is the default, bestie.
-mlfence-before-indirect-branch=all — generates lfence before indirect near branch via register, and issues a warning before indirect near branch via memory. It also implicitly sets -mlfence-before-ret=shl when there's no explicit -mlfence-before-ret= on the command line. Sneaky combo deal 💅
-mlfence-before-indirect-branch=register — generates lfence before indirect near branch via register only.
-mlfence-before-indirect-branch=memory — issues a warning before indirect near branch via memory only.

Heads up 🫶: lfence won't be generated before an indirect near branch via register when you've got -mlfence-after-load=yes going, because in that case the lfence gets generated after loading the branch target register. Different placement, same idea.

All four of those live under one umbrella: they control whether the assembler should generate lfence before indirect near branch instructions. Very much a "pick your fighter" situation.

Now the ret flavour, same energy:

-mlfence-before-ret=none — won't generate lfence. This is the default.
-mlfence-before-ret=shl — generates shl instruction with lfence.
-mlfence-before-ret=or — generates or instruction with lfence.
-mlfence-before-ret=yes — generates shl instruction with lfence (same deal as shl).
-mlfence-before-ret=not — generates not instruction with lfence.

All of these control whether the assembler should generate lfence before ret. ✨

-mx86-used-note=no, -mx86-used-note=yes — controls whether the assembler should generate GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes. The default is whatever the --enable-x86-used-note configure option said, so iykyk 🌸

-mevexrcig=rne — encodes the RC bits of SAE-only EVEX instructions with 00. This is the default.
-mevexrcig=rd — encodes SAE-only EVEX instructions with 01 RC bits.
-mevexrcig=ru — encodes SAE-only EVEX instructions with 10 RC bits.
-mevexrcig=rz — encodes SAE-only EVEX instructions with 11 RC bits.

Collectively: these control how the assembler should encode SAE-only EVEX instructions. 🦋

-mamd64 — the assembler accepts only AMD64 ISA in 64-bit mode.
-mintel64 — the assembler accepts only Intel64 ISA in 64-bit mode.

Default (neither flag) = accept common, Intel64 only and AMD64 ISAs. Equal opportunity crown 👑

-O0 — turns off the optimization described below.
-O, -O1 — encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bit immediates; encode 64-bit register clearing instructions with 32-bit register clearing instructions; encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions; encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions; and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical.
-O2 — everything -O1 does, plus encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions. And in 64-bit mode, VEX encoded instructions with commutative source operands will also have their source operands swapped if that allows using the 2-byte VEX prefix form instead of the 3-byte one. Certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST. Lowkey genius ✨
-Os — everything -O2 does, plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate.

The whole point of this family: optimize instruction encoding with smaller instruction size. Shrinking is the vibe 💅

The following options are available when `as` is configured for the Ubicom IP2K series.

-mip2022ext — specifies that the extended IP2022 instructions are allowed.
-mip2022 — restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones.

The following options are available when `as` is configured for the Renesas M32C and M16C processors.

-m32c — assemble M32C instructions.
-m16c — assemble M16C instructions. (this one's the default 🎀)
-relax — enable support for link-time relaxations.
-h-tick-hex — supports H'00 style hex constants in addition to 0x00 style.

The following options are available when `as` is configured for the Renesas M32R (formerly Mitsubishi M32R) series.

--m32rx — specifies which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.
--warn-explicit-parallel-conflicts or --Wp — produce warning messages when questionable parallel constructs are encountered.
--no-warn-explicit-parallel-conflicts or --Wnp — do not produce warning messages when questionable parallel constructs are encountered.

The following options are available when `as` is configured for the Motorola 68000 series.

-l — shorten references to undefined symbols, to one word instead of two.
-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 — specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time. That's a lot of siblings 😭
-m68881 | -m68882 | -mno-68881 | -mno-68882 — the target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor. Chaos combo, but valid 🌀
-m68851 | -mno-68851 — the target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up.

For details about the PDP-11 machine dependent features options, see PDP-11-Options.

-mpic | -mno-pic — generate position-independent (or position-dependent) code. The default is -mpic.
-mall, -mall-extensions — enable all instruction set extensions. This is the default. ✨
-mno-extensions — disable all instruction set extensions.
-mextension | -mno-extension — enable (or disable) a particular instruction set extension.
-mcpu — enable the instruction set extensions supported by a particular CPU, and disable all other extensions.
-mmachine — enable the instruction set extensions supported by a particular machine model, and disable all other extensions.

The following options are available when `as` is configured for a picoJava processor.

-mb — generate "big endian" format output.
-ml — generate "little endian" format output.

The following options are available when `as` is configured for a PRU processor.

-mlink-relax — assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LD would shorten the LDI32 instruction to a single LDI. In such case as will output DIFF relocations for diff expressions.
-mno-link-relax — assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted.
-mno-warn-regname-label — do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off.
*-mcore-revision=revision* — specifies the PRU core revision to assemble for. Recognized revisions: "V1", "V2", "V3" and "V4". The assembler defaults to "V3".

The following options are available when `as` is configured for a MIPS processor.

-G num — sets the largest size of an object that can be referenced implicitly with the "gp" register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
-EB — generate "big endian" format output.
-EL — generate "little endian" format output.

Ok so the ISA-level squad, all generating code for a particular MIPS Instruction Set Architecture level — buckle up bestie, there's sixteen of them 🎀:

-mips1 — alias for -march=r3000.
-mips2 — alias for -march=r6000.
-mips3 — alias for -march=r4000.
-mips4 — alias for -march=r8000.
-mips5 — generic MIPS V ISA processor.
-mips32 — generic MIPS32 ISA processor.
-mips32r2 — MIPS32 Release 2 ISA processor.
-mips32r3 — MIPS32 Release 3 ISA processor.
-mips32r5 — MIPS32 Release 5 ISA processor.
-mips32r6 — MIPS32 Release 6 ISA processor.
-mips64 — generic MIPS64 ISA processor.
-mips64r2 — MIPS64 Release 2 ISA processor.
-mips64r3 — MIPS64 Release 3 ISA processor.
-mips64r5 — MIPS64 Release 5 ISA processor.
-mips64r6 — MIPS64 Release 6 ISA processor.
-march=cpu — generate code for a particular MIPS CPU.
-mtune=cpu — schedule and tune for a particular MIPS CPU.
-mfix7000 | -mno-fix7000 — cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
-mfix-rm7000 | -mno-fix-rm7000 — cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.
-mfix-r5900 | -mno-fix-r5900 — do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer, and always schedule a "nop" instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. 💀 real hardware tea
-mdebug | -no-mdebug — cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections.
-mpdr | -mno-pdr — control generation of ".pdr" sections.
-mgp32 | -mfp32 — the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.
-mgp64, -mfp64 — so normally the register sizes are just inferred from the ISA and ABI, right? These two force it. -mgp64 says "general-purpose registers are 64 bits wide at all times" and -mfp64 says the same for the floating-point registers. No vibes-based inference, just vibes-based certainty 💅
-mfpxx — paired up with -mabi=32, this unlocks an ABI variant that plays nice with floating-point registers that are either 32 or 64 bits wide. Very "will get along with everyone" of it 🫶
-modd-spreg, -mno-odd-spreg — lets you do float ops on odd-numbered single-precision registers, when the ISA supports it. Heads up though: -mfpxx implies -mno-odd-spreg. Otherwise the default is -modd-spreg. Odd registers stay booked and busy 🔥
-mips16, -no-mips16 — generates code for the MIPS 16 processor. Same energy as dropping .module mips16 at the top of your assembly file. -no-mips16 turns it back off (yes, that one really is spelled without the m, no I'm not fixing it ✨)
-mmips16e2, -mno-mips16e2 — turns on MIPS16e2 instructions while you're in MIPS16 mode. Equivalent to .module mips16e2 at the start of the assembly file. -mno-mips16e2 shuts that door. 🎀
-mmicromips, -mno-micromips — generates code for the microMIPS processor, like putting .module micromips at the top of the assembly file. -mno-micromips turns it off, and it's equivalent to putting .module nomicromips at the start of the assembly file. Tiny but mighty 🐜
-msmartmips, -mno-smartmips — enables the SmartMIPS extension to the MIPS32 instruction set. Same as .module smartmips at the top of the assembly file. -mno-smartmips turns it off. It's giving "honors student" fr 📚
-mips3d, -no-mips3d — generates code for the MIPS-3D Application Specific Extension. Basically telling the assembler "hey, accept MIPS-3D instructions." -no-mips3d turns it off. 3D glasses on 🕶️
-mdmx, -no-mdmx — generates code for the MDMX Application Specific Extension, which tells the assembler to accept MDMX instructions. -no-mdmx turns it off.
-mdsp, -mno-dsp — generates code for the DSP Release 1 Application Specific Extension so the assembler accepts DSP Release 1 instructions. -mno-dsp turns it off. 🎛️
-mdspr2, -mno-dspr2 — DSP Release 2 Application Specific Extension. Lowkey a package deal: this option implies -mdsp. Assembler accepts DSP Release 2 instructions. -mno-dspr2 turns it off.
-mdspr3, -mno-dspr3 — DSP Release 3 Application Specific Extension, and this one implies both -mdsp and -mdspr2. Assembler accepts DSP Release 3 instructions. -mno-dspr3 turns it off. The whole friend group showed up 💜
-mmsa, -mno-msa — generates code for the MIPS SIMD Architecture Extension, telling the assembler to accept MSA instructions. -mno-msa turns it off.
-mxpa, -mno-xpa — generates code for the MIPS eXtended Physical Address (XPA) Extension, so the assembler accepts XPA instructions. -mno-xpa turns it off.
-mmt, -mno-mt — generates code for the MT Application Specific Extension, telling the assembler to accept MT instructions. -mno-mt turns it off.
-mmcu, -mno-mcu — generates code for the MCU Application Specific Extension, so the assembler accepts MCU instructions. -mno-mcu turns it off.
-mcrc, -mno-crc — generates code for the MIPS cyclic redundancy check (CRC) Application Specific Extension, telling the assembler to accept CRC instructions. -mno-crc turns it off. Checking those bits, respectfully 🧐
-mginv, -mno-ginv — generates code for the Global INValidate (GINV) Application Specific Extension, so the assembler accepts GINV instructions. -mno-ginv turns it off.
-mloongson-mmi, -mno-loongson-mmi — generates code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension, telling the assembler to accept MMI instructions. -mno-loongson-mmi turns it off. 🎨
-mloongson-cam, -mno-loongson-cam — generates code for the Loongson Content Address Memory (CAM) instructions, so the assembler accepts Loongson CAM instructions. -mno-loongson-cam turns it off.
-mloongson-ext, -mno-loongson-ext — generates code for the Loongson EXTensions (EXT) instructions, telling the assembler to accept Loongson EXT instructions. -mno-loongson-ext turns it off.
-mloongson-ext2, -mno-loongson-ext2 — generates code for the Loongson EXTensions R2 (EXT2) instructions. This one implies -mloongson-ext, and it tells the assembler to accept Loongson EXT2 instructions. -mno-loongson-ext2 turns it off. Sequel era 🌸
-minsn32, -mno-insn32 — only use 32-bit instruction encodings when generating code for the microMIPS processor. It inhibits the use of any 16-bit instructions. Equivalent to .set insn32 at the top of the assembly file. -mno-insn32 turns it off, and that's equivalent to .set noinsn32 at the start of the assembly file. By default -mno-insn32 is selected, so all instructions are allowed. 🚪
--construct-floats, --no-construct-floats — --no-construct-floats disables building double-width floating point constants by loading the two halves of the value into the two single-width floating point registers that make up the double-width register. By default --construct-floats is selected, so constructing these floating point constants is allowed. 🧩
--relax-branch, --no-relax-branch — --relax-branch enables relaxation of out-of-range branches. By default --no-relax-branch is selected, which means any out-of-range branch throws an error. So like, chill by default? No. Not chill. 😭
-mignore-branch-isa, -mno-ignore-branch-isa — ignores branch checks for invalid transitions between ISA modes. Okay so the tea: branch semantics don't provide for an ISA mode switch, so in most cases the ISA mode a branch was encoded for has to match the ISA mode of the branch's target label. Because of that, GAS has checks built in that verify the two ISA modes match during branch assembly. -mignore-branch-isa disables those checks. By default -mno-ignore-branch-isa is selected, so any invalid branch that would require a transition between ISA modes produces an error. 👀
-mnan=encoding — picks between the IEEE 754-2008 NaN encoding format (-mnan=2008) and the legacy one (-mnan=legacy). The legacy format is the default, ngl.
--emulation=name — bestie, this one's a relic 💀 It used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose — it's just kept around for backwards compatibility. The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are the preferred options now.
-nocpp — as straight up ignores this option. It's accepted for compatibility with the native tools. Fake fan behavior honestly 🙈
--trap, --no-trap, --break, --no-break — controls how multiplication overflow and division by zero get handled. --trap or --no-break (synonyms!) take a trap exception, and those only work for Instruction Set Architecture level 2 and higher. --break or --no-trap (also synonyms, and the default) take a break exception. 💥
-n — when this is used, as issues a warning every single time it generates a nop instruction from a macro. Every. Single. Time. 🚨

🌈 When `as` is configured for a LoongArch processor

-fpic, -fPIC — generate position-independent code
-fno-pic — don't generate position-independent code (this one's the default)

🦋 When `as` is configured for a Meta processor

-mcpu=metac11 — generate code for Meta 1.1.
-mcpu=metac12 — generate code for Meta 1.2.
-mcpu=metac21 — generate code for Meta 2.1.
-mfpu=metac21 — allow code to use the FPU hardware of Meta 2.1.

See the info pages for documentation of the MMIX-specific options. (Yes, that's a whole different thing, go look it up ✨)

💜 When `as` is configured for a NDS32 processor

-O1 — optimize for performance.
-Os — optimize for space.
-EL — produce little endian data output.
-EB — produce little endian data output.

Okay so that's genuinely what the page says for -EB, both of them "little endian." Not me editing that, not me explaining it, just reporting what's printed 💀

-mpic — generate PIC.
-mno-fp-as-gp-relax — suppress fp-as-gp relaxation for this file.
-mb2bb-relax — back-to-back branch optimization.
-mno-all-relax — suppress all relaxation for this file.
-march=<arch name> — assemble for architecture <arch name>, which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.
-mbaseline=<baseline> — assemble for baseline <baseline>, which could be v2, v3, v3m.
-mfpu-freg=FREG — specify an FPU configuration. The options are iconic:

0      8 SP /  4 DP registers
1     16 SP /  8 DP registers
2     32 SP / 16 DP registers
3     32 SP / 32 DP registers

-mabi=abi — specify an abi version, <abi> could be v1, v2, v2fp, v2fpp.
-m[no-]mac — enable/disable Multiply instructions support.
-m[no-]div — enable/disable Divide instructions support.
-m[no-]16bit-ext — enable/disable 16-bit extension
-m[no-]dx-regs — enable/disable d0/d1 registers
-m[no-]perf-ext — enable/disable Performance extension
-m[no-]perf2-ext — enable/disable Performance extension 2
-m[no-]string-ext — enable/disable String extension
-m[no-]reduced-regs — enable/disable Reduced Register configuration (GPR16) option
-m[no-]audio-isa-ext — enable/disable AUDIO ISA extension
-m[no-]fpu-sp-ext — enable/disable FPU SP extension
-m[no-]fpu-dp-ext — enable/disable FPU DP extension
-m[no-]fpu-fma — enable/disable FPU fused-multiply-add instructions
-mall-ext — turn on all extensions and instructions support. All of them. Maximalist behavior 👑

🎀 When `as` is configured for a PowerPC processor

-a32 — generate ELF32 or XCOFF32.
-a64 — generate ELF64 or XCOFF64.
-K PIC — sets EF_PPC_RELOCATABLE_LIB in the ELF flags. tiny flag, big relocatable energy ✨
-mpwrx | -mpwr2 — generate code for POWER/2 (RIOS2).
-mpwr — generate code for POWER (RIOS1). yes the original original, respect the ancestors 🫶
-m601 — generate code for PowerPC 601.
-mppc, -mppc32, -m603, -m604 — generate code for PowerPC 603/604.
-m403, -m405 — generate code for PowerPC 403/405.
-m440 — generate code for PowerPC 440. that's BookE and some 405 instructions, bestie, it's giving hybrid 💅
-m464 — generate code for PowerPC 464.
-m476 — generate code for PowerPC 476.
-m7400, -m7410, -m7450, -m7455 — generate code for PowerPC 7400/7410/7450/7455.
-m750cl, -mgekko, -mbroadway — generate code for PowerPC 750CL/Gekko/Broadway. gamecube girlies rise 🌸
-m821, -m850, -m860 — generate code for PowerPC 821/850/860.
-mppc64, -m620 — generate code for PowerPC 620/625/630.
-me200z2, -me200z4 — generate code for e200 variants: e200z2 with LSP, e200z4 with SPE.
-me300 — generate code for the PowerPC e300 family.
-me500, -me500x2 — generate code for the Motorola e500 core complex.
-me500mc — generate code for the Freescale e500mc core complex.
-me500mc64 — generate code for the Freescale e500mc64 core complex.
-me5500 — generate code for the Freescale e5500 core complex.
-me6500 — generate code for the Freescale e6500 core complex.
-mlsp — enable LSP instructions. heads up: this disables SPE and SPE2. can't have both, it's a whole thing 😭
-mspe — generate code for Motorola SPE instructions. disables LSP.
-mspe2 — generate code for Freescale SPE2 instructions. disables LSP too.
-mtitan — generate code for the AppliedMicro Titan core complex.
-mppc64bridge — generate code for PowerPC 64, including bridge insns.
-mbooke — generate code for 32-bit BookE.
-ma2 — generate code for the A2 architecture.
-maltivec — generate code for processors with AltiVec instructions.
-mvle — generate code for Freescale PowerPC VLE instructions.
-mvsx — generate code for processors with Vector-Scalar (VSX) instructions.
-mhtm — generate code for processors with Hardware Transactional Memory instructions.
-mpower4, -mpwr4 — generate code for the Power4 architecture.
-mpower5, -mpwr5, -mpwr5x — generate code for the Power5 architecture.
-mpower6, -mpwr6 — generate code for the Power6 architecture.
-mpower7, -mpwr7 — generate code for the Power7 architecture.
-mpower8, -mpwr8 — generate code for the Power8 architecture.
-mpower9, -mpwr9 — generate code for the Power9 architecture.
-mpower10, -mpwr10 — generate code for the Power10 architecture.
-mpower11, -mpwr11 — generate code for the Power11 architecture.
-mfuture — generate code for the 'future' architecture. main character energy only 👑
-mcell — generate code for the Cell Broadband Engine architecture. (the manpage literally lists -mcell twice in a row and honestly? iconic. same flag, same vibe, no notes 💅)
-mcom — generate code Power/PowerPC common instructions.
-many — generate code for any architecture (PWR/PWRX/PPC). options open, bestie 🌈
-mregnames — allow symbolic names for registers.
-mno-regnames — do not allow symbolic names for registers.
-mrelocatable — support for GCC's -mrelocatable option.
-mrelocatable-lib — support for GCC's -mrelocatable-lib option.
-memb — set the PPC_EMB bit in ELF flags.
-mlittle, -mlittle-endian, -le — generate code for a little endian machine.
-mbig, -mbig-endian, -be — generate code for a big endian machine.
-nops=count — if an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops. efficiency slay ⚡

🦋 when `as` is configured for a RISC-V processor

-fpic, -fPIC — generate position-independent code.
-fno-pic — don't generate position-independent code. this one is the default.
-march=ISA|Profiles|Profiles_ISA — select the base isa, as specified by ISA or Profiles or Profies_ISA (yes that spelling is straight from the source, i don't make the rules 🙈). for example: -march=rv32ima -march=RVI20U64 -march=RVI20U64_d. if this option and the architecture attributes aren't set, then the assembler will check the default configure setting --with-arch=ISA.
-misa-spec=ISAspec — select the default isa spec version. if the version of ISA isn't set by -march, then the assembler helps to set the version according to the default chosen spec. if this option isn't set, then the assembler will check the default configure setting --with-isa-spec=ISAspec.
-mpriv-spec=PRIVspec — select the privileged spec version. we can decide whether the CSR is valid or not according to the chosen spec. if this option and the privilege attributes aren't set, then the assembler will check the default configure setting --with-priv-spec=PRIVspec.
-mabi=ABI — selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or "e" to indicate the soft-float calling convention ("e" indicates a soft-float RVE ABI).
-mrelax — take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. this is the default, we love a low-effort queen 💅
-mno-relax — don't do linker relaxations.
-march-attr — generate the default contents for the riscv elf attribute section if the .attribute directives are not set. this section is used to record the information that a linker or runtime loader needs to check compatibility. that info includes the ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of the privileged specification. it's giving ✨thorough✨
-mno-arch-attr — don't generate the default riscv elf attribute section if the .attribute directives are not set.
-mcsr-check — enable the CSR checking for the ISA-dependent CRS and the read-only CSR. the ISA-dependent CSR are only valid when the specific ISA is set. the read-only CSR can not be written by the CSR instructions. rules are rules 🚨
-mno-csr-check — don't do CSR checking.
-mlittle-endian — generate code for a little endian machine.
-mbig-endian — generate code for a big endian machine.

see the info pages for documentation of the RX-specific options. (not me pointing you at the info pages — go read them, bestie, they're right there 🫶)

💜 when `as` is configured for the s390 processor family

-m31, -m64 — select the word size, either 31/32 bits or 64 bits.
-mesa, -mzarch — select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).
-march=processor — specify which s390 processor variant is the target: g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or z17 (or arch15). that's the whole family tree, we stan a reunion 🌳
-mregnames, -mno-regnames — allow or disallow symbolic names for registers.
-mwarn-areg-zero — warn whenever the operand for a base or index register has been specified but evaluates to zero. like bestie… why 👀
-mwarn-regtype-mismatch=strict, -mwarn-regtype-mismatch=relaxed, -mwarn-regtype-mismatch=no, -mno-warn-regtype-mismatch — controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type. the default (which can be restored by using the relaxed argument) is to perform relaxed register name type checks, which allow floating point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating point register (FPR) operands — and that's acceptable as the FPR are embedded into the lower half of the VR. using the strict argument, strict register name type checks are performed. the no argument, which is equivalent to -mno-warn-regtype-mismatch, disables any register name type checks. so: relaxed, strict, or none — pick your fighter 💀

🎀 when `as` is configured for a TMS320C6000 processor

-march=arch — enable (only) instructions from architecture arch. by default, all instructions are permitted.

accepted values of arch: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x".

-mdsbt, -mno-dsbt — the -mdsbt option causes the assembler to generate the "Tag_ABI_DSBT" attribute with a value of 1, indicating that the code is using DSBT addressing. the -mno-dsbt option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. the linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. mixed-friend-group drama, but make it linking 😭
-mpid=no, -mpid=near, -mpid=far — the -mpid= option causes the assembler to generate the "Tag_ABI_PID" attribute with a value indicating the form of data addressing used by the code. -mpid=no, the default, indicates position-dependent data addressing; -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing; and -mpid=far indicates position-independent addressing with GOT accesses using far DP addressing. the linker will emit a warning if objects built with different settings of this option are linked together.
-mpic, -mno-pic — the -mpic option causes the assembler to generate the "Tag_ABI_PIC" attribute with a value of 1, indicating that the code is using position-independent code addressing. the "-mno-pic" option, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. the linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together.
-mbig-endian, -mlittle-endian — generate code for the specified endianness. the default is little-endian.

🌈 when `as` is configured for a TILE-Gx processor

-m32 | -m64 — select the word size, either 32 bits or 64 bits.
-EB | -EL — select the endianness, either big-endian (-EB) or little-endian (-EL).

⭐ when `as` is configured for a Visium processor

-mtune=arch — this option specifies the target architecture. if an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message.

the following names are recognized: "mcm24" "mcm" "gr5" "gr6"

and if you ignore the error message, that's on you, not me 🙈

🧚 when `as` is configured for an Xtensa processor

(hold that thought — more coming 💖)

--text-section-literals | --no-text-section-literals — bestie, this one controls how literal pools get treated 💅 The default is --no-text-section-literals, which puts literals in separate sections in the output file — that way the literal pool can live in a data RAM/ROM, iconic behavior honestly. With --text-section-literals, the literals get interspersed in the text section so they stay as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the L32R instructions in the text section. Literals are grouped into pools following .literal_position directives or preceding ENTRY instructions. Heads up: these options only affect literals referenced via PC-relative L32R instructions — literals for absolute mode L32R instructions are handled separately, no cap 🫶
--auto-litpools | --no-auto-litpools — same vibe, different flavor ✨ The default is --no-auto-litpools, which — in the absence of --text-section-literals — places literals in separate sections in the output file, so the literal pool can be placed in a data RAM/ROM. With --auto-litpools, the literals are interspersed in the text section to keep them as close as possible to their references, and explicit .literal_position directives are not required — lowkey magical. This may be necessary for very large functions, where a single literal pool at the beginning of the function may not be reachable by L32R instructions at the end. Again: these options only affect literals referenced via PC-relative L32R instructions; literals for absolute mode L32R instructions are handled separately. And when used together with --text-section-literals, --auto-litpools takes precedence. Periodt.
--absolute-literals | --no-absolute-literals — tells the assembler whether L32R instructions use absolute or PC-relative addressing 💫 If the processor includes the absolute addressing option, the default is to use absolute L32R relocations. Otherwise, only the PC-relative L32R relocations can be used. That's it, that's the whole vibe check 🦋
--target-align | --no-target-align — enable or disable automatic alignment to reduce branch penalties at some expense in code size 🎀 This optimization is enabled by default. Note that the assembler will always align instructions like LOOP that have fixed alignment requirements — no negotiating on that one, bestie 🙈
--longcalls | --no-longcalls — enable or disable transformation of call instructions so calls can reach across a greater range of addresses 🔥 Use this when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range (slay, linker). The default is --no-longcalls.
--transform | --no-transform — enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization 👑 The default is --transform; --no-transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source. And real talk: using --no-transform causes out of range instruction operands to be errors. 💀
--rename-section oldname=newname — renames the oldname section to newname. This option can be used multiple times to rename multiple sections 🌈 (yes, spam it, it's allowed)
--trampolines | --no-trampolines — enable or disable transformation of jump instructions to allow jumps across a greater range of addresses 🧚 Use this when jump targets can potentially be out of range. In the absence of such jumps this option does not affect code size or performance. The default is --trampolines.
--abi-windowed | --abi-call0 — chooses the ABI tag written to the .xtensa.info section 🎯 The ABI tag indicates the ABI of the assembly code. A warning is issued by the linker on an attempt to link object files with inconsistent ABI tags. Default ABI is chosen by the Xtensa core configuration.

🦋 The following options are available when `as` is configured for an Z80 processor 🦋

@chapter Z80 Dependent Features

✨ Command-line Options ✨

-march=CPU[-EXT...][+EXT...] — this option specifies the target processor 🎀 The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: z80, z180, ez80, gbz80, z80n, r800. In addition to the basic instruction set, the assembler can be told to accept some extension mnemonics. For example, -march=z180+sli+infc extends z180 with SLI instructions and IN F,(C). The following extensions are currently supported: full (all known instructions), adl (ADL CPU mode by default, eZ80 only), sli (instruction known as SLI, SLL or SL1), xyhl (instructions with halves of index registers: IXL, IXH, IYL, IYH), xdcb (instructions like RotOp (II+d),R and BitOp n,(II+d),R), infc (instruction IN F,(C) or IN (C)), outc0 (instruction OUT (C),0). Note that rather than extending a basic instruction set, the extension mnemonics starting with - revoke the respective functionality: -march=z80-full+xyhl first removes all default extensions and adds support for index register halves only. Sneaky but valid 💅

If this option is not specified then -march=z80+xyhl+infc is assumed. 🫶

-local-prefix=prefix — mark all labels with the specified prefix as local 💖 But such a label can be marked global explicitly in the code. This option does not change the default local label prefix .L — it just adds a new one.
-colonless — accept colonless labels 🌸 All symbols at line begin are treated as labels. Living dangerously, love that.
-sdcc — accept assembler code produced by SDCC 😌
-fp-s=FORMAT — single precision floating point numbers format. Default: ieee754 (32 bit).
-fp-d=FORMAT — double precision floating point numbers format. Default: ieee754 (64 bit).

💜 SEE ALSO 💜

gcc(1), ld(1), and the Info entries for binutils and ld. go read them, iykyk 📚

👑 COPYRIGHT 👑

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".

and that's the whole page, bestie 💖 you made it to the end, i'm literally so proud of you ✨🎀🦋

kay so this absolute icon of a manpage is binutils-2.47, dated 2026-08-31 — go forth and assemble, main character 🫶💅⭐

📦 where this page comes from

arch rolling: riscv64-linux-gnu-binutils 2.47-1 · GPL-2.0-or-later
💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on 2026-11-04: a language model's rewrite of the original, under its terms