AS(1)

📦 version 2.45.1, in arch rolling

💅 AS(1) — the portable GNU assembler ✨

okay so bestie, welcome to AS(1) — that's the manual page for the assembler, sitting pretty in the GNU Development Tools collection, section 1. and yes it's the source-of-truth list of every flag, so buckle up 🎀

✨ NAME ✨

AS — the portable GNU assembler. like, that's literally its whole name and its whole job. it assembles. portably. GNU-ly. periodt 💅

🎀 SYNOPSIS 🎀

here's the full invocation shape — the way that this thing is long, no cap. don't worry about memorizing it, nobody does. just know everything's optional-ish and it's giving "choose your own adventure" 🌈

as [-a[cdghilns][=file]]
 [--alternate]
 [--compress-debug-sections] [--nocompress-debug-sections]
 [-D]
 [--dump-config]
 [--debug-prefix-map old=new]
 [--defsym sym=val]
 [--elf-stt-common=[no|yes]]
 [--emulation=name]
 [-f]
 [-g] [--gstabs] [--gstabs+]
 [--gdwarf-<N>] [--gdwarf-sections]
 [--gdwarf-cie-version=VERSION]
 [--generate-missing-build-notes=[no|yes]]
 [--gsframe] [--gsframe=[no|yes]]
 [--hash-size=N]
 [--help] [--target-help]
 [--info] [--no-info]
 [-I dir]
 [-J]
 [-K]
 [--keep-locals]
 [-L]
 [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM]
 [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM]
 [--multibyte-handling=[allow|warn|warn-sym-only]]
 [--no-pad-sections]
 [-o objfile] [-R]
 [--scfi=experimental]
 [--sectname-subst]
 [--size-check=[error|warning]]
 [--statistics]
 [-v] [--verbose]
 [-version] [--version]
 [-W] [--no-warn] [--warn] [--fatal-warnings]
 [-w] [-x]
 [-Z] [@FILE]
 [target-options]
 [--|files ...]
ngl the [--|files ...] at the end is doing main character energy — it's the "everything after the double dash is a file" moment. iconic. 👑

🌈 TARGET 🌈

okay so this is the part where every CPU family gets its own little cameo 💖. each block below is verbatim — copy-paste exact, don't "fix" the dashes, don't rename anything, i am begging 🫶.

Target AArch64 options

   [-EB|-EL]
   [-mabi=ABI]

Target Alpha options

   [-mcpu]
   [-mdebug | -no-mdebug]
   [-replace | -noreplace]
   [-relax] [-g] [-Gsize]
   [-F] [-32addr]

Target ARC options

   [-mcpu=cpu]
   [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
   [-mcode-density]
   [-mrelax]
   [-EB|-EL]

Target ARM options

   [-mcpu=processor[+extension...]]
   [-march=architecture[+extension...]]
   [-mfpu=floating-point-format]
   [-mfloat-abi=abi]
   [-meabi=ver]
   [-mthumb]
   [-EB|-EL]
   [-mapcs-32|-mapcs-26|-mapcs-float|
    -mapcs-reentrant]
   [-mthumb-interwork] [-k]

Target Blackfin options

   [-mcpu=processor[-sirevision]]
   [-mfdpic]
   [-mno-fdpic]
   [-mnopic]

Target BPF options

   [-EL] [-EB]

Target CRIS options

   [--underscore | --no-underscore]
   [--pic] [-N]
   [--emulation=criself | --emulation=crisaout]
   [--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]

Target C-SKY options

   [-march=arch] [-mcpu=cpu]
   [-EL] [-mlittle-endian] [-EB] [-mbig-endian]
   [-fpic] [-pic]
   [-mljump] [-mno-ljump]
   [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
   [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
   [-mnolrw ] [-mno-lrw]
   [-melrw] [-mno-elrw]
   [-mlaf ] [-mliterals-after-func]
   [-mno-laf] [-mno-literals-after-func]
   [-mlabr] [-mliterals-after-br]
   [-mno-labr] [-mnoliterals-after-br]
   [-mistack] [-mno-istack]
   [-mhard-float] [-mmp] [-mcp] [-mcache]
   [-msecurity] [-mtrust]
   [-mdsp] [-medsp] [-mvdsp]
ok the C-SKY list is long long. and yes, [-mnolrw ] and [-mlaf ] really do have that stray space in there — i did not touch it, that's the vibe it came with 💀

Target D10V options

   [-O]

Target D30V options

   [-O|-n|-N]

Target EPIPHANY options

   [-mepiphany|-mepiphany16]

Target H8/300 options

   [-h-tick-hex]

Target i386 options

   [--32|--x32|--64] [-n]
   [-march=CPU[+EXTENSION...]] [-mtune=CPU]

Target IA-64 options

   [-mconstant-gp|-mauto-pic]
   [-milp32|-milp64|-mlp64|-mp64]
   [-mle|mbe]
   [-mtune=itanium1|-mtune=itanium2]
   [-munwind-check=warning|-munwind-check=error]
   [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
   [-x|-xexplicit] [-xauto] [-xdebug]

Target IP2K options

   [-mip2022|-mip2022ext]

Target M32C options

   [-m32c|-m16c] [-relax] [-h-tick-hex]

Target M32R options

   [--m32rx|--[no-]warn-explicit-parallel-conflicts|
   --W[n]p]

Target M680X0 options

   [-l] [-m68000|-m68010|-m68020|...]

Target M68HC11 options

   [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
   [-mshort|-mlong]
   [-mshort-double|-mlong-double]
   [--force-long-branches] [--short-branches]
   [--strict-direct-mode] [--print-insn-syntax]
   [--print-opcodes] [--generate-example]

Target MCORE options

   [-jsri2bsr] [-sifilter] [-relax]
   [-mcpu=[210|340]]

Target Meta options

   [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
   [-mlittle-endian] [-mbig-endian]
🙈 okay so the Meta block and the MICROBLAZE block are literally squished together on the same line up there — Target MICROBLAZE options: is right there in the middle of Meta's options. that's exactly how it is in the original, so i left it untouched. not me fixing it, no ma'am. 💅

Target MIPS options

   [-nocpp] [-EL] [-EB] [-O[optimization level]]
   [-g[debug level]] [-G num] [-KPIC] [-call_shared]
   [-non_shared] [-xgot [-mvxworks-pic]
   [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
   [-mfp64] [-mgp64] [-mfpxx]
   [-modd-spreg] [-mno-odd-spreg]
   [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
   [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
   [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
   [-mips64r3] [-mips64r5] [-mips64r6]
   [-construct-floats] [-no-construct-floats]
   [-mignore-branch-isa] [-mno-ignore-branch-isa]
   [-mnan=encoding]
   [-trap] [-no-break] [-break] [-no-trap]
   [-mips16] [-no-mips16]
   [-mmips16e2] [-mno-mips16e2]
   [-mmicromips] [-mno-micromips]
   [-msmartmips] [-mno-smartmips]
   [-mips3d] [-no-mips3d]
   [-mdmx] [-no-mdmx]
   [-mdsp] [-mno-dsp]
   [-mdspr2] [-mno-dspr2]
   [-mdspr3] [-mno-dspr3]
   [-mmsa] [-mno-msa]
   [-mxpa] [-mno-xpa]
   [-mmt] [-mno-mt]
   [-mmcu] [-mno-mcu]
   [-mcrc] [-mno-crc]
   [-mginv] [-mno-ginv]
   [-mloongson-mmi] [-mno-loongson-mmi]
   [-mloongson-cam] [-mno-loongson-cam]
   [-mloongson-ext] [-mno-loongson-ext]
   [-mloongson-ext2] [-mno-loongson-ext2]
   [-minsn32] [-mno-insn32]
   [-mfix7000] [-mno-fix7000]
   [-mfix-rm7000] [-mno-fix-rm7000]
   [-mfix-vr4120] [-mno-fix-vr4120]
   [-mfix-vr4130] [-mno-fix-vr4130]
   [-mfix-r5900] [-mno-fix-r5900]
   [-mdebug] [-no-mdebug]
   [-mpdr] [-mno-pdr]
🔥 MIPS said "i will have one of everything" and honestly? ate. also peep [-xgot [-mvxworks-pic] — the bracket does not close, bestie, and that's canon, i'm not touching it 😭

Target MMIX options

   [--fixed-special-register-names] [--globalize-symbols]
   [--gnu-syntax] [--relax] [--no-predefined-symbols]
   [--no-expand] [--no-merge-gregs] [-x]
   [--linker-allocated-gregs]

Target NDS32 options

    [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
    [-misa=isa] [-mabi=abi] [-mall-ext]
    [-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
    [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
    [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
    [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
    [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
    [-mb2bb]

Target PDP11 options

   [-mpic|-mno-pic] [-mall] [-mno-extensions]
   [-mextension|-mno-extension]
   [-mcpu] [-mmachine]

Target picoJava options

   [-mb|-me]

Target PowerPC options

   [-a32|-a64]
   [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
    -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
    -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
    -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
    -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
    -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
   [-many] [-maltivec|-mvsx|-mhtm|-mvle]
   [-mregnames|-mno-regnames]
   [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
   [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
   [-msolaris|-mno-solaris]
   [-nops=count]
✨ that first PowerPC block is a whole wall of CPU names and it is giving shrine. -mppc? -mpower9? -m7455? she contains multitudes 🦋

Target PRU options

   [-link-relax]
   [-mnolink-relax]
   [-mno-warn-regname-label]

Target RISC-V options

   [-fpic|-fPIC|-fno-pic]
   [-march=ISA|Profiles|Profiles_ISA]
   [-mabi=ABI]
   [-mlittle-endian|-mbig-endian]

Target RL78 options

   [-mg10]
   [-m32bit-doubles|-m64bit-doubles]

Target RX options

   [-mlittle-endian|-mbig-endian]
   [-m32bit-doubles|-m64bit-doubles]
   [-muse-conventional-section-names]
   [-msmall-data-limit]
   [-mpid]
   [-mrelax]
   [-mint-register=number]
   [-mgcc-abi|-mrx-abi]

Target s390 options

   [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
   [-mregnames|-mno-regnames]
   [-mwarn-areg-zero]
   [-mwarn-regtype-mismatch=strict
    -mwarn-regtype-mismatch=relaxed
    -mwarn-regtype-mismatch=no
    -mno-warn-regtype-mismatch]

Target SCORE options

   [-EB][-EL][-FIXDD][-NWARN]
   [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
   [-march=score7][-march=score3]
   [-USE_R1][-KPIC][-O0][-G num][-V]

Target SPARC options

   [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
    -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
    -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
    -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
    -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
    -Asparcvisr|-Asparc5]
   [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
    -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
    -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
    -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
    -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
    -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
    -bump]
   [-32|-64]
   [--enforce-aligned-data][--dcti-couples-detect]
🫶 the SPARC -xarch= run is so long it needed its own zip code. also -Asparc and -Asparc5 are both in there and that is not a typo, they're different things, don't @ me 💀

Target TIC54X options

    [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
    [-merrors-to-file <filename>|-me <filename>]

Target TIC6X options

   [-march=arch] [-mbig-endian|-mlittle-endian]
   [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
   [-mpic|-mno-pic]

Target TILE-Gx options

   [-m32|-m64][-EB][-EL]

Target Visium options

   [-mtune=arch]

Target Xtensa options

   [--[no-]text-section-literals] [--[no-]auto-litpools]
   [--[no-]absolute-literals]
   [--[no-]target-align] [--[no-]longcalls]
   [--[no-]transform]
   [--rename-section oldname=newname]
   [--[no-]trampolines]
   [--abi-windowed|--abi-call0]

Target Z80 options

    [-march=CPU[-EXT][+EXT]]
    [-local-prefix=PREFIX]
    [-colonless]
    [-sdcc]
    [-fp-s=FORMAT]
    [-fp-d=FORMAT]
🌸 and that's the entire TARGET roster — every architecture accounted for, every bracket exactly where it was. part 2 is coming, don't go anywhere bestie 💜

✨ DESCRIPTION ✨

okay so bestie, here's the tea: GNU as is literally not one assembler, it's a whole family of assemblers 💅. If you've used the GNU assembler on one architecture, sliding over to another architecture should feel pretty comfy — like visiting your friend's house and the wifi password is the same. Each version has a ton in common with the others, including object file formats, most assembler directives (which everyone calls pseudo-ops), and assembler syntax. iykyk.

as is primarily intended to assemble the output of the GNU C compiler gcc, for use by the linker ld. But ngl, we've tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly — no secret surprises. This does not mean as always uses the same syntax as another assembler for the same architecture; for example, we know of several incompatible versions of 680x0 assembly language syntax. so yeah, chaos lives there, don't @ us.

Each time you run as it assembles exactly one source program. That source program is made up of one or more files. (The standard input is also a file, she's valid too 💖.)

You give as a command line that has zero or more input file names. The input files are read from left file name to right. A command-line argument (in any position) that has no special meaning is taken to be an input file name. simple as that.

If you give as no file names, it attempts to read one input file from the as standard input, which is normally your terminal. You may have to type ctl-D to tell as there is no more program to assemble. (yes bestie, you literally tell it "that's all, bye" 💀)

Use -- if you need to explicitly name the standard input file in your command line.

If the source is empty, as produces a small, empty object file. tiny baby object file 🥺 iconic.

as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly. so: warning = "we're still going, but side-eye 👀", error = "bestie the assembly is over."

If you are invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the -Wa) by commas. For example:

gcc -c -g -O -Wa,-alh,-L file.c

This passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table). two options, one little comma-separated package, she ate ✨.

Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.) so like, a lot of the time it's already handled for you, but -v is right there if you're nosy — and honestly, be nosy 🔍.

💅 OPTIONS 💅

buckle up, this list is long and we're going through all of it. no skimming, bestie 🫶.

  • @file — Read command-line options from file. The options read are inserted in place of the original @file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed.

Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively. it's giving inception 🌀 — don't worry, that recursion is intentional.

  • -a[cdghilmns] — Turn on listings, in any of a variety of ways:
    • -ac — omit false conditionals
    • -ad — omit debugging directives
    • -ag — include general information, like as version and options passed
    • -ah — include high-level source
    • -al — include assembly
    • -ali — include assembly with ginsn
    • -am — include macro expansions
    • -an — omit forms processing
    • -as — include symbols
    • =file — set the name of the listing file

You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls. mix and match, it's a whole vibe check 🎀

  • --alternate — Begin in alternate macro mode.
  • --compress-debug-sections — Compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities 🙈. Note: if compression would make a given section larger, then it is not compressed.
  • --compress-debug-sections=none, --compress-debug-sections=zlib, --compress-debug-sections=zlib-gnu, --compress-debug-sections=zlib-gabi, --compress-debug-sections=zstd — These options control how DWARF debug sections are compressed.
    • --compress-debug-sections=none is equivalent to --nocompress-debug-sections.
    • --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to --compress-debug-sections.
    • --compress-debug-sections=zlib-gnu compresses DWARF debug sections using the obsoleted zlib-gnu format. The debug sections are renamed to begin with .zdebug.
    • --compress-debug-sections=zstd compresses DWARF debug sections using zstd.

Note: if compression would actually make a section larger, then it is not compressed nor renamed.

  • --nocompress-debug-sections — Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.
  • -D — Enable debugging in target specific backends, if supported. Otherwise ignored. Even if ignored, this option is accepted for script compatibility with calls to other assemblers. she's flexible like that 💅
  • --debug-prefix-map old=new — When assembling files in directory old, record debugging information describing them as in new instead.
  • --defsym sym=value — Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a .set pseudo-op.
  • --dump-config — Displays how the assembler is configured and then exits. a little self-portrait before she leaves 🪞
  • --elf-stt-common=no, --elf-stt-common=yes — These options control whether the ELF assembler should generate common symbols with the STT_COMMON type. The default can be controlled by a configure option --enable-elf-stt-common.
  • --emit-local-absolute — Emit even pre-defined (local) absolute symbols to the outgoing symbol table. Note that this isn't the exact opposite of --strip-local-absolute. not the exact opposite, bestie, read it again 🔥
  • --emulation=name — If the assembler is configured to support multiple different target configurations then this option can be used to select the desired form.
  • -f — "fast"—skip whitespace and comment preprocessing (assume source is compiler output). zoom zoom ⚡
  • -g, --gen-debug — Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a .debug_info and .debug_line section is only emitted when the assembly file doesn't generate one itself.
  • --gstabs — Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
  • --gstabs+ — Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program 💀. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time.
  • --gdwarf-2 — Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note: this option is only supported by some targets, not all of them.
  • --gdwarf-3 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
  • --gdwarf-4 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
  • --gdwarf-5 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
  • --gdwarf-sections — Instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. For example a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. If the code section is just called .text then debug line section will still be called just .debug_line without any suffix. per-section glow-up ✨
  • --gdwarf-cie-version=version — Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specified the default is version 1, though some targets can modify this default. Other possible values for version are 3 or 4.
  • --generate-missing-build-notes=yes, --generate-missing-build-notes=no — These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the --enable-generate-build-notes configure option.
  • --gsframe, --gsframe, --gsframe=no, --gsframe=yes — Create .sframe section from CFI directives. The explicit --gsframe=yes option behaves the same as --gsframe. Generation can be suppressed with --gsframe=no. (yes, --gsframe is listed twice up there — just keeping it 100% faithful to the page, no cap 🫶)
  • --hash-size N — Ignored. Supported for command line compatibility with other assemblers. she's just here to be polite 💅
  • --help — Print a summary of the command-line options and exit.
  • --target-help — Print a summary of all target specific options and exit.
  • --info — Don't suppress informational messages.
  • --no-info — Suppress informational messages.
  • -I dir — Add directory dir to the search list for .include directives.
  • -J — Don't warn about signed overflow.
  • -K — throws warnings at you when difference tables get altered for long displacements. like it's watching 👀
  • -L, --keep-locals — keeps local symbols in the symbol table. these are the lil guys that start with system-specific local label prefixes — typically .L for ELF systems or L for traditional a.out systems. don't lose them 💖
  • --listing-lhs-width=number — sets the max width, in words, of the output data column for an assembler listing to number. width matters bestie ✨
  • --listing-lhs-width2=number — same vibe but for continuation lines: sets the max width, in words, of the output data column for continuation lines in an assembler listing to number.
  • --listing-rhs-width=number — sets the max width of an input source line, as displayed in a listing, to number bytes.
  • --listing-cont-lines=number — caps how many lines get printed in a listing for a single line of input — it's number + 1. yes, plus one, that's not a typo 🎀
  • --multibyte-handling=allow, --multibyte-handling=warn, --multibyte-handling=warn-sym-only, --multibyte-handling=warn_sym_only — controls how the assembler handles multibyte characters in the input. the default is to allow such characters without complaint (and you can get back to that default by passing the allow argument). use warn and the assembler generates a warning message whenever any multibyte character is encountered. use warn-sym-only and it only warns when a symbol is defined with a name that contains multibyte characters — references to undefined symbols will not generate a warning. (also yes, warn_sym_only with underscores is a whole valid spelling, we love options 💅)
  • --no-pad-sections — stops the assembler from padding the ends of output sections to the alignment of that section. default is to pad the sections, but that can waste space, and some targets have tight memory constraints. lowkey a space saver 🦋
  • -o objfile — names the object-file output from as objfile. that's it, that's the whole job.
  • -R — folds the data section into the text section. merging era 🔥
  • --reduce-memory-overheads — ignored. it's supported purely for compatibility with tools that pass the same option to both the assembler and the linker. so it's there, it's just not doing anything 😭
  • --scfi=experimental — controls whether the assembler should synthesize CFI for hand-written input. if the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning. note that --scfi=experimental is not intended to be used for compiler-generated code, including inline assembly. this experimental support is work in progress. only System V AMD64 ABI is supported.

each input function in assembly must begin with the .type directive, and should ideally be closed off using a .size directive. when using SCFI, each .type directive prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry). this implies that with each .type directive, a previous block of instructions, if any, is finalised as a distinct FDE. it's giving experimental for a reason, bestie — tread carefully 🧚

  • --sectname-subst — honors substitution sequences in section names. periodt ✨
  • --size-check=error, --size-check=warning — issues an error or a warning for an invalid ELF .size directive. pick your fighter 💀
  • --statistics — prints the maximum space (in bytes) and total time (in seconds) used by assembly. receipts! 📊
  • --strip-local-absolute — removes local absolute symbols from the outgoing symbol table. bye bye 🫶
  • -v, --verbose — prints the as version.
  • --version, -version — prints the as version and exits. iconic exit behavior 👑
  • -W, --no-warn — suppresses warning messages. shhh 🤫
  • --warn — doesn't suppress warning messages and doesn't treat them as errors.
  • --fatal-warnings — treats warnings as errors. no chill mode 😤
  • -w — ignored.
  • -x — ignored.
  • -Z — generates an object file even after errors. bold. reckless. we respect it 💅
  • -- | files ... — standard input, or source files to assemble. feed her 🍓

🌈 the AArch64 era (64-bit mode of the ARM Architecture)

the following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64).

  • -EB — says the output generated by the assembler should be marked as being encoded for a big-endian processor.
  • -EL — says the output generated by the assembler should be marked as being encoded for a little-endian processor.
  • -mabi=abi — specifies which ABI the source code uses. the recognized arguments are: ilp32 and lp64, which decides the generated object file in ELF32 and ELF64 format respectively. the default is lp64. 💖
  • -mcpu=processor[+extension...] — specifies the target processor. the assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. the following processor names are recognized: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a510, cortex-a520, cortex-a710, cortex-a720, ares, exynos-m1, falkor, neoverse-n1, neoverse-n2, neoverse-e1, neoverse-v1, qdf24xx, saphira, thunderx, vulcan, xgene1 xgene2, cortex-r82, cortex-x1, cortex-x2, cortex-x3, and cortex-x4. the special name all may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions.

in addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.

if some implementations of a particular processor can have an extension, then then those extensions are automatically enabled. consequently, you will not normally have to specify any additional extensions. (yes the manpage says "then then", we're keeping it, it's part of the lore 🙈)

  • -march=architecture[+extension...] — specifies the target architecture. the assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. the following architecture names are recognized: armv8-a, armv8.1-a, armv8.2-a, armv8.3-a, armv8.4-a armv8.5-a, armv8.6-a, armv8.7-a, armv8.8-a, armv8.9-a, armv8-r, armv9-a, armv9.1-a, armv9.2-a, armv9.3-a, armv9.4-a and armv9.5-a.

if both -mcpu and -march are specified, the assembler will use the setting for -mcpu. if neither are specified, the assembler will default to -mcpu=all.

the architecture option can be extended with the same instruction set extension options as the -mcpu option. unlike -mcpu, extensions are not always enabled by default. ⭐

  • -mverbose-error — enables verbose error messages for AArch64 gas. this option is enabled by default. verbose queen 👑
  • -mno-verbose-error — disables verbose error messages in AArch64 gas.
  • -menable-sysreg-checking — enables error messages that are issued if an attempt is made to assemble a system register access which will not execute on the target architecture. it's checking ur vibes 🔍

🌸 the Alpha processor era

the following options are available when as is configured for an Alpha processor.

  • -mcpu — specifies the target processor. if an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. this option is equivalent to the .arch directive.

the following processor names are recognized: 21064, 21064a, 21066, 21068, 21164, 21164a, 21164pc, 21264, 21264a, 21264b, ev4, ev5, lca45, ev5, ev56, pca56, ev6, ev67, ev68. (yep, ev5 shows up twice in there — that's how it's written 🫠) the special name all may be used to allow the assembler to accept instructions valid for any Alpha processor.

in order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the electro-vlasic names (e.g. ev4) do not. 💅

  • -mdebug, -no-mdebug — enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. the default is to automatically enable .mdebug when the first stabs directive is seen.
  • -relax — forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. however, the option can still be useful in specific applications. niche but valid 🦋
  • -replace, -noreplace — enables or disables the optimization of procedure calls, both at assemblage and at link time. these options are only available for VMS targets and -replace is the default. see section 1.4.1 of the OpenVMS Linker Utility Manual. 📚
  • -g — used when the compiler generates debug information. when gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. otherwise this option has no effect. shrug 😭
  • -Gsize — a local common symbol larger than size is placed in .bss, while smaller symbols are placed in .sbss. size-based sorting, we love a threshold 💖
  • -F, -32addr — these options are ignored for backward compatibility.

🎀 the ARC processor era

the following options are available when as is configured for an ARC processor.

  • -mcpu=cpu — selects the core processor variant.
  • -EB | -EL — selects either big-endian (-EB) or little-endian (-EL) output. pick a lane ✨
  • -mcode-density — enables Code Density extension instructions. packing it in 📦

🔥 the ARM processor family era

the following options are available when as is configured for the ARM processor family.

  • -mcpu=processor[+extension...] — specifies which ARM processor variant is the target.
  • -march=architecture[+extension...] — specifies which ARM architecture variant is used by the target.
  • -mfpu=floating-point-format — selects which Floating Point architecture is the target.
  • -mfloat-abi=abi — selects which floating point ABI is in use.
  • -mthumb — enables Thumb only instruction decoding. thumb gang 👍
  • -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant — selects which procedure calling convention is in use.
  • -EB | -EL — selects either big-endian (-EB) or little-endian (-EL) output.
  • -mthumb-interwork — specifies that the code has been generated with interworking between Thumb and ARM code in mind. teamwork makes the dream work 🤝
  • -mccs — turns on CodeComposer Studio assembly syntax compatibility mode.
  • -k — specifies that PIC code has been generated.

The following options are available when as is configured for the Blackfin processor family. 🖤

  • -mcpu=processor[-sirevision] — this picks the target processor. The optional sirevision is not used in assembler; it’s just here so GCC can easily pass down its -mcpu= option. The assembler will issue an error message if you try to assemble an instruction that won’t execute on the target processor. Recognized processor names are: bf504, bf506, bf512, bf514, bf516, bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf535 (not implemented yet), bf536, bf537, bf538, bf539, bf542, bf542m, bf544, bf544m, bf547, bf547m, bf548, bf548m, bf549, bf549m, bf561, and bf592.
  • -mfdpic — assemble for the FDPIC ABI. ✨
  • -mno-fdpic, -mnopic — disable -mfdpic.

The following options are available when as is configured for the Linux kernel BPF processor family. 🦋

🦋 BPF Dependent Features

BPF Options

  • -EB — tells the assembler to emit big-endian eBPF.
  • -EL — tells the assembler to emit little-endian eBPF.
  • -mdialect=dialect — says which assembly language dialect to recognize while assembling. The assembler supports normal and pseudoc.
  • -misa-spec=spec — says which version of the BPF instruction set to use when assembling. The supported BPF ISA versions are v1 v2, v3 and v4.

The value xbpf can be specified to recognize extra instructions that GCC uses for testing purposes. But beware: this is not valid BPF. 💀

  • -mno-relax — tells the assembler to not relax instructions.
Note that if no endianness option is specified in the command line, the host endianness is used. See the info pages for documentation of the CRIS-specific options.

The following options are available when as is configured for the C-SKY processor family. 🌸

🌸 C-SKY processor family

  • -march=archname — assemble for architecture archname. The --help option lists valid values for archname.
  • -mcpu=cpuname — assemble for architecture cpuname. The --help option lists valid values for cpuname.
  • -EL, -mlittle-endian — generate little-endian output.
  • -EB, -mbig-endian — generate big-endian output.
  • -fpic, -pic — generate position-independent code.
  • -mljump, -mno-ljump — enable/disable transformation of the short branch instructions jbf, jbt, and jbr to jmpi. This option is for V2 processors only. It is ignored on CK801 and CK802 targets, which do not support the jmpi instruction, and is enabled by default for other processors.
  • -mbranch-stub, -mno-branch-stub — pass through R_CKCORE_PCREL_IMM26BY2 relocations for bsr instructions to the linker.

This option is only available for bare-metal C-SKY V2 ELF targets, where it is enabled by default. It cannot be used in code that will be dynamically linked against shared libraries. ⚠️

  • -force2bsr, -mforce2bsr, -no-force2bsr, -mno-force2bsr — enable/disable transformation of jbsr instructions to bsr. This option is always enabled (and -mno-force2bsr is ignored) for CK801/CK802 targets. It is also always enabled when -mbranch-stub is in effect.
  • -jsri2bsr, -mjsri2bsr, -no-jsri2bsr, -mno-jsri2bsr — enable/disable transformation of jsri instructions to bsr. This option is enabled by default.
  • -mnolrw, -mno-lrw — enable/disable transformation of lrw instructions into a movih/ori pair.
  • -melrw, -mno-elrw — enable/disable extended lrw instructions. This option is enabled by default for CK800-series processors.
  • -mlaf, -mliterals-after-func, -mno-laf, -mno-literals-after-func — enable/disable placement of literal pools after each function.
  • -mlabr, -mliterals-after-br, -mno-labr, -mnoliterals-after-br — enable/disable placement of literal pools after unconditional branches. This option is enabled by default.
  • -mistack, -mno-istack — enable/disable interrupt stack instructions. This option is enabled by default on CK801, CK802, and CK802 processors.

The following options explicitly enable certain optional instructions. These features are also enabled implicitly by using -mcpu= to specify a processor that supports it. 👑

  • -mhard-float — enable hard float instructions.
  • -mmp — enable multiprocessor instructions.
  • -mcp — enable coprocessor instructions.
  • -mcache — enable cache prefetch instruction.
  • -msecurity — enable C-SKY security instructions.
  • -mtrust — enable C-SKY trust instructions.
  • -mdsp — enable DSP instructions.
  • -medsp — enable enhanced DSP instructions.
  • -mvdsp — enable vector DSP instructions.

The following options are available when as is configured for an Epiphany processor. 🧚

🧚 Epiphany processor

  • -mepiphany — specifies that both 32 and 16 bit instructions are allowed. This is the default behavior.
  • -mepiphany16 — restricts the permitted instructions to just the 16 bit set.

The following options are available when as is configured for an H8/300 processor. 🍓

🍓 H8/300 Dependent Features

Options

The Renesas H8/300 version of as has one machine-dependent option:

  • -h-tick-hex — support H'00 style hex constants in addition to 0x00 style.
  • -mach=name — sets the H8300 machine variant. The following machine names are recognised: h8300h, h8300hn, h8300s, h8300sn, h8300sx and h8300sxn.

The following options are available when as is configured for an i386 processor. 💻

💻 i386 processor

  • --32 | --x32 | --64 — select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.

These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).

  • -n — by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.
  • --divide — on SVR4-derived platforms, the character / is treated as a comment character, which means that it cannot be used in expressions. The --divide option turns / into a normal character. This does not disable / at the beginning of a line starting a comment, or affect using # for starting a comment.
  • -march=CPU[+EXTENSION...] — this option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, znver5, btver1, btver2, generic32 and generic64.

In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics. For example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. The following extensions are currently supported: 8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb, avx10.1, avx10.1/512, avx10.1/256, avx10.1/128, user_msr, msr_imm, apx_f, avx10.2, avx10.2/512, avx10.2/256, avx10.2/128, movrs, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8, amx_movrs, amx_avx512, amx_tile, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, snp, invlpgb, tlbsync, rmpquery, rmpread, svme, gmism2, gmiccs, padlockrng2, padlockphe2, padlockxmodx and padlock.

Note that these extension mnemonics can be prefixed with no to revoke the respective (and any dependent) functionality. Note further that the suffixes permitted on -march=avx10.<N> enforce a vector length restriction, i.e. despite these otherwise being “enabling” options, using these suffixes will disable all insns with wider vector or mask register operands.

When the .arch directive is used with -march, the .arch directive will take precedent.

  • -mtune=CPU — this option specifies a processor to optimize for. When used in conjunction with the -march option, only instructions of the processor specified by the -march option will be generated.

Valid CPU values are identical to the processor list of -march=CPU.

  • -moperand-check=none, -moperand-check=warning, -moperand-check=error — these control whether the assembler does a little vibe check on certain instruction operands or operand combos 🕵️‍♀️ like, the example given is instructions where the operand size just cannot be inferred from its operands and nobody specified it via an instruction suffix. none = no checks at all, warning = throw a warning when the checks fail (this is the default, bestie), error = straight up error when they fail.
  • -msse2avx — tells the assembler to encode SSE instructions with a VEX prefix, which means AVX has to be available. And if the SSE instructions use extended GPRs, they get encoded with an EVEX prefix instead, which needs AVX512 or AVX10 to be available. upgrade era 💅
  • -muse-unaligned-vector-move — makes the assembler encode aligned vector moves as unaligned vector moves. chaotic but ok 🌀
  • -msse-check=none, -msse-check=warning, -msse-check=error — controls whether the assembler checks SSE instructions. none = no checking at all, which is the default. warning = warn on any SSE instruction. error = error on any SSE instruction.
  • -mavxscalar=128, -mavxscalar=256 — controls how scalar AVX instructions get encoded. 128 = 128bit vector length, and that's the default. 256 = 256bit vector length.
⚠️ WARNING: don't use this for production code — due to CPU errata the resulting code may not work on certain models. no cap, please don't ship this 😭
  • -mvexwig=0, -mvexwig=1 — controls how VEX.W-ignored (WIG) VEX instructions get encoded. 0 = vex.w = 0, the default. 1 = encode WIG EVEX instructions with vex.w = 1.
⚠️ WARNING: don't use this for production code — due to CPU errata the resulting code may not work on certain models. same energy, different flag 💀
  • -mevexlig=128, -mevexlig=256, -mevexlig=512 — controls how length-ignored (LIG) EVEX instructions get encoded. 128 = 128bit vector length, default obviously. 256 and 512 = 256bit and 512bit vector length respectively. pick your fighter ✨
  • -mevexwig=0, -mevexwig=1 — controls how w-ignored (WIG) EVEX instructions get encoded. 0 = evex.w = 0, the default. 1 = WIG EVEX instructions with evex.w = 1.
  • -mmnemonic=att, -mmnemonic=intel — sets the instruction mnemonic used for matching instructions. heads up tho: the .att_mnemonic and .intel_mnemonic directives take precedent 👑
  • -msyntax=att, -msyntax=intel — sets the instruction syntax used when processing instructions. and again, .att_syntax and .intel_syntax directives take precedent. directives stay winning fr fr
  • -mnaked-reg — says registers don't need a % prefix. and yes, once more, .att_syntax and .intel_syntax directives take precedent.
  • -madd-bnd-prefix — forces the assembler to slap a BND prefix on all branches, even the ones where you never wrote a BND prefix in your source. generous icon 🎀
  • -mno-shared — on ELF targets, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. the -mshared option tells it to generate code that could go into a shared library where all those non-weak global branch targets with default visibility can be preempted — the resulting code is slightly bigger. this option only affects how branch instructions are handled. it's giving "safety over slay" 🛡️
  • -mbig-obj — on PE/COFF targets this forces the big object file format, which lets you have more than 32768 sections. so many sections. obsessed 🗂️
  • -momit-lock-prefix=no, -momit-lock-prefix=yes — controls how the lock prefix gets encoded. it's a workaround for processors that fail on the lock prefix. yes omits all lock prefixes. no encodes the lock prefix as usual, which is the default.
🚨 this one can only be safely used with single-core, single-thread computers. like, read that again. single-core, single-thread. do not come for me if you ignore this 😭
  • -mfence-as-lock-add=no, -mfence-as-lock-add=yes — controls how lfence, mfence and sfence get encoded. yes encodes them as lock addl $0x0, (%rsp) in 64-bit mode and lock addl $0x0, (%esp) in 32-bit mode. no encodes lfence, mfence and sfence as usual, which is the default. yes that's a real instruction sequence, no I will not elaborate 💅
  • -mrelax-relocations=no, -mrelax-relocations=yes — controls whether the assembler generates relax relocations: R_386_GOT32X in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX in 64-bit mode. yes generates them, no doesn't. the default can be controlled by a configure option --enable-x86-relax-relocations. config girlies rise 🧚
  • -mtls-check=no, -mtls-check=yes — controls whether the assembler checks tls relocation. yes checks it, no doesn't. the default can be controlled by a configure option --enable-x86-tls-check.
  • -malign-branch-boundary=NUM — controls how the assembler aligns branches with segment prefixes or NOP. NUM must be a power of 2, and it should be 0 or no less than 16. branches get aligned within a NUM byte boundary. -malign-branch-boundary=0 is the default and means branches don't get aligned at all. math girlie moment 🔢
  • -malign-branch=TYPE[+TYPE...] — specifies which types of branches to align. TYPE is a combination of: jcc (aligns conditional jumps), fused (aligns fused conditional jumps), jmp (aligns unconditional jumps), call (aligns calls), ret (aligns rets), and indirect (aligns indirect jumps and calls). default is -malign-branch=jcc+fused+jmp. build your own combo, it's giving custom playlist 🎧
  • -malign-branch-prefix-size=NUM — the maximum number of prefixes on an instruction to align branches. NUM should be between 0 and 5, and the default NUM is 5.
  • -mbranches-within-32B-boundaries — aligns conditional jumps, fused conditional jumps and unconditional jumps within a 32 byte boundary, with up to 5 segment prefixes on an instruction. it's exactly equivalent to -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5. the default doesn't align branches. shortcut queen 👑
  • -mlfence-after-load=no, -mlfence-after-load=yes — controls whether the assembler generates lfence after load instructions. yes generates it, no doesn't, and no is the default.
  • -mlfence-before-indirect-branch=none, -mlfence-before-indirect-branch=all, -mlfence-before-indirect-branch=register, -mlfence-before-indirect-branch=memory — controls whether the assembler generates lfence before indirect near branch instructions. breaking it down:
    • all generates lfence before an indirect near branch via register, and issues a warning before an indirect near branch via memory. it also implicitly sets -mlfence-before-ret=shl when there's no explicit -mlfence-before-ret=. sneaky implicit behaviour, love that for us
    • register generates lfence before an indirect near branch via register
    • memory issues a warning before an indirect near branch via memory
    • none generates no lfence and issues no warning — that's the default
    • 📌 note: lfence won't be generated before an indirect near branch via register when -mlfence-after-load=yes is on, since lfence gets generated after loading the branch target register anyway. no double fencing, we're not doing that 💅
  • -mlfence-before-ret=none, -mlfence-before-ret=shl, -mlfence-before-ret=or, -mlfence-before-ret=yes, -mlfence-before-ret=not — controls whether the assembler generates lfence before ret. deets:
    • or generates an or instruction with lfence
    • shl / yes generates a shl instruction with lfence
    • not generates a not instruction with lfence
    • none generates no lfence, and that's the default 🎀
  • -mx86-used-note=no, -mx86-used-note=yes — controls whether the assembler generates the GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes. the default can be controlled by the --enable-x86-used-note configure option.
  • -mevexrcig=rne, -mevexrcig=rd, -mevexrcig=ru, -mevexrcig=rz — controls how SAE-only EVEX instructions get encoded. rne encodes the RC bits of the EVEX instruction as 00, which is the default. rd, ru and rz encode SAE-only EVEX instructions with 01, 10 and 11 RC bits, respectively. four little moods 🌈
  • -mamd64, -mintel64 — says the assembler should only accept AMD64 or Intel64 ISA in 64-bit mode. the default is to accept common, Intel64 only and AMD64 ISAs. pick a side or don't, your call ✨
  • -O0, -O, -O1, -O2, -Os — optimize instruction encoding for smaller instruction size. -O and -O1:
    • encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates
    • encode 64-bit register clearing instructions with 32-bit register clearing instructions
    • encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions
    • encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions
    • encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical

smaller bytes, same energy. slay 💖

  • -O2 — so -O2 is literally -O1 plus it encodes 256-bit/512-bit EVEX vector register clearing instructions using 128-bit EVEX vector register clearing instructions 💅✨. Also, in 64-bit mode, VEX encoded instructions with commutative source operands get their source operands swapped if that lets the assembler use the 2-byte VEX prefix form instead of the 3-byte one. And certain forms of AND, plus OR with the same (register) operand specified twice, get changed to TEST. iykyk 🎀
  • -Os — -Os is -O2 plus it encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. And -O0 turns this optimization off 🫶

🦋 the Ubicom IP2K era 🦋

The following options are available when as is configured for the Ubicom IP2K series ✨

  • -mip2022ext — says the extended IP2022 instructions are allowed 👑
  • -mip2022 — restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. back to basics, no cap 💜

🌸 Renesas M32C and M16C 🌸

The following options are available when as is configured for the Renesas M32C and M16C processors 💖

  • -m32c — assemble M32C instructions.
  • -m16c — assemble M16C instructions (and this one's the default 👀).
  • -relax — enable support for link-time relaxations. chill vibes only 😌
  • -h-tick-hex — support H'00 style hex constants in addition to 0x00 style. retro hex era 🙈

🎀 Renesas M32R (formerly Mitsubishi M32R) series 🎀

The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series ⭐

  • --m32rx — specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.
  • --warn-explicit-parallel-conflicts or --Wp — produce warning messages when questionable parallel constructs are encountered 👀
  • --no-warn-explicit-parallel-conflicts or --Wnp — do not produce warning messages when questionable parallel constructs are encountered 🤫

🧚 Motorola 68000 series 🧚

The following options are available when as is configured for the Motorola 68000 series 💖

  • -l — shorten references to undefined symbols, to one word instead of two. less is more 💅
  • the big processor picker — specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time.
-m68000 | -m68008 | -m68010 | -m68020 | -m68030
| -m68040 | -m68060 | -m68302 | -m68331 | -m68332
| -m68333 | -m68340 | -mcpu32 | -m5200
  • -m68881 | -m68882 | -mno-68881 | -mno-68882 — the target machine does (or does not) have a floating-point coprocessor 🧮. The default is to assume a coprocessor for 68020, 68030, and cpu32. And yeah — although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor. iconic loophole fr fr ✨
  • -m68851 | -mno-68851 — the target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up 👑

For details about the PDP-11 machine dependent features options, see PDP-11-Options 🔍

  • -mpic | -mno-pic — generate position-independent (or position-dependent) code. The default is -mpic 🌈
  • -mall
  • -mall-extensions — enable all instruction set extensions. This is the default 👑 (yes, both spellings, they're the same vibe)
  • -mno-extensions — disable all instruction set extensions. absolutely not the vibe 💀
  • -mextension | -mno-extension — enable (or disable) a particular instruction set extension 🎀
  • -mcpu — enable the instruction set extensions supported by a particular CPU, and disable all other extensions. main character CPU only 💅
  • -mmachine — enable the instruction set extensions supported by a particular machine model, and disable all other extensions 🛠️

💜 picoJava 💜

The following options are available when as is configured for a picoJava processor 🌸

  • -mb — generate "big endian" format output.
  • -ml — generate "little endian" format output.

🍓 PRU processor 🍓

The following options are available when as is configured for a PRU processor 💖

  • -mlink-relax — assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LD would shorten the LDI32 instruction to a single LDI. In such case as will output DIFF relocations for diff expressions 🤝
  • -mno-link-relax — assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted. no relocations, no drama 🙅‍♀️
  • -mno-warn-regname-label — do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off 👀

👑 MIPS processor 👑

The following options are available when as is configured for a MIPS processor ✨

  • -G num — this option sets the largest size of an object that can be referenced implicitly with the "gp" register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8 🎀
  • -EB — generate "big endian" format output.
  • -EL — generate "little endian" format output.
  • -mips1, -mips2, -mips3, -mips4, -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, -mips64r6 — generate code for a particular MIPS Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an alias for -march=r8000. Then -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. the whole alphabet of ISAs, ate and left no crumbs 💅🔥
  • -march=cpu — generate code for a particular MIPS CPU.
  • -mtune=cpu — schedule and tune for a particular MIPS CPU 🎶
  • -mfix7000, -mno-fix7000 — cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions 🔧
  • -mfix-rm7000, -mno-fix-rm7000 — cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.
  • -mfix-r5900, -mno-fix-r5900 — do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer, and always schedule a "nop" instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. hardware said no 😭💀
  • -mdebug, -no-mdebug — cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections 🐛
  • -mpdr, -mno-pdr — control generation of ".pdr" sections.
  • -mgp32, -mfp32 — the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers 🎀
  • -mgp64, -mfp64 — same deal, register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times. -mgp64 controls the size of general-purpose registers and -mfp64 controls the size of floating-point registers ✨
  • -mfpxx — register sizes are normally inferred from the ISA and ABI, but using this flag in combination with -mabi=32 enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide. flexible queen 🌸
  • -modd-spreg, -mno-odd-spreg — enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA. -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg 👀
  • -mips16, -no-mips16 — generate code for the MIPS 16 processor. This is equivalent to putting ".module mips16" at the start of the assembly file. -no-mips16 turns off this option.
  • -mmips16e2, -mno-mips16e2 — enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting ".module mips16e2" at the start of the assembly file. -mno-mips16e2 turns off this option 💜
  • -mmicromips, -mno-micromips — generate code for the microMIPS processor. This is equivalent to putting ".module micromips" at the start of the assembly file. -mno-micromips turns off this option. This is equivalent to putting ".module nomicromips" at the start of the assembly file 📎
  • -msmartmips, -mno-smartmips — enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting ".module smartmips" at the start of the assembly file. -mno-smartmips turns off this option 🧠✨
  • -mips3d, -no-mips3d — generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option 🎀
  • -mdmx, -no-mdmx — generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.
  • -mdsp, -mno-dsp — generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option 🎛️
  • -mdspr2, -mno-dspr2 — generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option.
  • -mdspr3, -mno-dspr3 — generate code for the DSP Release 3 Application Specific Extension. This option implies -mdsp and -mdspr2. This tells the assembler to accept DSP Release 3 instructions. -mno-dspr3 turns off this option. the whole DSP family tree, we love a lineage 👑
  • -mmsa, -mno-msa — generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. -mno-msa turns off this option 🌈
  • -mxpa, -mno-xpa — generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions. -mno-xpa turns off this option 🔥
  • -mmt, -mno-mt — generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns off this option 💅
  • -mmcu, -mno-mcu — generate code for the MCU Application Specific Extension. This is you telling the assembler "yes babe, accept MCU instructions." -mno-mcu turns it back off. ✨
  • -mcrc, -mno-crc — generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. Lets the assembler accept CRC instructions. -mno-crc switches it off.
  • -mginv, -mno-ginv — generate code for the Global INValidate (GINV) Application Specific Extension. Assembler accepts GINV instructions. -mno-ginv = off. 🎀
  • -mloongson-mmi, -mno-loongson-mmi — generate code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. Assembler accepts MMI instructions. -mno-loongson-mmi kills it.
  • -mloongson-cam, -mno-loongson-cam — generate code for the Loongson Content Address Memory (CAM) instructions. Assembler accepts Loongson CAM instructions. -mno-loongson-cam turns it off.
  • -mloongson-ext, -mno-loongson-ext — generate code for the Loongson EXTensions (EXT) instructions. Assembler accepts Loongson EXT instructions. -mno-loongson-ext = off.
  • -mloongson-ext2, -mno-loongson-ext2 — generate code for the Loongson EXTensions R2 (EXT2) instructions. Heads up: this option implies -mloongson-ext (package deal 🫶). Assembler accepts Loongson EXT2 instructions. -mno-loongson-ext2 turns it off.
  • -minsn32, -mno-insn32 — only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions. It's equivalent to putting .set insn32 at the start of the assembly file. -mno-insn32 turns it off — equivalent to putting .set noinsn32 at the start of the assembly file. By default -mno-insn32 is selected, so all instructions are allowed to be used. 💅
  • --construct-floats, --no-construct-floats — --no-construct-floats disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default --construct-floats is selected, which allows construction of those floating point constants.
  • --relax-branch, --no-relax-branch — --relax-branch enables relaxation of out-of-range branches. By default --no-relax-branch is selected, which means any out-of-range branch throws an error. 😭
  • -mignore-branch-isa, -mno-ignore-branch-isa — ignore branch checks for invalid transitions between ISA modes. Okay so the tea ☕: branches' semantics don't provide for an ISA mode switch, so in most cases the ISA mode a branch was encoded for has to be the same as the ISA mode of the branch's target label. So GAS has checks implemented that verify in branch assembly that the two ISA modes match. -mignore-branch-isa disables those checks. By default -mno-ignore-branch-isa is selected, so any invalid branch requiring a transition between ISA modes produces an error.
  • -mnan=encoding — pick between the IEEE 754-2008 NaN encoding format (-mnan=2008) or the legacy one (-mnan=legacy). The legacy one is the default. 🦋
  • --emulation=name — this option was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24 though, so lowkey it serves little purpose now. It's retained for backwards compatibility.

The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are the preferred options now instead. 👑

  • -nocpp — as ignores this option. It's just accepted for compatibility with the native tools. Not me accepting an option and doing nothing with it 💀
  • --trap, --no-trap, --break, --no-break — control how to deal with multiplication overflow and division by zero. --trap or --no-break (synonyms, bestie) take a trap exception — and those only work for Instruction Set Architecture level 2 and higher. --break or --no-trap (also synonyms, and the default) take a break exception.
  • -n — when this is used, as issues a warning every time it generates a nop instruction from a macro. Every. Single. Time. 🙈

The following options are available when as is configured for a LoongArch processor. 🌈

  • -fpic, -fPIC — generate position-independent code.
  • -fno-pic — don't generate position-independent code (default).

The following options are available when as is configured for a Meta processor.

  • -mcpu=metac11 — generate code for Meta 1.1.
  • -mcpu=metac12 — generate code for Meta 1.2.
  • -mcpu=metac21 — generate code for Meta 2.1.
  • -mfpu=metac21 — allow code to use FPU hardware of Meta 2.1.

See the info pages for documentation of the MMIX-specific options. (iykyk, go read 'em 📖)

The following options are available when as is configured for a NDS32 processor.

  • -O1 — optimize for performance. 🔥
  • -Os — optimize for space.
  • -EL — produce little endian data output.
  • -EB — produce little endian data output. (yes, that's really what the page says for -EB too — not my typo, I promise 😭)
  • -mpic — generate PIC.
  • -mno-fp-as-gp-relax — suppress fp-as-gp relaxation for this file.
  • -mb2bb-relax — back-to-back branch optimization.
  • -mno-all-relax — suppress all relaxation for this file.
  • -march=<arch name> — assemble for architecture <arch name>, which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.
  • -mbaseline=<baseline> — assemble for baseline <baseline>, which could be v2, v3, v3m.
  • -mfpu-freg=FREG — specify a FPU configuration.
0      8 SP /  4 DP registers
1     16 SP /  8 DP registers
2     32 SP / 16 DP registers
3     32 SP / 32 DP registers
  • -mabi=abi — specify a abi version, <abi> could be v1, v2, v2fp, v2fpp.
  • -m[no-]mac — enable/disable Multiply instructions support.
  • -m[no-]div — enable/disable Divide instructions support.
  • -m[no-]16bit-ext — enable/disable 16-bit extension.
  • -m[no-]dx-regs — enable/disable d0/d1 registers.
  • -m[no-]perf-ext — enable/disable Performance extension.
  • -m[no-]perf2-ext — enable/disable Performance extension 2.
  • -m[no-]string-ext — enable/disable String extension.
  • -m[no-]reduced-regs — enable/disable Reduced Register configuration (GPR16) option.
  • -m[no-]audio-isa-ext — enable/disable AUDIO ISA extension.
  • -m[no-]fpu-sp-ext — enable/disable FPU SP extension.
  • -m[no-]fpu-dp-ext — enable/disable FPU DP extension.
  • -m[no-]fpu-fma — enable/disable FPU fused-multiply-add instructions.
  • -mall-ext — turn on all extensions and instructions support. the full slay package ✨

The following options are available when as is configured for a PowerPC processor. y'all ready, this list is long 🫶

  • -a32 — generate ELF32 or XCOFF32.
  • -a64 — generate ELF64 or XCOFF64.
  • -K PIC — set EF_PPC_RELOCATABLE_LIB in ELF flags.
  • -mpwrx | -mpwr2 — generate code for POWER/2 (RIOS2).
  • -mpwr — generate code for POWER (RIOS1).
  • -m601 — generate code for PowerPC 601.
  • -mppc, -mppc32, -m603, -m604 — generate code for PowerPC 603/604.
  • -m403, -m405 — generate code for PowerPC 403/405.
  • -m440 — generate code for PowerPC 440. BookE and some 405 instructions.
  • -m464 — generate code for PowerPC 464.
  • -m476 — generate code for PowerPC 476.
  • -m7400, -m7410, -m7450, -m7455 — generate code for PowerPC 7400/7410/7450/7455.
  • -m750cl, -mgekko, -mbroadway — generate code for PowerPC 750CL/Gekko/Broadway.
  • -m821, -m850, -m860 — generate code for PowerPC 821/850/860.
  • -mppc64, -m620 — generate code for PowerPC 620/625/630.
  • -me200z2, -me200z4 — generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.
  • -me300 — generate code for PowerPC e300 family.
  • -me500, -me500x2 — generate code for Motorola e500 core complex.
  • -me500mc — generate code for Freescale e500mc core complex.
  • -me500mc64 — generate code for Freescale e500mc64 core complex.
  • -me5500 — generate code for Freescale e5500 core complex.
  • -me6500 — generate code for Freescale e6500 core complex.
  • -mlsp — enable LSP instructions. (Disables SPE and SPE2.) 🎀
  • -mspe — generate code for Motorola SPE instructions. (Disables LSP.)
  • -mspe2 — generate code for Freescale SPE2 instructions. (Disables LSP.)
  • -mtitan — generate code for AppliedMicro Titan core complex.
  • -mppc64bridge — generate code for PowerPC 64, including bridge insns.
  • -mbooke — generate code for 32-bit BookE.
  • -ma2 — generate code for A2 architecture.
  • -maltivec — generate code for processors with AltiVec instructions.
  • -mvle — generate code for Freescale PowerPC VLE instructions.
  • -mvsx — generate code for processors with Vector-Scalar (VSX) instructions.
  • -mhtm — generate code for processors with Hardware Transactional Memory instructions.
  • -mpower4, -mpwr4 — generate code for Power4 architecture.
  • -mpower5, -mpwr5, -mpwr5x — generate code for Power5 architecture.
  • -mpower6, -mpwr6 — generate code for Power6 architecture.
  • -mpower7, -mpwr7 — generate code for Power7 architecture.
  • -mpower8, -mpwr8 — generate code for Power8 architecture.
  • -mpower9, -mpwr9 — generate code for Power9 architecture.
  • -mpower10, -mpwr10 — generate code for Power10 architecture.
  • -mpower11, -mpwr11 — generate code for Power11 architecture.
  • -mfuture — generate code for 'future' architecture. 🔮 main character energy fr
  • -mcell — generate code for Cell Broadband Engine architecture.
  • -mcell — generate code for Cell Broadband Engine architecture. (yes, it's listed twice in the page — she said it twice because she meant it 💅)
  • -mcom — generate code Power/PowerPC common instructions.
  • -many — generate code for any architecture (PWR/PWRX/PPC).
  • -mregnames — allow symbolic names for registers.
  • -mno-regnames — do not allow symbolic names for registers.
  • -mrelocatable — support for GCC's -mrelocatable option.
  • -mrelocatable-lib — support for GCC's -mrelocatable-lib option.
  • -memb — set PPC_EMB bit in ELF flags.
  • -mlittle, -mlittle-endian, -le — generate code for a little endian machine.
  • -mbig, -mbig-endian, -be — generate code for a big endian machine. big-endian bestie behavior 💅
  • -msolaris — generate code for Solaris. 🌞
  • -mno-solaris — do not generate code for Solaris. 🙅
  • -nops=count — if an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops. yes, that's the whole vibe 😭

✨ The following options are available when as is configured for a RISC-V processor: ✨

  • -fpic, -fPIC — generate position-independent code. 🦋
  • -fno-pic — don't generate position-independent code. This is the default. modest but real.
  • -march=ISA|Profiles|Profiles_ISA — select the base isa, as specified by ISA or Profiles or Profies_ISA (that spelling is what the page says, bestie 💀). For example: -march=rv32ima, -march=RVI20U64, -march=RVI20U64_d. If this option and the architecture attributes aren't set, then the assembler will check the default configure setting --with-arch=ISA.
  • -misa-spec=ISAspec — select the default isa spec version. If the version of ISA isn't set by -march, then the assembler helps to set the version according to the default chosen spec. If this option isn't set, then the assembler will check the default configure setting --with-isa-spec=ISAspec. 🧚
  • -mpriv-spec=PRIVspec — select the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren't set, then the assembler will check the default configure setting --with-priv-spec=PRIVspec. 👑
  • -mabi=ABI — selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or "e" to indicate the soft-float calling convention ("e" indicates a soft-float RVE ABI). 💖
  • -mrelax — take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. This is the default. 🫶
  • -mno-relax — don't do linker relaxations. no thoughts, just no relax. 🙈
  • -march-attr — generate the default contents for the riscv elf attribute section if the .attribute directives are not set. This section is used to record the information that a linker or runtime loader needs to check compatibility. This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification. 📝
  • -mno-arch-attr — don't generate the default riscv elf attribute section if the .attribute directives are not set. 🚫
  • -mcsr-check — enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions. 🔍
  • -mno-csr-check — don't do CSR checking. 😌
  • -mlittle-endian — generate code for a little endian machine. 🍓
  • -mbig-endian — generate code for a big endian machine. 🐘

📖 See the info pages for documentation of the RX-specific options.

✨ The following options are available when as is configured for the s390 processor family: ✨

  • -m31, -m64 — select the word size, either 31/32 bits or 64 bits. ⭐
  • -mesa, -mzarch — select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch). 🏛️
  • -march=processor — specify which s390 processor variant is the target: g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or z17 (or arch15). 👑
  • -mregnames, -mno-regnames — allow or disallow symbolic names for registers. 🏷️
  • -mwarn-areg-zero — warn whenever the operand for a base or index register has been specified but evaluates to zero. ⚠️
  • -mwarn-regtype-mismatch=strict, -mwarn-regtype-mismatch=relaxed, -mwarn-regtype-mismatch=no, -mno-warn-regtype-mismatch — controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type. The default (which can be restored by using the relaxed argument) is to perform relaxed register name type checks, which allow floating point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating point register (FPR) operands. This is acceptable as the FPR are embedded into the lower half of the VR. Using the strict argument, strict register name type checks are performed. The no argument, which is equivalent to -mno-warn-regtype-mismatch, disables any register name type checks. 💅

✨ The following options are available when as is configured for a TMS320C6000 processor: ✨

  • -march=arch — enable (only) instructions from architecture arch. By default, all instructions are permitted. The following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x". 🎯
  • -mdsbt, -mno-dsbt — the -mdsbt option causes the assembler to generate the "Tag_ABI_DSBT" attribute with a value of 1, indicating that the code is using DSBT addressing. The -mno-dsbt option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. 🔗
  • -mpid=no, -mpid=near, -mpid=far — the -mpid= option causes the assembler to generate the "Tag_ABI_PID" attribute with a value indicating the form of data addressing used by the code. -mpid=no, the default, indicates position-dependent data addressing, -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing, and -mpid=far indicates position-independent addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together. 🧭
  • -mpic, -mno-pic — the -mpic option causes the assembler to generate the "Tag_ABI_PIC" attribute with a value of 1, indicating that the code is using position-independent code addressing. The -mno-pic option, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together. 🎨
  • -mbig-endian, -mlittle-endian — generate code for the specified endianness. The default is little-endian. 🐘🍓

✨ The following options are available when as is configured for a TILE-Gx processor: ✨

  • -m32 / -m64 — select the word size, either 32 bits or 64 bits. 📏
  • -EB / -EL — select the endianness, either big-endian (-EB) or little-endian (-EL). 🌍

✨ The following option is available when as is configured for a Visium processor: ✨

  • -mtune=arch — this option specifies the target architecture. If an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. The following names are recognized: "mcm24" "mcm" "gr5" "gr6". 🎛️

✨ The following options are available when as is configured for an Xtensa processor: ✨

  • --text-section-literals / --no-text-section-literals — control the treatment of literal pools. The default is --no-text-section-literals, which places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With --text-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the "L32R" instructions in the text section. Literals are grouped into pools following .literal_position directives or preceding "ENTRY" instructions. These options only affect literals referenced via PC-relative "L32R" instructions; literals for absolute mode "L32R" instructions are handled separately. ✨
  • --auto-litpools / --no-auto-litpools — control the treatment of literal pools. The default is --no-auto-litpools, which in the absence of --text-section-literals places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With --auto-litpools, the literals are interspersed in the text section in order to keep them as close as possible to their references, explicit .literal_position directives are not required. This may be necessary for very large functions, where single literal pool at the beginning of the function may not be reachable by "L32R" instructions at the end. These options only affect literals referenced via PC-relative "L32R" instructions; literals for absolute mode "L32R" instructions are handled separately. When used together with --text-section-literals, --auto-litpools takes precedence. 🧚
  • --absolute-literals / --no-absolute-literals — indicate to the assembler whether "L32R" instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute "L32R" relocations. Otherwise, only the PC-relative "L32R" relocations can be used. 🧭
  • --target-align / --no-target-align — enable or disable automatic alignment to reduce branch penalties at some expense in code size. This optimization is enabled by default. Note that the assembler will always align instructions like "LOOP" that have fixed alignment requirements. 📐
  • --longcalls / --no-longcalls — enable or disable transformation of call instructions to allow calls across a greater range of addresses. This option should be used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. The default is --no-longcalls. 📞
  • --transform / --no-transform — enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The default is --transform; --no-transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source. Using --no-transform causes out of range instruction operands to be errors. 💀
  • --rename-section oldname=newname — renames the section called oldname to newname. Bestie you can stack this one as many times as you want to rename a whole bunch of sections at once 💅
  • --trampolines, --no-trampolines — turns on (or off) the transformation of jump instructions so jumps can reach across a bigger range of addresses. Use this when your jump targets could potentially be out of range 🎯. If you don't have any jumps like that, it literally doesn't touch your code size or performance, no cap. The default is --trampolines.
  • --abi-windowed, --abi-call0 — picks which ABI tag gets written into the ".xtensa.info" section. That ABI tag is basically the ✨vibe check✨ of your assembly code's ABI. The linker will throw a warning if you try to link object files whose ABI tags don't match up 😭. The default ABI is chosen by the Xtensa core configuration, so it's not even your call unless you make it your call.

The following options are available when as is configured for an Z80 processor. 🫶

@chapter Z80 Dependent Features

🎀 Command-line Options 🎀

  • -march=CPU[-EXT...][+EXT...] — tells the assembler which processor you're targeting. If you try to assemble an instruction that won't actually run on that processor, the assembler will hit you with an error message 🔥. These are the processor names it recognizes: "z80", "z180", "ez80", "gbz80", "z80n", "r800".

And plot twist: on top of the basic instruction set, the assembler can be told to accept some extension mnemonics. For example, -march=z180+sli+infc extends z180 with SLI instructions and IN F,(C). These are the extensions currently supported:

  • "full" — all known instructions, the whole buffet 🍓
  • "adl" — ADL CPU mode by default, eZ80 only
  • "sli" — the instruction known as SLI, SLL or SL1
  • "xyhl" — instructions with halves of index registers: IXL, IXH, IYL, IYH
  • "xdcb" — instructions like RotOp (II+d),R and BitOp n,(II+d),R
  • "infc" — the instruction IN F,(C) or IN (C)
  • "outc0" — the instruction OUT (C),0

Ok so here's the galaxy-brain part 🧠✨: instead of extending a basic instruction set, extension mnemonics starting with - revoke the respective functionality. So -march=z80-full+xyhl first removes all default extensions and then adds support for index register halves only. It's giving subtraction, but for features.

If you don't specify this option at all, -march=z80+xyhl+infc is assumed. That's the default, periodt.

  • -local-prefix= prefix — marks all labels with the specified prefix as local. But bestie, such a label can still be marked global explicitly in the code, so it's not a trap 💅. Also this option does not change the default local label prefix ".L" — it just adds a new one on top. More local labels, more fun.
  • -colonless — accepts colonless labels. Every symbol at the beginning of a line gets treated as a label. No colon, no problem 🦋.
  • -sdcc — accepts assembler code produced by SDCC. Iconic collab fr fr.
  • -fp-s= FORMAT — the format for single precision floating point numbers. Default: ieee754 (32 bit).
  • -fp-d= FORMAT — the format for double precision floating point numbers. Default: ieee754 (64 bit). Double the precision, double the drama 🌸.

💖 SEE ALSO 💖

gcc(1), ld(1), and the Info entries for binutils and ld. Go read those too, they're lowkey required reading 👑

Copyright (c) 1991-2025 Free Software Foundation, Inc.

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".

Real talk: that license paragraph is not a suggestion, bestie. It's the actual deal. Reproduce it properly, and don't go adding invariant sections or cover texts unless the license says you can 🙈

And that's the whole page, start to finish 🎀 This one's binutils-2.45.1, dated 2026-01-23, and no I will not be normal about it — go assemble something iconic 💜

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