AS(1)
💖 AS(1) 💖
GNU Development Tools — okay bestie, this is AS(1), aka the portable GNU assembler, and we are going to get through this together. 🫶✨
🎀 NAME 🎀
AS - the portable GNU assembler. 💅
✨ SYNOPSIS ✨
okay so here's the whole invocation menu, and yes it's giving "too many options" but we love her. no cap, just breathe and read the code block. 🦋
as [-a[cdghilns][=file]]
[--alternate]
[--compress-debug-sections] [--nocompress-debug-sections]
[-D]
[--dump-config]
[--debug-prefix-map old=new]
[--defsym sym=val]
[--elf-stt-common=[no|yes]]
[--emulation=name]
[-f]
[-g] [--gstabs] [--gstabs+]
[--gdwarf-<N>] [--gdwarf-sections]
[--gdwarf-cie-version=VERSION]
[--generate-missing-build-notes=[no|yes]]
[--gsframe] [--gsframe=[no|yes]]
[--gsframe-3]
[--hash-size=N]
[--help] [--target-help]
[--info] [--no-info]
[-I dir]
[-J]
[-K]
[--keep-locals]
[-L]
[--listing-lhs-width=NUM]
[--listing-lhs-width2=NUM]
[--listing-rhs-width=NUM]
[--listing-cont-lines=NUM]
[--multibyte-handling=[allow|warn|warn-sym-only]]
[--no-pad-sections]
[-o objfile] [-R]
[--scfi=experimental]
[--sectname-subst]
[--size-check=[error|warning]]
[--statistics]
[-v] [--verbose]
[-version] [--version]
[-W] [--no-warn] [--warn] [--fatal-warnings]
[-w] [-x]
[-Z] [@FILE]
[target-options]
[--|files ...]🎯 TARGET 🎯
bestie, this is the target-options part, and it is iconic in the "there are so many architectures" way. every target group is here, exactly as listed. 💀✨
🌸 Target AArch64 options:
[-EB|-EL]
[-mabi=ABI]🦋 Target Alpha options:
[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]🐚 Target ARC options:
[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]🎀 Target ARM options:
[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
-mapcs-reentrant]
[-mthumb-interwork] [-k]🧚 Target Blackfin options:
[-mcpu=processor[-sirevision]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]🍓 Target BPF options:
[-EL] [-EB]💜 Target CRIS options:
[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
[--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]🌈 Target C-SKY options:
[-march=arch] [-mcpu=cpu]
[-EL] [-mlittle-endian] [-EB] [-mbig-endian]
[-fpic] [-pic]
[-mljump] [-mno-ljump]
[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
[-mnolrw ] [-mno-lrw]
[-melrw] [-mno-elrw]
[-mlaf ] [-mliterals-after-func]
[-mno-laf] [-mno-literals-after-func]
[-mlabr] [-mliterals-after-br]
[-mno-labr] [-mnoliterals-after-br]
[-mistack] [-mno-istack]
[-mhard-float] [-mmp] [-mcp] [-mcache]
[-msecurity] [-mtrust]
[-mdsp] [-medsp] [-mvdsp]⭐ Target D10V options:
[-O]🔥 Target D30V options:
[-O|-n|-N]💖 Target EPIPHANY options:
[-mepiphany|-mepiphany16]🌸 Target H8/300 options:
[-h-tick-hex]🎯 Target i386 options:
[--32|--x32|--64] [-n]
[-march=CPU[+EXTENSION...]] [-mtune=CPU]🛸 Target IA-64 options:
[-mconstant-gp|-mauto-pic]
[-milp32|-milp64|-mlp64|-mp64]
[-mle|mbe]
[-mtune=itanium1|-mtune=itanium2]
[-munwind-check=warning|-munwind-check=error]
[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
[-x|-xexplicit] [-xauto] [-xdebug]🫶 Target IP2K options:
[-mip2022|-mip2022ext]🧁 Target M32C options:
[-m32c|-m16c] [-relax] [-h-tick-hex]🎀 Target M32R options:
[--m32rx|--[no-]warn-explicit-parallel-conflicts|
--W[n]p]👑 Target M680X0 options:
[-l] [-m68000|-m68010|-m68020|...]🦋 Target M68HC11 options:
[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branches] [--short-branches]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]🌈 Target MCORE options:
[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]🧚 Target Meta options: / Target MICROBLAZE options:
yes bestie, the original literally glued Target MICROBLAZE options: onto this line, so here it is, preserved and everything. 💀
[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
[-mlittle-endian] [-mbig-endian]💅 Target MIPS options:
[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot [-mvxworks-pic]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-mfp64] [-mgp64] [-mfpxx]
[-modd-spreg] [-mno-odd-spreg]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
[-mips64r3] [-mips64r5] [-mips64r6]
[-construct-floats] [-no-construct-floats]
[-mignore-branch-isa] [-mno-ignore-branch-isa]
[-mnan=encoding]
[-trap] [-no-break] [-break] [-no-trap]
[-mips16] [-no-mips16]
[-mmips16e2] [-mno-mips16e2]
[-mmicromips] [-mno-micromips]
[-msmartmips] [-mno-smartmips]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdsp] [-mno-dsp]
[-mdspr2] [-mno-dspr2]
[-mdspr3] [-mno-dspr3]
[-mmsa] [-mno-msa]
[-mxpa] [-mno-xpa]
[-mmt] [-mno-mt]
[-mmcu] [-mno-mcu]
[-mcrc] [-mno-crc]
[-mginv] [-mno-ginv]
[-mloongson-mmi] [-mno-loongson-mmi]
[-mloongson-cam] [-mno-loongson-cam]
[-mloongson-ext] [-mno-loongson-ext]
[-mloongson-ext2] [-mno-loongson-ext2]
[-minsn32] [-mno-insn32]
[-mfix7000] [-mno-fix7000]
[-mfix-rm7000] [-mno-fix-rm7000]
[-mfix-vr4120] [-mno-fix-vr4120]
[-mfix-vr4130] [-mno-fix-vr4130]
[-mfix-r5900] [-mno-fix-r5900]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]🍓 Target MMIX options:
[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]🦄 Target NDS32 options:
[-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
[-misa=isa] [-mabi=abi] [-mall-ext]
[-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
[-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
[-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
[-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
[-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
[-mb2bb]🎀 Target PDP11 options:
[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]🌸 Target picoJava options:
[-mb|-me]🔥 Target PowerPC options:
[-a32|-a64]
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
-m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
-mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
-me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
-mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
-mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
[-many] [-maltivec|-mvsx|-mhtm|-mvle]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
[-nops=count]🫶 Target PRU options:
[-link-relax]
[-mnolink-relax]
[-mno-warn-regname-label]💜 Target RISC-V options:
[-fpic|-fPIC|-fno-pic]
[-march=ISA|Profiles|Profiles_ISA]
[-mabi=ABI]
[-mlittle-endian|-mbig-endian]🧚 Target RL78 options:
[-mg10]
[-m32bit-doubles|-m64bit-doubles]🌈 Target RX options:
[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]👑 Target s390 options:
[-m31|-m64] [-mesa|-mzarch] [-march=CPU]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]
[-mwarn-regtype-mismatch=strict
-mwarn-regtype-mismatch=relaxed
-mwarn-regtype-mismatch=no
-mno-warn-regtype-mismatch]🍓 Target SCORE options:
[-EB][-EL][-FIXDD][-NWARN]
[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
[-march=score7][-march=score3]
[-USE_R1][-KPIC][-O0][-G num][-V]⭐ Target SPARC options:
[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
-Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
-Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
-Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
-Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
-Asparcvisr|-Asparc5]
[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
-xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
-xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
-xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
-xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
-xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
-bump]
[-32|-64]
[--enforce-aligned-data][--dcti-couples-detect]🎀 Target TIC54X options:
[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]🦋 Target TIC6X options:
[-march=arch] [-mbig-endian|-mlittle-endian]
[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
[-mpic|-mno-pic]🧁 Target TILE-Gx options:
[-m32|-m64][-EB][-EL]🌸 Target Visium options:
[-mtune=arch]🧚 Target Xtensa options:
[--[no-]text-section-literals] [--[no-]auto-litpools]
[--[no-]absolute-literals]
[--[no-]target-align] [--[no-]longcalls]
[--[no-]transform]
[--rename-section oldname=newname]
[--[no-]trampolines]
[--abi-windowed|--abi-call0]💅 Target Z80 options:
[-march=CPU[-EXT][+EXT]]
[-local-prefix=PREFIX]
[-colonless]
[-sdcc]
[-fp-s=FORMAT]
[-fp-d=FORMAT]💅 DESCRIPTION 💅
okay so first things first: GNU as is literally not one assembler, it's a whole family of assemblers 💖. The way that if you've used the GNU assembler on one architecture, you'll find a pretty similar environment when you use it on another one — that's the whole vibe. Every version has a ton in common with the others, including object file formats, most assembler directives (which people usually call pseudo-ops, iykyk), and the assembler syntax. Sisterhood of the traveling assembler, honestly.
as is primarily intended to assemble the output of the GNU C compiler gcc so the linker ld can use it. That's its main character job. But bestie, they've tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly, no cap. This does not mean as always uses the same syntax as another assembler for the same architecture — for example, we know of several incompatible versions of 680x0 assembly language syntax. Chaos, but documented chaos 🫶.
Every single time you run as, it assembles exactly one source program. Periodt. And that source program is made up of one or more files. (Yes, the standard input counts as a file too, she's inclusive like that ✨.)
You give as a command line that has zero or more input file names. The input files get read left file name to right, like reading a group chat in order. A command-line argument (in any position) that has no special meaning is taken to be an input file name. Simple as that.
If you give as no file names at all, it attempts to read one input file from standard input, which is normally your terminal. You may have to type ctl-D to tell as there's no more program to assemble. (Iconic "I'm done talking" signal 💀.)
Use -- if you need to explicitly name the standard input file in your command line. Like, "no fr actually the file is stdin, bestie."
If the source is empty, as produces a small, empty object file. A little empty vessel. Lowkey poetic 🌸.
as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically — that's the rule. Warnings report an assumption made so that as could keep assembling a flawed program. Errors report a grave problem that stops the assembly. So: warning = "we vibed through it", error = "we're done here" 😭.
If you're invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the -Wa) by commas. For example:
gcc -c -g -O -Wa,-alh,-L file.cThis passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table). Look at her go 💅.
Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.) So like, you can peek behind the curtain if you're nosy 🧚.
✨ OPTIONS ✨
@file— read command-line options from file. The options read are inserted in place of the original@fileoption. If file does not exist, or cannot be read, then the option will be treated literally, and not removed. Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional@fileoptions; any such options will be processed recursively. It's giving inception 🌀.-a[cdghilmns]— turn on listings, in any of a variety of ways:-ac— omit false conditionals-ad— omit debugging directives-ag— include general information, likeasversion and options passed-ah— include high-level source-al— include assembly-ali— include assembly with ginsn-am— include macro expansions-an— omit forms processing-as— include symbols=file— set the name of the listing file
You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls. Combo meal energy 🍓.
--alternate— begin in alternate macro mode.--compress-debug-sections— compress DWARF debug sections using zlib withSHF_COMPRESSEDfrom the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities. Note: if compression would make a given section larger then it is not compressed. She's not gonna make things worse, she has standards 💖.--compress-debug-sections=none,--compress-debug-sections=zlib,--compress-debug-sections=zlib-gnu,--compress-debug-sections=zlib-gabi,--compress-debug-sections=zstd— these options control how DWARF debug sections are compressed.--compress-debug-sections=noneis equivalent to--nocompress-debug-sections.--compress-debug-sections=zliband--compress-debug-sections=zlib-gabiare equivalent to--compress-debug-sections.--compress-debug-sections=zlib-gnucompresses DWARF debug sections using the obsoleted zlib-gnu format. The debug sections are renamed to begin with.zdebug.--compress-debug-sections=zstdcompresses DWARF debug sections using zstd.
Note: if compression would actually make a section larger, then it is not compressed nor renamed. Respect the size queen logic 🌈.
--nocompress-debug-sections— do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.-D— enable debugging in target specific backends, if supported. Otherwise ignored. Even if ignored, this option is accepted for script compatibility with calls to other assemblers. She's flexible, she's a team player 🫶.--debug-prefix-map old=new— when assembling files in directory old, record debugging information describing them as in new instead.--defsym sym=value— define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading0xindicates a hexadecimal value, and a leading0indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a.setpseudo-op.--dump-config— displays how the assembler is configured and then exits. Show-off behavior, honestly 👑.--elf-stt-common=no,--elf-stt-common=yes— these options control whether the ELF assembler should generate common symbols with theSTT_COMMONtype. The default can be controlled by a configure option--enable-elf-stt-common.--emit-local-absolute— emit even pre-defined (local) absolute symbols to the outgoing symbol table. Note that this isn't the exact opposite of--strip-local-absolute. Not me pointing out the nuance 💀.--emulation=name— if the assembler is configured to support multiple different target configurations then this option can be used to select the desired form.-f— "fast" — skip whitespace and comment preprocessing (assume source is compiler output). Zoom zoom ⭐.-g,--gen-debug— generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a.debug_infoand.debug_linesection is only emitted when the assembly file doesn't generate one itself.--gstabs— generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.--gstabs+— generate stabs debugging information for each assembler line, with GNU extensions that probably onlygdbcan handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time. > Risky flex, bestie — other debuggers might literally crash out 😭.--gdwarf-2— generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note — this option is only supported by some targets, not all of them.--gdwarf-3— this option is the same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis. She said "maybe", not "yes" 💅.--gdwarf-4— this option is the same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.--gdwarf-5— this option is the same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.--gdwarf-sections— instead of creating a.debug_linesection, create a series of.debug_line.foosections where foo is the name of the corresponding code section. For example a code section called.text.funcwill have its dwarf line number information placed into a section called.debug_line.text.func. If the code section is just called.textthen debug line section will still be called just.debug_linewithout any suffix. Organized queen 🎀.--gdwarf-cie-version=version— control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specified the default is version 1, though some targets can modify this default. Other possible values for version are3or4.--generate-missing-build-notes=yes,--generate-missing-build-notes=no— these options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the--enable-generate-build-notesconfigure option.--gsframe,--gsframe,--gsframe=no,--gsframe=yes— create.sframesection from CFI directives. The explicit--gsframe=yesoption behaves the same as--gsframe. Generation can be suppressed with--gsframe=no. The default can be controlled by a configure option--enable-default-sframe. The current version of the emitted SFrame stack trace data isSFRAME_VERSION_3. (Yes,--gsframeis listed twice up there — she's just like that 🙈.)--gsframe-3— generate SFrame stack trace information as per Version 3 of the specification.--hash-size N— ignored. Supported for command line compatibility with other assemblers. She's literally just here to be polite 💀.--help— print a summary of the command-line options and exit. Your emotional support flag 🦋.--target-help— prints a lil summary of all target specific options and then exits. 💅--info— don’t suppress informational messages. Let the info breathe. 🫶--no-info— suppress informational messages. shhh. 🤫-Idir — add directory dir to the search list for.includedirectives. 🎀-J— don’t warn about signed overflow. not a peep. 💛-K— issue warnings when difference tables altered for long displacements. heads up energy. 🍑-L,--keep-locals— keep local symbols in the symbol table. These symbols start with system-specific local label prefixes, typically.Lfor ELF systems orLfor traditional a.out systems. 🧚--listing-lhs-width=number— set the maximum width, in words, of the output data column for an assembler listing to number. ✨--listing-lhs-width2=number— set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number. 🌸--listing-rhs-width=number— set the maximum width of an input source line, as displayed in a listing, to number bytes. 🦋--listing-cont-lines=number— set the maximum number of lines printed in a listing for a single line of input to number + 1. 🎀--multibyte-handling=allow,--multibyte-handling=warn,--multibyte-handling=warn-sym-only,--multibyte-handling=warn_sym_only— controls how the assembler handles multibyte characters in the input. The default (which can be restored by using theallowargument) is to allow such characters without complaint. Using thewarnargument will make the assembler generate a warning message whenever any multibyte character is encountered. Using thewarn-sym-onlyargument will only cause a warning to be generated when a symbol is defined with a name that contains multibyte characters. (References to undefined symbols will not generate a warning). 🌈--no-pad-sections— stop the assembler from padding the ends of output sections to the alignment of that section. The default is to pad the sections, but this can waste space which might be needed on targets which have tight memory constraints. space is precious, bestie. 💀-oobjfile — name the object-file output fromasobjfile. 💖-R— fold the data section into the text section. 🫶--reduce-memory-overheads— ignored. Supported for compatibility with tools that pass the same option to both the assembler and the linker. it’s just vibing there. 😭--scfi=experimental— controls whether the assembler should synthesize CFI for hand-written input. If the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning. Note that--scfi=experimentalis not intended to be used for compiler-generated code, including inline assembly. This experimental support is work in progress. Only System V AMD64 ABI is supported. Each input function in assembly must begin with the.typedirective, and should ideally be closed off using a.sizedirective. When using SCFI, each.typedirective promptsGASto start a new FDE (a.k.a., Function Descriptor Entry). This implies that with each.typedirective, a previous block of instructions, if any, is finalised as a distinct FDE. 🧪--sectname-subst— honor substitution sequences in section names. ✨--size-check=error,--size-check=warning— issue an error or warning for invalid ELF.sizedirective. pick your consequence. 🍑--statistics— print the maximum space (in bytes) and total time (in seconds) used by assembly. numbers girlies rise. 📊--strip-local-absolute— remove local absolute symbols from the outgoing symbol table. 🧹-v,--verbose— print theasversion. 💅--version,-version— print theasversion and exit. 👑-W,--no-warn— suppress warning messages. quiet luxury. 🤫--warn— don’t suppress warning messages or treat them as errors. let them speak. 💛--fatal-warnings— treat warnings as errors. no warnings allowed, periodt. 💀-w— ignored. 🙈-x— ignored. 🙈-Z— generate an object file even after errors. resilient queen. 👑-- | files ...— standard input, or source files to assemble. 🎀
The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). 🧚
-EB— this option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. big-endian branch. 🦋-EL— this option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. little-endian luv. 🌸-mabi=abi— specify which ABI the source code uses. The recognized arguments are:"ilp32"and"lp64", which decides the generated object file in ELF32 and ELF64 format respectively. The default is"lp64". 💖-mcpu=processor[+extension...]— this option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized:"cortex-a34","cortex-a35","cortex-a53","cortex-a55","cortex-a57","cortex-a65","cortex-a65ae","cortex-a72","cortex-a73","cortex-a75","cortex-a76","cortex-a76ae","cortex-a77","cortex-a78","cortex-a78ae","cortex-a78c","cortex-a510","cortex-a520","cortex-a710","cortex-a720","ares","exynos-m1","falkor","neoverse-n1","neoverse-n2","neoverse-e1","neoverse-v1","qdf24xx","saphira","thunderx","vulcan","xgene1" "xgene2","cortex-r82","cortex-x1","cortex-x2","cortex-x3", and"cortex-x4". The special name"all"may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions. ✨
In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor. 🎀
If some implementations of a particular processor can have an extension, then then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions. 🫶
-march=architecture[+extension...]— this option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized:"armv8-a","armv8.1-a","armv8.2-a","armv8.3-a","armv8.4-a""armv8.5-a","armv8.6-a","armv8.7-a","armv8.8-a","armv8.9-a","armv8-r","armv9-a","armv9.1-a","armv9.2-a","armv9.3-a","armv9.4-a"and"armv9.5-a". 🌈
If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assembler will default to -mcpu=all. 💅
The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu, extensions are not always enabled by default. 🌸
-mbig-obj— on PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. big object energy. 👑-mverbose-error— this option enables verbose error messages for AArch64 gas. This option is enabled by default. talkative by default. 🗣️-mno-verbose-error— this option disables verbose error messages in AArch64 gas. 🤫-menable-sysreg-checking— this option enables error messages that are issued if an attempt is made to assemble a system register access which will not execute on the target architecture. 🧚
The following options are available when as is configured for an Alpha processor. 💜
-mcpu— this option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the.archdirective. 🎀
The following processor names are recognized: 21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6", "ev67", "ev68". The special name "all" may be used to allow the assembler to accept instructions valid for any Alpha processor. ✨
In order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. "ev4") do not. 🦋
-mdebug,-no-mdebug— enables or disables the generation of.mdebugencapsulation for stabs directives and procedure descriptors. The default is to automatically enable.mdebugwhen the first stabs directive is seen. 🌸-relax— this option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications. 🫶-replace,-noreplace— enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets and-replaceis the default. See section 1.4.1 of the OpenVMS Linker Utility Manual. 💖-g— this option is used when the compiler generates debug information. Whengccis usingmips-tfileto generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect. 🧚-Gsize— a local common symbol larger than size is placed in.bss, while smaller symbols are placed in.sbss. size matters, bestie. 💛-F,-32addr— these options are ignored for backward compatibility. 😭
The following options are available when as is configured for an ARC processor. 🦋
-mcpu=cpu— this option selects the core processor variant. 💅-EB|-EL— select either big-endian (-EB) or little-endian (-EL) output. 🌈-mcode-density— enable Code Density extension instructions. ✨
The following options are available when as is configured for the ARM processor family. 🌸
-mcpu=processor[+extension...]— specify which ARM processor variant is the target. 🎀-march=architecture[+extension...]— specify which ARM architecture variant is used by the target. 🦋-mfpu=floating-point-format— select which Floating Point architecture is the target. 💖-mfloat-abi=abi— select which floating point ABI is in use. ✨-mthumb— enable Thumb only instruction decoding. 👑-mapcs-32|-mapcs-26|-mapcs-float|-mapcs-reentrant— picks which procedure calling convention we're living in 💫 that's it, that's the whole vibe check.-EB|-EL— endianness moment:-EBgives you big-endian output,-ELgives you little-endian output. pick your fighter 🫶-mthumb-interwork— says, out loud, that the code was generated with interworking between Thumb and ARM code in mind. it's giving "we planned ahead" energy ✨-mccs— turns on CodeComposer Studio assembly syntax compatibility mode. blast from the past behavior ngl 💅-k— declares that PIC code has been generated. short king option, one letter, no notes 👑
The following options are available when as is configured for the Blackfin processor family.
-mcpu=processor[-sirevision]— specifies the target processor. the optional sirevision is not used in the assembler — it's literally just here so GCC can easily pass down its-mcpu=option 🙈 the assembler will throw an error message if you try to assemble an instruction that won't execute on the target processor. recognized processor names, get ready:
bf504, bf506, bf512, bf514, bf516, bf518, bf522, bf523, bf524,
bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf535 (not implemented yet),
bf536, bf537, bf538, bf539, bf542, bf542m, bf544, bf544m, bf547, bf547m,
bf548, bf548m, bf549, bf549m, bf561, and bf592-mfdpic— assemble for the FDPIC ABI.-mno-fdpic,-mnopic— disable-mfdpic. that's the whole job 🎀
The following options are available when as is configured for the Linux kernel BPF processor family.
@chapter BPF Dependent Features💜 BPF Options
-EB— this option specifies that the assembler should emit big-endian eBPF.-EL— and this one says emit little-endian eBPF. pick your endianness, bestie 🦋-mdialect=dialect— specifies the assembly language dialect to recognize while assembling. the assembler supportsnormalandpseudoc.-misa-spec=spec— specifies the version of the BPF instruction set to use when assembling. the BPF ISA versions supported arev1v2,v3andv4.
you can also pass the value xbpf to recognize extra instructions that are used by GCC for testing purposes — but beware, this is not valid BPF 💀
-mno-relax— tells the assembler to not relax instructions. unclench. do not relax. 😌
Note that if no endianness option is specified in the command line, the host endianness is used. See the info pages for documentation of the CRIS-specific options. 📖
The following options are available when as is configured for the C-SKY processor family.
-march=archname— assemble for architecture archname. the--helpoption lists valid values for archname 👀-mcpu=cpuname— assemble for architecture cpuname. and yes,--helplists valid values for cpuname too, iykyk.-EL,-mlittle-endian— generate little-endian output.-EB,-mbig-endian— generate big-endian output.-fpic,-pic— generate position-independent code. we love a relocatable icon ✨-mljump,-mno-ljump— enable/disable transformation of the short branch instructionsjbf,jbt, andjbrtojmpi. this option is for V2 processors only. it's ignored on CK801 and CK802 targets, which do not support thejmpiinstruction, and it's enabled by default for other processors 🎀-mbranch-stub,-mno-branch-stub— pass throughR_CKCORE_PCREL_IMM26BY2relocations forbsrinstructions to the linker.
this option is only available for bare-metal C-SKY V2 ELF targets, where it's enabled by default. it cannot be used in code that will be dynamically linked against shared libraries 🚨
-force2bsr,-mforce2bsr,-no-force2bsr,-mno-force2bsr— enable/disable transformation ofjbsrinstructions tobsr. this option is always enabled (and-mno-force2bsris ignored) for CK801/CK802 targets. it's also always enabled when-mbranch-stubis in effect. no takebacks 💅-jsri2bsr,-mjsri2bsr,-no-jsri2bsr,-mno-jsri2bsr— enable/disable transformation ofjsriinstructions tobsr. enabled by default, as a treat 🌸-mnolrw,-mno-lrw— enable/disable transformation oflrwinstructions into amovih/oripair.-melrw,-mno-elrw— enable/disable extendedlrwinstructions. this one's enabled by default for CK800-series processors 💖-mlaf,-mliterals-after-func,-mno-laf,-mno-literals-after-func— enable/disable placement of literal pools after each function.-mlabr,-mliterals-after-br,-mno-labr,-mnoliterals-after-br— enable/disable placement of literal pools after unconditional branches. enabled by default! 🦋-mistack,-mno-istack— enable/disable interrupt stack instructions. enabled by default on CK801, CK802, and CK802 processors 🙈
The following options explicitly enable certain optional instructions. These features are also enabled implicitly by using -mcpu= to specify a processor that supports it. (cute little shortcut, tbh 🫶)
-mhard-float— enable hard float instructions.-mmp— enable multiprocessor instructions.-mcp— enable coprocessor instructions.-mcache— enable cache prefetch instruction.-msecurity— enable C-SKY security instructions.-mtrust— enable C-SKY trust instructions.-mdsp— enable DSP instructions.-medsp— enable enhanced DSP instructions.-mvdsp— enable vector DSP instructions. go off vector DSP ✨
The following options are available when as is configured for an Epiphany processor.
-mepiphany— specifies that both 32 and 16 bit instructions are allowed. this is the default behavior, so like, it's already serving 💅-mepiphany16— restricts the permitted instructions to just the 16 bit set. small but mighty energy 🎀
The following options are available when as is configured for an H8/300 processor.
@chapter H8/300 Dependent Features🌸 Options
The Renesas H8/300 version of as has one machine-dependent option:
-h-tick-hex— supportH'00style hex constants in addition to0x00style. both vibes welcome 🤝-mach=name— sets the H8300 machine variant. recognized machine names:h8300h,h8300hn,h8300s,h8300sn,h8300sxandh8300sxn.
The following options are available when as is configured for an i386 processor.
--32|--x32|--64— selects the word size, either 32 bits or 64 bits.--32implies Intel i386 architecture, while--x32and--64imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.
⚠️ these options are only available with the ELF object file format, and they require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform). so like, check your build first bestie 😭
-n— by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such asleal 0(%esi,1),%esi. this switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment. tiny flag, big consequences 💀--divide— on SVR4-derived platforms, the character/is treated as a comment character, which means it cannot be used in expressions. the--divideoption turns/into a normal character. this does not disable/at the beginning of a line starting a comment, or affect using#for starting a comment./stays booked and busy in some contexts, sorry 🫠-march=CPU[+EXTENSION...]— specifies the target processor. the assembler will issue an error message if you try to assemble an instruction which will not execute on the target processor. recognized processor names:
i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro,
pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7,
iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3,
bdver4, znver1, znver2, znver3, znver4, znver5, znver6, btver1, btver2,
generic32 and generic64in addition to the basic instruction set, the assembler can be told to accept various extension mnemonics. for example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. the following extensions are currently supported:
8087, 287, 387, 687, "cmov", "fxsr", "mmx", "sse", "sse2", "sse3",
"sse4a", "ssse3", "sse4.1", "sse4.2", "sse4", "avx", "avx2", "lahf_sahf",
"monitor", "adx", "rdseed", "prfchw", "smap", "mpx", "sha", "rdpid",
"ptwrite", "cet", "gfni", "vaes", "vpclmulqdq", "prefetchwt1",
"clflushopt", "se1", "clwb", "movdiri", "movdir64b", "enqcmd",
"serialize", "tsxldtrk", "kl", "widekl", "hreset", "avx512f", "avx512cd",
"avx512er", "avx512pf", "avx512vl", "avx512bw", "avx512dq", "avx512ifma",
"avx512vbmi", "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq",
"avx512_vbmi2", "avx512_vnni", "avx512_bitalg", "avx512_vp2intersect",
"tdx", "avx512_bf16", "avx_vnni", "avx512_fp16", "avx512_bmm",
"prefetchi", "avx_ifma", "avx_vnni_int8", "cmpccxadd", "wrmsrns",
"msrlist", "avx_ne_convert", "rao_int", "fred", "lkgs", "avx_vnni_int16",
"sha512", "sm3", "sm4", "pbndkb", "avx10.1", "avx10.1/512",
"avx10.1/256", "avx10.1/128", "user_msr", "msr_imm", "apx_f", "apx_nci",
"apx_ndd", "apx_nf", "apx_nci_ndd_nf", "avx10.2", "avx10.2/512",
"avx10.2/256", "avx10.2/128", "movrs", "amx_int8", "amx_bf16",
"amx_fp16", "amx_complex", "amx_transpose", "amx_tf32", "amx_fp8"
"amx_movrs", "amx_avx512", "amx_tile", "vmx", "vmfunc", "smx", "xsave",
"xsaveopt", "xsavec", "xsaves", "aes", "pclmul", "fsgsbase", "rdrnd",
"f16c", "bmi2", "fma", "movbe", "ept", "lzcnt", "popcnt", "hle", "rtm",
"tsx", "invpcid", "clflush", "mwaitx", "clzero", "wbnoinvd", "pconfig",
"waitpkg", "uintr", "cldemote", "rdpru", "mcommit", "sev_es", "lwp",
"fma4", "xop", "cx16", "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a",
"sse5", "snp", "invlpgb", "tlbsync", "rmpquery", "rmpread", "svme",
"gmism2", "gmiccs", "padlockrng2", "padlockphe2", "padlockxmodx" and
"padlock"💡 note that these extension mnemonics can be prefixed withnoto revoke the respective (and any dependent) functionality. note further that the suffixes permitted on-march=avx10.<N>enforce a vector length restriction — i.e. despite these otherwise being "enabling" options, using these suffixes will disable all insns with wider vector or mask register operands. sneaky little plot twist 😭
when the .arch directive is used with -march, the .arch directive will take precedent. .arch said "i'm the main character" and honestly? fair 👑
-mtune=CPU— tells the assembler which processor to optimize for 🎯. When you use it with-march, only instructions from the processor named in-marchget generated. ValidCPUvalues are literally the same list as-march=CPU, no extras, no surprises.-moperand-check=none,-moperand-check=warning,-moperand-check=error— these three control whether the assembler checks certain instruction operands or operand combos 👀. Example of the kind of thing it's checking: an instruction where the operand size can't be figured out from the operands and nobody specified it with an instruction suffix. So:-moperand-check=none— assembler does not do these checks.-moperand-check=warning— assembler throws a warning when the checks fail. this is the default ✨-moperand-check=error— assembler throws an error when the checks fail. no warnings, we're serious now 💅
-msse2avx— tells the assembler to encode SSE instructions with a VEX prefix, which means AVX needs to be available. And SSE instructions that use extended GPRs get encoded with an EVEX prefix, which needs AVX512 or AVX10 to be available. like, it's upgrading the encoding but also the requirements, bestie 🦋-muse-unaligned-vector-move— tells the assembler to encode an aligned vector move as an unaligned vector move. that's it, that's the whole vibe 🎀-msse-check=none,-msse-check=warning,-msse-check=error— controls whether the assembler checks SSE instructions:-msse-check=none— no SSE checking at all. default behavior 🙈-msse-check=warning— warning for any SSE instruction.-msse-check=error— error for any SSE instruction.
-mavxscalar=128,-mavxscalar=256— controls how scalar AVX instructions get encoded:-mavxscalar=128— encode scalar AVX instructions with 128-bit vector length. default ⭐-mavxscalar=256— encode scalar AVX instructions with 256-bit vector length.
WARNING: don't use this for production code — because of CPU errata, the resulting code may not work on certain models. not a vibe, fr fr 😭
-mvexwig=0,-mvexwig=1— controls how the assembler encodes VEX.W-ignored (WIG) VEX instructions:-mvexwig=0— encode WIG VEX instructions withvex.w = 0. default 💜-mvexwig=1— encode WIG EVEX instructions withvex.w = 1.
WARNING: again, not for production code — CPU errata means the resulting code may not work on certain models. same energy, same caution 💀
-mevexlig=128,-mevexlig=256,-mevexlig=512— controls how length-ignored (LIG) EVEX instructions get encoded:-mevexlig=128— encode LIG EVEX instructions with 128-bit vector length. default 🌸-mevexlig=256— 256-bit vector length.-mevexlig=512— 512-bit vector length.
-mevexwig=0,-mevexwig=1— controls how w-ignored (WIG) EVEX instructions get encoded:-mevexwig=0— encode WIG EVEX instructions withevex.w = 0. default 🫶-mevexwig=1— encode WIG EVEX instructions withevex.w = 1.
-mmnemonic=att,-mmnemonic=intel— specifies which instruction mnemonic to use when matching instructions. heads up though: the.att_mnemonicand.intel_mnemonicdirectives take precedent over this 👑-msyntax=att,-msyntax=intel— specifies the instruction syntax used when processing instructions. and again: the.att_syntaxand.intel_syntaxdirectives take precedent 🙌-mnaked-reg— says registers don't need a%prefix. and yep, you guessed it: the.att_syntaxand.intel_syntaxdirectives take precedent 💅-madd-bnd-prefix— forces the assembler to slap a BND prefix on all branches, even when that prefix was never explicitly written in the source code. generous of it honestly 🎀-mno-shared— okay so on ELF targets the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The-msharedoption tells the assembler to generate code that might go into a shared library, where all non-weak global branch targets with default visibility can be preempted — resulting code is slightly bigger. This option only affects the handling of branch instructions, nothing else 🦋-mbig-obj— on PE/COFF targets this forces the use of the big object file format, which allows more than32768sections. big file energy 🔥-momit-lock-prefix=no,-momit-lock-prefix=yes— controls how the assembler encodes the lock prefix:-momit-lock-prefix=yes— omits all lock prefixes.-momit-lock-prefix=no— encodes lock prefix as usual. default ⭐
WARNING: this option is meant as a workaround for processors that fail on the lock prefix. it can only be safely used with single-core, single-thread computers. do not casually drop this into a multithreaded build, bestie 😭
-mfence-as-lock-add=no,-mfence-as-lock-add=yes— controls howlfence,mfenceandsfenceget encoded:-mfence-as-lock-add=yes— encodeslfence,mfenceandsfenceaslock addl $0x0, (%rsp)in 64-bit mode andlock addl $0x0, (%esp)in 32-bit mode.-mfence-as-lock-add=no— encodeslfence,mfenceandsfenceas usual. default 🌈
-mrelax-relocations=no,-mrelax-relocations=yes— controls whether the assembler generates relax relocations:R_386_GOT32Xin 32-bit mode, orR_X86_64_GOTPCRELXandR_X86_64_REX_GOTPCRELXin 64-bit mode.-mrelax-relocations=yes— generates relax relocations.-mrelax-relocations=no— does not generate relax relocations.
-mtls-check=no,-mtls-check=yes— controls whether the assembler checks tls relocation.-mtls-check=yes— checks tls relocation.-mtls-check=no— does not check tls relocation. the default here can be controlled by a configure option,--enable-x86-tls-check👀
-malign-branch-boundary=NUM— controls how the assembler aligns branches, using segment prefixes or NOP.NUMmust be a power of 2, and it should be0or no less than16. Branches get aligned within aNUMbyte boundary.-malign-branch-boundary=0is the default and doesn't align branches at all 💅-malign-branch=TYPE[+TYPE...]— specifies which types of branches to align.TYPEis a combination of:jcc— aligns conditional jumpsfused— aligns fused conditional jumpsjmp— aligns unconditional jumpscall— aligns callsret— aligns retsindirect— aligns indirect jumps and calls
the default is -malign-branch=jcc+fused+jmp ✨
-malign-branch-prefix-size=NUM— the maximum number of prefixes on an instruction, for branch alignment purposes.NUMshould be between0and5, and the defaultNUMis5🎯-mbranches-within-32B-boundaries— aligns conditional jumps, fused conditional jumps and unconditional jumps within a 32 byte boundary, with up to 5 segment prefixes on an instruction. it's exactly equivalent to:
-malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5and the default doesn't align branches 🦋
-mlfence-after-load=no,-mlfence-after-load=yes— controls whether the assembler generateslfenceafter load instructions.-mlfence-after-load=yes— generateslfence.-mlfence-after-load=no— doesn't generatelfence. default 🌸
-mlfence-before-indirect-branch=none,-mlfence-before-indirect-branch=all,-mlfence-before-indirect-branch=register,-mlfence-before-indirect-branch=memory— controls whether the assembler generateslfencebefore indirect near branch instructions:-mlfence-before-indirect-branch=all— generateslfencebefore an indirect near branch via register, and issues a warning before an indirect near branch via memory. it also implicitly sets-mlfence-before-ret=shlwhen there's no explicit-mlfence-before-ret=.-mlfence-before-indirect-branch=register— generateslfencebefore an indirect near branch via register.-mlfence-before-indirect-branch=memory— issues a warning before an indirect near branch via memory.-mlfence-before-indirect-branch=none— generates nolfenceand issues no warning. default 💜
heads up:lfencewon't be generated before an indirect near branch via register when-mlfence-after-load=yesis set, becauselfencegets generated after loading the branch target register anyway 🙈
-mlfence-before-ret=none,-mlfence-before-ret=shl,-mlfence-before-ret=or,-mlfence-before-ret=yes,-mlfence-before-ret=not— controls whether the assembler generateslfencebeforeret:-mlfence-before-ret=or— generatesorinstruction withlfence.-mlfence-before-ret=shl/-mlfence-before-ret=yes— generatesshlinstruction withlfence.-mlfence-before-ret=not— generatesnotinstruction withlfence.-mlfence-before-ret=none— nolfence. default ⭐
-mx86-used-note=no,-mx86-used-note=yes— controls whether the assembler generatesGNU_PROPERTY_X86_ISA_1_USEDandGNU_PROPERTY_X86_FEATURE_2_USEDGNU property notes. the default is controlled by the--enable-x86-used-noteconfigure option 👑-mevexrcig=rne,-mevexrcig=rd,-mevexrcig=ru,-mevexrcig=rz— controls how SAE-only EVEX instructions get encoded:-mevexrcig=rne— encodes the RC bits of the EVEX instruction with00. default 🎀-mevexrcig=rd— encodes with RC bits01.-mevexrcig=ru— encodes with RC bits10.-mevexrcig=rz— encodes with RC bits11.
-mamd64,-mintel64— specifies that the assembler should accept only AMD64 or Intel64 ISA in 64-bit mode. the default is to accept common, Intel64 only and AMD64 ISAs 🦋-O0|-O|-O1|-O2|-Os— bestie, this is the "make the encoding smoller" knob. Optimize instruction encoding with smaller instruction size. 💅
So -O and -O1 encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with 32-bit register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions, encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions, and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical. Lowkey a whole glow-up for your byte count. ✨
-O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions. And okay, 64-bit mode girlies get extra: VEX encoded instructions with commutative source operands will also have their source operands swapped if this allows using the 2-byte VEX prefix form instead of the 3-byte one. Certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST. Not me swapping your operands to save a byte 😭 iconic.
-Os includes -O2 optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. And -O0 turns off this optimization. (Yes, that's the off switch, she's giving minimalism.)
The following options are available when as is configured for the Ubicom IP2K series. 🫶
-mip2022ext— Specifies that the extended IP2022 instructions are allowed. Go off, use the fancy ones.-mip2022— Restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. Back to basics, no cap.
The following options are available when as is configured for the Renesas M32C and M16C processors. 🌸
-m32c— Assemble M32C instructions.-m16c— Assemble M16C instructions (the default). She's the default for a reason 💅-relax— Enable support for link-time relaxations.-h-tick-hex— SupportH'00style hex constants in addition to0x00style. Two aesthetics, both valid ✨
The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series. 🦋
--m32rx— Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX. It's giving character development.--warn-explicit-parallel-conflictsor--Wp— Produce warning messages when questionable parallel constructs are encountered. 👀 "questionable" is doing so much work here.--no-warn-explicit-parallel-conflictsor--Wnp— Do not produce warning messages when questionable parallel constructs are encountered. Ignorance is bliss, I guess 🙈
The following options are available when as is configured for the Motorola 68000 series. 🔥
-l— Shorten references to undefined symbols, to one word instead of two. Efficiency queen.-m68000|-m68008|-m68010|-m68020|-m68030|-m68040|-m68060|-m68302|-m68331|-m68332|-m68333|-m68340|-mcpu32|-m5200— Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time. Pick your fighter, bestie 🎀-m68881|-m68882|-mno-68881|-mno-68882— The target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor. Not the 68000 and the 68881 being an incompatible couple but still making it work via emulation 😭 we love a plot twist.-m68851|-mno-68851— The target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up. MMU girlies rise 🫶
For details about the PDP-11 machine dependent features options, see PDP-11-Options. (Not me pointing you at another page, but like, that's where the lore lives 💀)
-mpic|-mno-pic— Generate position-independent (or position-dependent) code. The default is-mpic. Position-independent is literally the main character of modern code, ngl.-mall-mall-extensions— Enable all instruction set extensions. This is the default. All of them. Every single one. She's greedy and we respect it 👑-mno-extensions— Disable all instruction set extensions. The opposite vibe entirely.-mextension|-mno-extension— Enable (or disable) a particular instruction set extension. You pick the one, she obeys 💅-mcpu— Enable the instruction set extensions supported by a particular CPU, and disable all other extensions. One CPU only, everyone else blocked.-mmachine— Enable the instruction set extensions supported by a particular machine model, and disable all other extensions. Same energy but for a machine model. Periodt.
The following options are available when as is configured for a picoJava processor. 🧚
-mb— Generate "big endian" format output.-ml— Generate "little endian" format output.
Big endian vs little endian, the eternal discourse, we stay neutral ✨
The following options are available when as is configured for a PRU processor. 🌈
-mlink-relax— Assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LD would shorten the LDI32 instruction to a single LDI. In such case "as" will output DIFF relocations for diff expressions.-mno-link-relax— Assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted. The pessimistic timeline, honestly.-mno-warn-regname-label— Do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off. Your C compiler is out here turning off the warning like it's above the rules 💀
The following options are available when as is configured for a MIPS processor. 👑
-G num— This option sets the largest size of an object that can be referenced implicitly with the "gp" register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is8. Only for the ECOFF girlies, iykyk.-EB— Generate "big endian" format output.-EL— Generate "little endian" format output.-mips1-mips2-mips3-mips4-mips5-mips32-mips32r2-mips32r3-mips32r5-mips32r6-mips64-mips64r2-mips64r3-mips64r5-mips64r6— Generate code for a particular MIPS Instruction Set Architecture level.-mips1is an alias for-march=r3000,-mips2is an alias for-march=r6000,-mips3is an alias for-march=r4000and-mips4is an alias for-march=r8000.-mips5,-mips32,-mips32r2,-mips32r3,-mips32r5,-mips32r6,-mips64,-mips64r2,-mips64r3,-mips64r5, and-mips64r6correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. That's the whole family tree, bestie, and they all slay in their own release 🎀-march=cpu— Generate code for a particular MIPS CPU.-mtune=cpu— Schedule and tune for a particular MIPS CPU. Same CPU, but make it fashion 💅-mfix7000-mno-fix7000— Cause nops to be inserted if the read of the destination register of anmfhiormfloinstruction occurs in the following two instructions. Nop nop nop, just a little hardware therapy 😌-mfix-rm7000-mno-fix-rm7000— Cause nops to be inserted if admultordmultuinstruction is followed by a load instruction.-mfix-r5900-mno-fix-r5900— Do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a "nop" instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. Ma'am, that is a hardware bug and it ate the loop count 😭 so like, thenopis a fix, please keep it.-mdebug-no-mdebug— Cause stabs-style debugging output to go into an ECOFF-style.mdebugsection instead of the standard ELF.stabssections. Different container, same drama.-mpdr-mno-pdr— Control generation of.pdrsections.-mgp32-mfp32— The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times.-mgp32controls the size of general-purpose registers and-mfp32controls the size of floating-point registers. Forcing the width, no vibes-based inference 💀-mgp64-mfp64— The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times.-mgp64controls the size of general-purpose registers and-mfp64controls the size of floating-point registers. Double the width, double the icon energy ✨-mfpxx— The register sizes are normally inferred from the ISA and ABI, but using this flag in combination with-mabi=32enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide. She's flexible, she works with either width, we stan an adaptable queen 🦋-modd-spreg-mno-odd-spreg— Enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA.-mfpxximplies-mno-odd-spreg, otherwise the default is-modd-spreg. Odd-numbered registers deserve love too, fr fr.-mips16-no-mips16— Generate code for the MIPS 16 processor. This is equivalent to putting.module mips16at the start of the assembly file.-no-mips16turns off this option. Same thing, different spelling, lowkey convenient.-mmips16e2-mno-mips16e2— Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting.module mips16e2at the start of the assembly file.-mno-mips16e2turns off this option.-mmicromips-mno-micromips— Generate code for the microMIPS processor. This is equivalent to putting.module micromipsat the start of the assembly file.-mno-micromipsturns off this option. This is equivalent to putting.module nomicromipsat the start of the assembly file. Two.modulelines, one function, that's the whole bit 💅-msmartmips-mno-smartmips— Enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting.module smartmipsat the start of the assembly file.-mno-smartmipsturns off this option. The name says smart, I'm just saying 👑-mips3d-no-mips3d— Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions.-no-mips3dturns off this option. 3D era, she's giving extra dimension ✨-mdmx-no-mdmx— Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions.-no-mdmxturns off this option.-mdsp-mno-dsp— Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions.-mno-dspturns off this option.-mdspr2-mno-dspr2— Generate code for the DSP Release 2 Application Specific Extension. This option implies-mdsp. This tells the assembler to accept DSP Release 2 instructions.-mno-dspr2turns off this option. Yes bestie,-mdspr2drags-mdspalong with it, they're a package deal 🫶-mdspr3,-mno-dspr3— Generate code for the DSP Release 3 Application Specific Extension. This option implies-mdspand-mdspr2. This tells the assembler to accept DSP Release 3 instructions.-mno-dspr3turns off this option.-mmsa,-mno-msa— Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions, bestie.-mno-msaturns off this option.-mxpa,-mno-xpa— Generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions.-mno-xpaturns off this option.-mmt,-mno-mt— Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions.-mno-mtturns off this option.-mmcu,-mno-mcu— Generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions.-mno-mcuturns off this option.-mcrc,-mno-crc— Generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. This tells the assembler to accept CRC instructions.-mno-crcturns off this option.-mginv,-mno-ginv— Generate code for the Global INValidate (GINV) Application Specific Extension. This tells the assembler to accept GINV instructions.-mno-ginvturns off this option.-mloongson-mmi,-mno-loongson-mmi— Generate code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. This tells the assembler to accept MMI instructions.-mno-loongson-mmiturns off this option.-mloongson-cam,-mno-loongson-cam— Generate code for the Loongson Content Address Memory (CAM) instructions. This tells the assembler to accept Loongson CAM instructions.-mno-loongson-camturns off this option.-mloongson-ext,-mno-loongson-ext— Generate code for the Loongson EXTensions (EXT) instructions. This tells the assembler to accept Loongson EXT instructions.-mno-loongson-extturns off this option.-mloongson-ext2,-mno-loongson-ext2— Generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies-mloongson-ext. This tells the assembler to accept Loongson EXT2 instructions.-mno-loongson-ext2turns off this option.-minsn32,-mno-insn32— Only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions. This is equivalent to putting.set insn32at the start of the assembly file.-mno-insn32turns off this option. This is equivalent to putting.set noinsn32at the start of the assembly file. By default-mno-insn32is selected, allowing all instructions to be used.--construct-floats,--no-construct-floats— The--no-construct-floatsoption disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default--construct-floatsis selected, allowing construction of these floating point constants.--relax-branch,--no-relax-branch— The--relax-branchoption enables the relaxation of out-of-range branches. By default--no-relax-branchis selected, causing any out-of-range branches to produce an error.-mignore-branch-isa,-mno-ignore-branch-isa— Ignore branch checks for invalid transitions between ISA modes. The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. Therefore GAS has checks implemented that verify in branch assembly that the two ISA modes match.-mignore-branch-isadisables these checks. By default-mno-ignore-branch-isais selected, causing any invalid branch requiring a transition between ISA modes to produce an error.-mnan=encoding— Select between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format. The latter is the default.--emulation=name— This option was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. It is retained for backwards compatibility.
The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferred options instead.
-nocpp—aslowkey ignores this option. It is accepted for compatibility with the native tools.--trap,--no-trap,--break,--no-break— Control how to deal with multiplication overflow and division by zero.--trapor--no-break(which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher);--breakor--no-trap(also synonyms, and the default) take a break exception.-n— When this option is used,aswill issue a warning every time it generates anopinstruction from a macro.
LoongArch processor era 🐣 — The following options are available when as is configured for a LoongArch processor.
-fpic,-fPIC— Generate position-independent code-fno-pic— Don't generate position-independent code (default)
Meta processor time 🎀 — The following options are available when as is configured for a Meta processor.
-mcpu=metac11— Generate code for Meta 1.1.-mcpu=metac12— Generate code for Meta 1.2.-mcpu=metac21— Generate code for Meta 2.1.-mfpu=metac21— Allow code to use FPU hardware of Meta 2.1.
See the info pages for documentation of the MMIX-specific options.
NDS32 processor zone 🦋 — The following options are available when as is configured for a NDS32 processor.
-O1— Optimize for performance.-Os— Optimize for space.-EL— Produce little endian data output.-EB— Produce little endian data output.-mpic— Generate PIC.-mno-fp-as-gp-relax— Suppress fp-as-gp relaxation for this file.-mb2bb-relax— Back-to-back branch optimization.-mno-all-relax— Suppress all relaxation for this file.-march=<arch name>— Assemble for architecture<arch name>which could bev3,v3j,v3m,v3f,v3s,v2,v2j,v2f,v2s.-mbaseline=<baseline>— Assemble for baseline<baseline>which could bev2,v3,v3m.-mfpu-freg=FREG— Specify a FPU configuration.
0 8 SP / 4 DP registers
1 16 SP / 8 DP registers
2 32 SP / 16 DP registers
3 32 SP / 32 DP registers-mabi=abi— Specify a abi version<abi>could bev1,v2,v2fp,v2fpp.-m[no-]mac— Enable/Disable Multiply instructions support.-m[no-]div— Enable/Disable Divide instructions support.-m[no-]16bit-ext— Enable/Disable 16-bit extension-m[no-]dx-regs— Enable/Disable d0/d1 registers-m[no-]perf-ext— Enable/Disable Performance extension-m[no-]perf2-ext— Enable/Disable Performance extension 2-m[no-]string-ext— Enable/Disable String extension-m[no-]reduced-regs— Enable/Disable Reduced Register configuration (GPR16) option-m[no-]audio-isa-ext— Enable/Disable AUDIO ISA extension-m[no-]fpu-sp-ext— Enable/Disable FPU SP extension-m[no-]fpu-dp-ext— Enable/Disable FPU DP extension-m[no-]fpu-fma— Enable/Disable FPU fused-multiply-add instructions-mall-ext— Turn on all extensions and instructions support
PowerPC processor section, no cap 🔥 — The following options are available when as is configured for a PowerPC processor.
-a32— Generate ELF32 or XCOFF32.-a64— Generate ELF64 or XCOFF64.-K PIC— SetEF_PPC_RELOCATABLE_LIBin ELF flags.-mpwrx|-mpwr2— Generate code for POWER/2 (RIOS2).-mpwr— Generate code for POWER (RIOS1)-m601— Generate code for PowerPC 601.-mppc,-mppc32,-m603,-m604— Generate code for PowerPC 603/604.-m403,-m405— Generate code for PowerPC 403/405.-m440— Generate code for PowerPC 440. BookE and some 405 instructions.-m464— Generate code for PowerPC 464.-m476— Generate code for PowerPC 476.-m7400,-m7410,-m7450,-m7455— Generate code for PowerPC 7400/7410/7450/7455.-m750cl,-mgekko,-mbroadway— Generate code for PowerPC 750CL/Gekko/Broadway.-m821,-m850,-m860— Generate code for PowerPC 821/850/860.-mppc64,-m620— Generate code for PowerPC 620/625/630.-me200z2,-me200z4— Generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.-me300— Generate code for PowerPC e300 family.-me500,-me500x2— Generate code for Motorola e500 core complex.-me500mc— Generate code for Freescale e500mc core complex.-me500mc64— Generate code for Freescale e500mc64 core complex.-me5500— Generate code for Freescale e5500 core complex.-me6500— Generate code for Freescale e6500 core complex.-mlsp— Enable LSP instructions. (Disables SPE and SPE2.)-mspe— Generate code for Motorola SPE instructions. (Disables LSP.)-mspe2— Generate code for Freescale SPE2 instructions. (Disables LSP.)-mtitan— Generate code for AppliedMicro Titan core complex.-mppc64bridge— Generate code for PowerPC 64, including bridge insns.-mbooke— Generate code for 32-bit BookE.-ma2— Generate code for A2 architecture.-maltivec— Generate code for processors with AltiVec instructions.-mvle— Generate code for Freescale PowerPC VLE instructions.-mvsx— Generate code for processors with Vector-Scalar (VSX) instructions.-mhtm— Generate code for processors with Hardware Transactional Memory instructions.-mpower4,-mpwr4— Generate code for Power4 architecture.-mpower5,-mpwr5,-mpwr5x— Generate code for Power5 architecture.-mpower6,-mpwr6— Generate code for Power6 architecture.-mpower7,-mpwr7— Generate code for Power7 architecture.-mpower8,-mpwr8— Generate code for Power8 architecture.-mpower9,-mpwr9— Generate code for Power9 architecture.-mpower10,-mpwr10— make code for the Power10 architecture ✨-mpower11,-mpwr11— make code for the Power11 architecture ✨-mfuture— make code for the'future'architecture 👀 (yes literally, that's the name)-mcell— make code for the Cell Broadband Engine architecture 💅-mcom— make code for Power/PowerPC common instructions-many— make code for any architecture (PWR/PWRX/PPC) — she does it all fr fr-mregnames— allow symbolic names for registers 🎀-mno-regnames— nope, no symbolic names for registers allowed-mrelocatable— support for GCC's-mrelocatableoption-mrelocatable-lib— support for GCC's-mrelocatable-liboption-memb— set thePPC_EMBbit in ELF flags 🦋-mlittle,-mlittle-endian,-le— make code for a little endian machine-mbig,-mbig-endian,-be— make code for a big endian machine-nops=count— if an alignment directive inserts more than count nops, it puts a branch at the beginning to skip execution of the nops 🏃♀️💨
Okay bestie, now the following options are available when as is configured for a RISC-V processor 👑
-fpic,-fPIC— generate position-independent code-fno-pic— don't generate position-independent code (this is the default)-march=ISA|Profiles|Profiles_ISA— picks the base isa, as specified by ISA or Profiles or Profiles_ISA. For example-march=rv32ima-march=RVI20U64-march=RVI20U64_d. If this option and the architecture attributes aren't set, then the assembler will check the default configure setting--with-arch=ISA.-misa-spec=ISAspec— picks the default isa spec version. If the version of ISA isn't set by-march, then the assembler helps to set the version according to the default chosen spec. If this option isn't set, then the assembler will check the default configure setting--with-isa-spec=ISAspec.-mpriv-spec=PRIVspec— picks the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren't set, then the assembler will check the default configure setting--with-priv-spec=PRIVspec.-mabi=ABI— selects the ABI, which is either"ilp32"or"lp64", optionally followed by"f","d", or"q"to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or"e"to indicate the soft-float calling convention ("e"indicates a soft-float RVE ABI). 🫶-mrelax— take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default, bestie, she's already doing it)-mno-relax— don't do linker relaxations-march-attr— generate the default contents for the riscv elf attribute section if the.attributedirectives are not set. This section is used to record the information that a linker or runtime loader needs to check compatibility. This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification.-mno-arch-attr— don't generate the default riscv elf attribute section if the.attributedirectives are not set-mcsr-check— enable the CSR checking for the ISA-dependent CSR and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions. ⚠️-mno-csr-check— don't do CSR checking-mlittle-endian— make code for a little endian machine-mbig-endian— make code for a big endian machine
Also: see the info pages for documentation of the RX-specific options 📖
And when as is configured for the s390 processor family? Different fit entirely 💜
-m31,-m64— select the word size, either 31/32 bits or 64 bits-mesa,-mzarch— select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch)-march=processor— specify which s390 processor variant is the target:g5(orarch3),g6,z900(orarch5),z990(orarch6),z9-109,z9-ec(orarch7),z10(orarch8),z196(orarch9),zEC12(orarch10),z13(orarch11),z14(orarch12),z15(orarch13),z16(orarch14), orz17(orarch15). That's a whole glow-up timeline ngl 🌈-mregnames,-mno-regnames— allow or disallow symbolic names for registers-mwarn-areg-zero— warn whenever the operand for a base or index register has been specified but evaluates to zero 👀-mwarn-regtype-mismatch=strict,-mwarn-regtype-mismatch=relaxed,-mwarn-regtype-mismatch=no,-mno-warn-regtype-mismatch— controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type. The default (which can be restored by using therelaxedargument) is to perform relaxed register name type checks, which allow floating point register (FPR) names%f0to%f15to be specified as argument to vector register (VR) operands and vector register (VR) names%v0to%v15to be specified as argument to floating point register (FPR) operands. This is acceptable as the FPR are embedded into the lower half of the VR. Using thestrictargument strict register name type checks are performed. Thenoargument, which is equivalent to-mno-warn-regtype-mismatch, disables any register name type checks. Phew, that was a lot, but you got this 💪
Now when as is configured for a TMS320C6000 processor 🍑
-march=arch— enable (only) instructions from architecture arch. By default, all instructions are permitted. The following values of arch are accepted:"c62x","c64x","c64x+","c67x","c67x+","c674x".-mdsbt,-mno-dsbt— the-mdsbtoption causes the assembler to generate the"Tag_ABI_DSBT"attribute with a value of 1, indicating that the code is using DSBT addressing. The-mno-dsbtoption, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. 😭-mpid=no,-mpid=near,-mpid=far— the-mpid=option causes the assembler to generate the"Tag_ABI_PID"attribute with a value indicating the form of data addressing used by the code.-mpid=no, the default, indicates position-dependent data addressing,-mpid=nearindicates position-independent addressing with GOT accesses using near DP addressing, and-mpid=farindicates position-independent addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together.-mpic,-mno-pic— the-mpicoption causes the assembler to generate the"Tag_ABI_PIC"attribute with a value of 1, indicating that the code is using position-independent code addressing. The-mno-picoption, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together.-mbig-endian,-mlittle-endian— make code for the specified endianness. The default is little-endian. 🐣
For a TILE-Gx processor, the lineup is short and iconic:
-m32|-m64— select the word size, either 32 bits or 64 bits-EB|-EL— select the endianness, either big-endian (-EB) or little-endian (-EL)
For a Visium processor, there's exactly one option and she's carrying the whole team:
-mtune=arch— this option specifies the target architecture. If an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. 🚨
The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
And finally for an Xtensa processor, the following options are available 🦋:
--text-section-literals|--no-text-section-literals— control the treatment of literal pools. The default is--no-text-section-literals, which places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With--text-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the"L32R"instructions in the text section. Literals are grouped into pools following.literal_positiondirectives or preceding"ENTRY"instructions. These options only affect literals referenced via PC-relative"L32R"instructions; literals for absolute mode"L32R"instructions are handled separately.--auto-litpools|--no-auto-litpools— control the treatment of literal pools. The default is--no-auto-litpools, which in the absence of--text-section-literalsplaces literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With--auto-litpools, the literals are interspersed in the text section in order to keep them as close as possible to their references, explicit.literal_positiondirectives are not required. This may be necessary for very large functions, where single literal pool at the beginning of the function may not be reachable by"L32R"instructions at the end. These options only affect literals referenced via PC-relative"L32R"instructions; literals for absolute mode"L32R"instructions are handled separately. When used together with--text-section-literals,--auto-litpoolstakes precedence. 👑--absolute-literals|--no-absolute-literals— indicate to the assembler whether"L32R"instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute"L32R"relocations. Otherwise, only the PC-relative"L32R"relocations can be used.--target-align|--no-target-align— enable or disable automatic alignment to reduce branch penalties at some expense in code size. This optimization is enabled by default. Note that the assembler will always align instructions like"LOOP"that have fixed alignment requirements. 🎯--longcalls/--no-longcalls— flips transformation of call instructions on or off so calls can reach across a way bigger range of addresses 💫. Use this when your call targets can potentially be out of range. Yeah, it may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. Default is--no-longcalls.--transform/--no-transform— turns all assembler transformations of Xtensa instructions on or off, and that includes both relaxation and optimization ✨. Default is--transform. Only reach for--no-transformin those rare cases when the instructions must be exactly as specified in the assembly source. Heads up though: using--no-transformcauses out of range instruction operands to be errors 😭.--rename-section oldname=newname— renames the oldname section to newname. Run it multiple times and you can rename multiple sections, no cap 🎀.--trampolines/--no-trampolines— enables or disables transformation of jump instructions so jumps can cross a greater range of addresses 🦋. Use this when jump targets can potentially be out of range. In the absence of such jumps this option does not affect code size or performance at all, so it's giving free real estate. Default is--trampolines.--abi-windowed/--abi-call0— picks the ABI tag written to the".xtensa.info"section. The ABI tag indicates the ABI of the assembly code. The linker issues a warning when you attempt to link object files with inconsistent ABI tags ⚠️. Default ABI is chosen by the Xtensa core configuration.
The following options are available when as is configured for an Z80 processor 👑.
🎀 Z80 Dependent Features 🎀
(okay so the manpage literally drops @chapter Z80 Dependent Features right here — stray markup moment, we respect it 😭)
🛠 Command-line Options 🛠
-march=CPU[-EXT...][+EXT...]— specifies the target processor 🎯. The assembler will issue an error message if you attempt to assemble an instruction which will not execute on the target processor. These processor names are recognized:z80,z180,ez80,gbz80,z80n,r800. On top of the basic instruction set, the assembler can be told to accept some extension mnemonics — for example,-march=z180+sli+infcextends z180 with SLI instructions andIN F,(C). The following extensions are currently supported:full(all known instructions),adl(ADL CPU mode by default, eZ80 only),sli(instruction known as SLI, SLL or SL1),xyhl(instructions with halves of index registers: IXL, IXH, IYL, IYH),xdcb(instructions likeRotOp (II+d),RandBitOp n,(II+d),R),infc(instructionIN F,(C)orIN (C)),outc0(instructionOUT (C),0).
Plot twist 🌀: rather than extending a basic instruction set, the extension mnemonics starting with - revoke the respective functionality. So -march=z80-full+xyhl first removes all default extensions and then adds support for index register halves only. Iconic behaviour, honestly.
If this option is not specified then -march=z80+xyhl+infc is assumed.
-local-prefix=prefix— marks all labels with the specified prefix as local 💅. But bestie, such a label can still be marked global explicitly in the code. Note that this option does not change the default local label prefix.L— it just adds a new one.-colonless— accepts colonless labels 🌸. All symbols at line begin are treated as labels.-sdcc— accepts assembler code produced by SDCC.-fp-s=FORMAT— single precision floating point numbers format. Default:ieee754(32 bit).-fp-d=FORMAT— double precision floating point numbers format. Default:ieee754(64 bit).
🌈 SEE ALSO 🌈
gcc(1), ld(1), and the Info entries for binutils and ld. Go read them, they're literally right there 🫶.
💜 COPYRIGHT 💜
Copyright (c) 1991-2026 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".
That's the whole page, bestie — every last flag, file, number and license line made it in 💖
And that's a wrap! 🎬 This entire masterpiece is from binutils-2.46.1, dated 1980-01-01, and it's the manual page for AS(1). Slay, go assemble something iconic 💅✨
📦 where this page comes from
- nixpkgs unstable: coreboot-toolchain-ppc64 26.09
- 💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms