AS(1)

📦
version 2.40.50~ti1ubuntu1 · 2 versions
, in ubuntu noble

💖 AS(1) — the portable GNU assembler 💖

okay bestie, gather round, because we're about to talk about as, aka the portable GNU assembler, coming to you straight from the GNU Development Tools 💅

this is part one of a very long love letter, so hydrate, sit criss-cross, and let's get into it 🫶

✨ NAME ✨

AS — the portable GNU assembler. that's it, that's the whole name, short and iconic 👑

✨ SYNOPSIS ✨

here's the vibe, the whole invocation, no cap:

as [-a[cdghlns][=file]]
 [--alternate]
 [--compress-debug-sections] [--nocompress-debug-sections]
 [-D]
 [--dump-config]
 [--debug-prefix-map old=new]
 [--defsym sym=val]
 [--elf-stt-common=[no|yes]]
 [--emulation=name]
 [-f]
 [-g] [--gstabs] [--gstabs+]
 [--gdwarf-<N>] [--gdwarf-sections]
 [--gdwarf-cie-version=VERSION]
 [--generate-missing-build-notes=[no|yes]]
 [--gsframe]
 [--hash-size=N]
 [--help] [--target-help]
 [-I dir]
 [-J]
 [-K]
 [--keep-locals]
 [-L]
 [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM]
 [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM]
 [--multibyte-handling=[allow|warn|warn-sym-only]]
 [--no-pad-sections]
 [-o objfile] [-R]
 [--sectname-subst]
 [--size-check=[error|warning]]
 [--statistics]
 [-v] [-version] [--version]
 [-W] [--warn] [--fatal-warnings] [-w] [-x]
 [-Z] [@FILE]
 [target-options]
 [--|files ...]

like, she's got layers okay 😭 every flag has a job and every job has a flag.

🎯 TARGET 🎯

okay so this next bit is a whole menu of target-specific options — think of it like picking your fighter in smash but the fighter is a CPU architecture 💀 pick your target, read your little section, slay.

AArch64 🦋

[-EB|-EL]
[-mabi=ABI]

Alpha 🌸

[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]

ARC 💜

[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]

ARM 🎀

[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
 -mapcs-reentrant]
[-mthumb-interwork] [-k]

Blackfin 🖤

[-mcpu=processor[-sirevision]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]

BPF 🌈

[-EL] [-EB]

CRIS ⭐

[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
[--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]

C-SKY ☁️

[-march=arch] [-mcpu=cpu]
[-EL] [-mlittle-endian] [-EB] [-mbig-endian]
[-fpic] [-pic]
[-mljump] [-mno-ljump]
[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
[-mnolrw ] [-mno-lrw]
[-melrw] [-mno-elrw]
[-mlaf ] [-mliterals-after-func]
[-mno-laf] [-mno-literals-after-func]
[-mlabr] [-mliterals-after-br]
[-mno-labr] [-mnoliterals-after-br]
[-mistack] [-mno-istack]
[-mhard-float] [-mmp] [-mcp] [-mcache]
[-msecurity] [-mtrust]
[-mdsp] [-medsp] [-mvdsp]

D10V 🍓

[-O]

D30V 🍓

[-O|-n|-N]

EPIPHANY 🧚

[-mepiphany|-mepiphany16]

H8/300 🐝

[-h-tick-hex]

i386 💻

[--32|--x32|--64] [-n]
[-march=CPU[+EXTENSION...]] [-mtune=CPU]

IA-64 🔥

[-mconstant-gp|-mauto-pic]
[-milp32|-milp64|-mlp64|-mp64]
[-mle|mbe]
[-mtune=itanium1|-mtune=itanium2]
[-munwind-check=warning|-munwind-check=error]
[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
[-x|-xexplicit] [-xauto] [-xdebug]

IP2K 🦋

[-mip2022|-mip2022ext]

M32C 🌸

[-m32c|-m16c] [-relax] [-h-tick-hex]

M32R 💜

[--m32rx|--[no-]warn-explicit-parallel-conflicts|
--W[n]p]

M680X0 🎀

[-l] [-m68000|-m68010|-m68020|...]

M68HC11 ⭐

[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branches] [--short-branches]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]

MCORE 🌈

[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]

Meta ☁️

[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
bestie, heads up: that line is literally how it appears in the original — the Meta entry runs straight into the MICROBLAZE header with no line break. not me fixing it, not me breaking it, just showing it to you exactly as it is 🙈

MIPS 🍓

[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot [-mvxworks-pic]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-mfp64] [-mgp64] [-mfpxx]
[-modd-spreg] [-mno-odd-spreg]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
[-mips64r3] [-mips64r5] [-mips64r6]
[-construct-floats] [-no-construct-floats]
[-mignore-branch-isa] [-mno-ignore-branch-isa]
[-mnan=encoding]
[-trap] [-no-break] [-break] [-no-trap]
[-mips16] [-no-mips16]
[-mmips16e2] [-mno-mips16e2]
[-mmicromips] [-mno-micromips]
[-msmartmips] [-mno-smartmips]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdsp] [-mno-dsp]
[-mdspr2] [-mno-dspr2]
[-mdspr3] [-mno-dspr3]
[-mmsa] [-mno-msa]
[-mxpa] [-mno-xpa]
[-mmt] [-mno-mt]
[-mmcu] [-mno-mcu]
[-mcrc] [-mno-crc]
[-mginv] [-mno-ginv]
[-mloongson-mmi] [-mno-loongson-mmi]
[-mloongson-cam] [-mno-loongson-cam]
[-mloongson-ext] [-mno-loongson-ext]
[-mloongson-ext2] [-mno-loongson-ext2]
[-minsn32] [-mno-insn32]
[-mfix7000] [-mno-fix7000]
[-mfix-rm7000] [-mno-fix-rm7000]
[-mfix-vr4120] [-mno-fix-vr4120]
[-mfix-vr4130] [-mno-fix-vr4130]
[-mfix-r5900] [-mno-fix-r5900]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]

like okay MIPS ate and left no crumbs, that's a lot of options and every single one is here 💅

MMIX 🧚

[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]

Nios II 🐝

[-relax-all] [-relax-section] [-no-relax]
[-EB] [-EL]

NDS32 💻

 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
 [-misa=isa] [-mabi=abi] [-mall-ext]
 [-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
 [-mb2bb]

PDP11 🔥

[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]

picoJava 🦋

[-mb|-me]

PowerPC 🌸

[-a32|-a64]
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
[-many] [-maltivec|-mvsx|-mhtm|-mvle]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
[-msolaris|-mno-solaris]
[-nops=count]

PRU 💜

[-link-relax]
[-mnolink-relax]
[-mno-warn-regname-label]

RISC-V 🎀

[-fpic|-fPIC|-fno-pic]
[-march=ISA]
[-mabi=ABI]
[-mlittle-endian|-mbig-endian]

RL78 ⭐

[-mg10]
[-m32bit-doubles|-m64bit-doubles]

RX 🌈

[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]

s390 ☁️

[-m31|-m64] [-mesa|-mzarch] [-march=CPU]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]

SCORE 🍓

[-EB][-EL][-FIXDD][-NWARN]
[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
[-march=score7][-march=score3]
[-USE_R1][-KPIC][-O0][-G num][-V]

SPARC 🧚

[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
 -Asparcvisr|-Asparc5]
[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
 -bump]
[-32|-64]
[--enforce-aligned-data][--dcti-couples-detect]

TIC54X 🐝

[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]

TIC6X 💻

[-march=arch] [-mbig-endian|-mlittle-endian]
[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
[-mpic|-mno-pic]

TILE-Gx 🔥

[-m32|-m64][-EB][-EL]

Visium 🦋

[-mtune=arch]

Xtensa 🌸

[--[no-]text-section-literals] [--[no-]auto-litpools]
[--[no-]absolute-literals]
[--[no-]target-align] [--[no-]longcalls]
[--[no-]transform]
[--rename-section oldname=newname]
[--[no-]trampolines]
[--abi-windowed|--abi-call0]

Z80 💜

[-march=CPU[-EXT][+EXT]]
[-local-prefix=PREFIX]
[-colonless]
[-sdcc]
[-fp-s=FORMAT]
[-fp-d=FORMAT]

that's the whole target lineup bestie, and that's just part one 😭 stay tuned, there's so much more coming 💖

✨ DESCRIPTION ✨

okay so as isn't just one assembler, bestie — it's literally a whole family of them 💖. If you've used (or ever used) the GNU assembler on one architecture, then hopping over to another one should feel extremely similar. Every version has sooo much in common with the rest, like object file formats, most assembler directives (the ones everyone calls pseudo-ops), and the assembler syntax. iconic behavior tbh 🎀

as is mainly meant to assemble the output of the GNU C compiler gcc so the linker ld can do its thing. But ngl, we really did try to make as assemble everything that other assemblers for the same machine would assemble, correctly. Any exceptions? Documented explicitly, no cap. That said, it does not mean as always uses the same syntax as another assembler for the same architecture — like, we know of several incompatible versions of 680x0 assembly language syntax. so yeah, chaos 👑

Every single time you run as, it assembles exactly one source program. That source program is made up of one or more files. (and yes, standard input counts as a file too, obviously 🦋)

You hand as a command line with zero or more input file names. The input files get read left file name to right. Any command-line argument (wherever it sits, in any position) that doesn't have some special meaning? It's taken as an input file name. periodt 💅

If you give as no file names at all, it tries to read one input file from the as standard input, which is normally your terminal. You might have to type ctl-D to tell as there's no more program to assemble. (yes bestie, you're the file now 😭)

Use -- if you need to explicitly name the standard input file in your command line.

If the source is empty, as produces a small, empty object file. tiny king 🫶

as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Here's the vibe check: warnings report an assumption that was made so as could keep assembling a flawed program, and errors report a grave problem that stops the assembly. so like, one is a gentle nudge, one is a full stop ✋

If you're invoking as through the GNU C compiler, you can use the -Wa option to pass arguments straight through to the assembler. Those assembler arguments have to be separated from each other (and from the -Wa) by commas. For example:

gcc -c -g -O -Wa,-alh,-L file.c

This passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table). ate that 💅

Usually you don't even need this -Wa mechanism, since tons of compiler command-line options get passed to the assembler automatically by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler. super useful for snooping 🌸)

💖 OPTIONS 💖

  • @file — Read command-line options from file. The options that get read are inserted in place of the original @file option. If file doesn't exist, or can't be read, then the option is treated literally and not removed. 💀

Options inside file are separated by whitespace. A whitespace character can be included in an option by surrounding the whole option in either single or double quotes. Any character (backslash included, bestie) can be included by prefixing that character with a backslash. And the file itself may contain additional @file options — any of those get processed recursively. it's giving inception 🌀

  • -a[cdghlmns] — Turn on listings, in any of a variety of ways:
    • -ac — omit false conditionals
    • -ad — omit debugging directives
    • -ag — include general information, like as version and options passed
    • -ah — include high-level source
    • -al — include assembly
    • -am — include macro expansions
    • -an — omit forms processing
    • -as — include symbols
    • =file — set the name of the listing file

You can combine these options, so for example use -aln for an assembly listing without forms processing. The =file option, if you use it, must be last — no exceptions. And by itself, -a defaults to -ahls. 💅

  • --alternate — Begin in alternate macro mode.
  • --compress-debug-sections — Compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. Heads up: the resulting object file may not be compatible with older linkers and object file utilities. Note that if compression would make a given section larger, then it is not compressed. 🙈
  • --compress-debug-sections=none
  • --compress-debug-sections=zlib
  • --compress-debug-sections=zlib-gnu
  • --compress-debug-sections=zlib-gabi
  • --compress-debug-sections=zstd — These options control how DWARF debug sections are compressed. --compress-debug-sections=none is equivalent to --nocompress-debug-sections. --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to --compress-debug-sections. --compress-debug-sections=zlib-gnu compresses DWARF debug sections using the obsoleted zlib-gnu format, and the debug sections get renamed to begin with .zdebug. --compress-debug-sections=zstd compresses DWARF debug sections using zstd. Note: if compression would actually make a section larger, then it is not compressed nor renamed. so it stays unbothered, honestly iconic 🦋
  • --nocompress-debug-sections — Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.
  • -D — Enable debugging in target specific backends, if supported. Otherwise ignored. And even if it's ignored, this option is still accepted for script compatibility with calls to other assemblers. (it just sits there politely 🫶)
  • --debug-prefix-map old=new — When assembling files in directory old, record debugging information describing them as in new instead.
  • --defsym sym=value — Define the symbol sym to value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a .set pseudo-op. 💅
  • --dump-config — Displays how the assembler is configured and then exits. little mirror moment ✨
  • --elf-stt-common=no
  • --elf-stt-common=yes — These options control whether the ELF assembler should generate common symbols with the STT_COMMON type. The default can be controlled by a configure option --enable-elf-stt-common.
  • --emulation=name — If the assembler is configured to support multiple different target configurations, then this option can be used to select the desired form.
  • -f — "fast" — skip whitespace and comment preprocessing (assume source is compiler output). speed demon energy 🏎️
  • -g
  • --gen-debug — Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF, then a .debug_info and .debug_line section is only emitted when the assembly file doesn't generate one itself.
  • --gstabs — Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
  • --gstabs+ — Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time. 💀
  • --gdwarf-2 — Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note — this option is only supported by some targets, not all of them.
  • --gdwarf-3 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information — the choice to do so is on a per target basis.
  • --gdwarf-4 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information — the choice to do so is on a per target basis.
  • --gdwarf-5 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information — the choice to do so is on a per target basis.
  • --gdwarf-sections — Instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. For example a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. If the code section is just called .text then the debug line section will still be called just .debug_line without any suffix. matching set, we love a consistent aesthetic 🎀
  • --gdwarf-cie-version=version — Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specified the default is version 1, though some targets can modify this default. Other possible values for version are 3 or 4.
  • --generate-missing-build-notes=yes
  • --generate-missing-build-notes=no — These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the --enable-generate-build-notes configure option.
  • --gsframe — Create .sframe section from CFI directives.
  • --hash-size N — Ignored. Supported for command line compatibility with other assemblers. (it's just here for the plot 🫶)
  • --help — Print a summary of the command-line options and exit.
  • --target-help — Print a summary of all target specific options and exit.
  • -I dir — Add directory dir to the search list for .include directives.
  • -J — Don't warn about signed overflow.
  • -K — Issue warnings when difference tables altered for long displacements.
  • -L
  • --keep-locals — Keep (in the symbol table) local symbols. These symbols start with system-specific local label prefixes, typically .L for ELF systems or L for traditional a.out systems.
  • --listing-lhs-width=number — Set the maximum width, in words, of the output data column for an assembler listing to number.
  • --listing-lhs-width2=number — sets the max width, in words, of the output data column for continuation lines in an assembler listing to number. 💅
  • --listing-rhs-width=number — sets the max width of an input source line, as displayed in a listing, to number bytes. ✨
  • --listing-cont-lines=number — sets the max number of lines printed in a listing for a single line of input to number + 1. 🎀
  • --multibyte-handling=allow, --multibyte-handling=warn, --multibyte-handling=warn-sym-only, --multibyte-handling=warn_sym_only — controls how the assembler handles multibyte characters in the input. The default (which you can restore with the allow argument) is to allow such characters without complaint. Using warn makes the assembler generate a warning message whenever any multibyte character is encountered. Using warn-sym-only will only cause a warning when a symbol is defined with a name that contains multibyte characters. (References to undefined symbols will not generate a warning). 💖
  • --no-pad-sections — stops the assembler for padding (yes, “for”, not “from” — the manpage said it like that 💀) the ends of output sections to the alignment of that section. The default is to pad the sections, but this can waste space which might be needed on targets which have tight memory constraints. 🫶
  • -o objfile — names the object-file output from as as objfile. 💅
  • -R — folds the data section into the text section. ✨
  • --reduce-memory-overheads — ignored. Supported for compatibility with tools that apss (their typo, not mine 💀) the same option to both the assembler and the linker. 🎀
  • --sectname-subst — honors substitution sequences in section names. 💖
  • --size-check=error, --size-check=warning — issues an error or warning for an invalid ELF .size directive. 🔥
  • --statistics — prints the maximum space (in bytes) and total time (in seconds) used by assembly. 👑
  • --strip-local-absolute — removes local absolute symbols from the outgoing symbol table. 💅
  • -v, -version — prints the as version. ✨
  • --version — prints the as version and exits. 🎀
  • -W, --no-warn — suppresses warning messages. 🙈
  • --fatal-warnings — treats warnings as errors. 💀
  • --warn — doesn’t suppress warning messages or treat them as errors. 🌈
  • -w — ignored. 💀
  • -x — ignored. 💀
  • -Z — generates an object file even after errors. 🔥
  • -- | files ... — standard input, or source files to assemble. ✨

✨ AArch64 (64-bit ARM) ✨

The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64).

  • -EB — specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. 💅
  • -EL — specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. 💅
  • -mabi=abi — specifies which ABI the source code uses. The recognized arguments are: "ilp32" and "lp64", which decide the generated object file in ELF32 and ELF64 format respectively. The default is "lp64". ✨
  • -mcpu=processor[+extension...] — specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: "cortex-a34", "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73", "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77", "cortex-a78", "cortex-a78ae", "cortex-a78c", "cortex-a510", "cortex-a710", "ares", "exynos-m1", "falkor", "neoverse-n1", "neoverse-n2", "neoverse-e1", "neoverse-v1", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1" "xgene2", "cortex-r82", "cortex-x1", and "cortex-x2". The special name "all" may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions.

In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor. If some implementations of a particular processor can have an extension, then then (yes, twice, the manpage said it like that 💀) those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions. 🫶

  • -march=architecture[+extension...] — specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: "armv8-a", "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a", "armv8.6-a", "armv8.7-a", "armv8.8-a", "armv8-r", "armv9-a", "armv9.1-a", "armv9.2-a", and "armv9.3-a". If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assembler will default to -mcpu=all. The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu, extensions are not always enabled by default, (yes, that comma is in the original too 💀).
  • -mverbose-error — enables verbose error messages for AArch64 gas. This option is enabled by default. ✨
  • -mno-verbose-error — disables verbose error messages in AArch64 gas. 🙈

🦋 Alpha processor 🦋

The following options are available when as is configured for an Alpha processor.

  • -mcpu — specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the .arch directive. The following processor names are recognized: 21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6", "ev67", "ev68". The special name "all" may be used to allow the assembler to accept instructions valid for any Alpha processor. In order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. "ev4") do not. 💅
  • -mdebug, -no-mdebug — enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. The default is to automatically enable .mdebug when the first stabs directive is seen. 🎀
  • -relax — forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications. 🔥
  • -replace, -noreplace — enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets and "-replace" is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual. 📖
  • -g — this option is used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect. 💅
  • -Gsize — a local common symbol larger than size is placed in .bss, while smaller symbols are placed in .sbss. ✨
  • -F, -32addr — these options are ignored for backward compatibility. 💀

🎀 ARC processor 🎀

The following options are available when as is configured for an ARC processor.

  • -mcpu=cpu — selects the core processor variant. 💅
  • -EB | -EL — select either big-endian (-EB) or little-endian (-EL) output. ✨
  • -mcode-density — enable Code Density extension instructions. 🎀

💖 ARM processor family 💖

The following options are available when as is configured for the ARM processor family.

  • -mcpu=processor[+extension...] — specify which ARM processor variant is the target. 💅
  • -march=architecture[+extension...] — specify which ARM architecture variant is used by the target. ✨
  • -mfpu=floating-point-format — select which Floating Point architecture is the target. 🎀
  • -mfloat-abi=abi — select which floating point ABI is in use. 💖
  • -mthumb — enable Thumb only instruction decoding. 👍
  • -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant — select which procedure calling convention is in use. 🫶
  • -EB | -EL — select either big-endian (-EB) or little-endian (-EL) output. ✨
  • -mthumb-interwork — specify that the code has been generated with interworking between Thumb and ARM code in mind. 🔄
  • -mccs — turns on CodeComposer Studio assembly syntax compatibility mode. 🎛️
  • -k — specify that PIC code has been generated. 💅

🐝 Blackfin processor family 🐝

The following options are available when as is configured for the Blackfin processor family.

  • -mcpu=processor[-sirevision] — specifies the target processor. The optional sirevision is not used in assembler. It’s here such that GCC can easily pass down its "-mcpu=" option. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: "bf504", "bf506", "bf512", "bf514", "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526", "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542", "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m", "bf549", "bf549m", "bf561", and "bf592". 💅
  • -mfdpic — assemble for the FDPIC ABI. 🦋
  • -mno-fdpic, -mnopic — disable -mfdpic. 🙈

🔥 Linux kernel BPF processor family 🔥

The following options are available when as is configured for the Linux kernel BPF processor family.

The manpage literally says:

@chapter BPF Dependent Features

   Options
  • -EB — specifies that the assembler should emit big-endian eBPF. 💅
  • -EL — specifies that the assembler should emit little-endian eBPF. ✨

Note that if no endianness option is specified in the command line, the host endianness is used. See the info pages for documentation of the CRIS-specific options. 📖

🌈 C-SKY processor family 🌈

The following options are available when as is configured for the C-SKY processor family.

  • -march=archname — assemble for architecture archname. Wanna know what's legal? --help lists every valid value for archname. ✨
  • -mcpu=cpuname — assemble for architecture cpuname. Same vibe, --help lists valid values for cpuname.
  • -EL, -mlittle-endian — generate little-endian output. 🦋
  • -EB, -mbig-endian — generate big-endian output.
  • -fpic, -pic — generate position-independent code. classic.
  • -mljump, -mno-ljump — turn on/off the transformation of the short branch instructions jbf, jbt, and jbr into jmpi. Heads up: this one's for V2 processors only. On CK801 and CK802 targets it just gets ignored (they don't support the jmpi instruction at all), and for every other processor it's on by default. 💅
  • -mbranch-stub, -mno-branch-stub — pass through R_CKCORE_PCREL_IMM26BY2 relocations for bsr instructions to the linker.

This one's only available for bare-metal C-SKY V2 ELF targets, where it's enabled by default. And lowkey important: it cannot be used in code that's going to be dynamically linked against shared libraries. 🚫

  • -force2bsr, -mforce2bsr, -no-force2bsr, -mno-force2bsr — enable/disable transformation of jbsr instructions into bsr. For CK801/CK802 targets this is always enabled (and -mno-force2bsr just gets ignored, sorry bestie). It's also always enabled whenever -mbranch-stub is in effect.
  • -jsri2bsr, -mjsri2bsr, -no-jsri2bsr, -mno-jsri2bsr — enable/disable transformation of jsri instructions into bsr. This one's on by default. 🌸
  • -mnolrw, -mno-lrw — enable/disable transformation of lrw instructions into a movih/ori pair.
  • -melrw, -mno-elrw — enable/disable extended lrw instructions. Default-on for CK800-series processors. ⭐
  • -mlaf, -mliterals-after-func, -mno-laf, -mno-literals-after-func — enable/disable placing literal pools after each function.
  • -mlabr, -mliterals-after-br, -mno-labr, -mnoliterals-after-br — enable/disable placing literal pools after unconditional branches. On by default. ✨
  • -mistack, -mno-istack — enable/disable interrupt stack instructions. Default-on for CK801, CK802, and CK802 processors.

The following options are the "yes please I want this specific instruction set" buttons. They also get switched on implicitly if you use -mcpu= to name a processor that supports the feature. 🫶

  • -mhard-float — enable hard float instructions.
  • -mmp — enable multiprocessor instructions.
  • -mcp — enable coprocessor instructions.
  • -mcache — enable cache prefetch instruction.
  • -msecurity — enable C-SKY security instructions.
  • -mtrust — enable C-SKY trust instructions.
  • -mdsp — enable DSP instructions.
  • -medsp — enable enhanced DSP instructions.
  • -mvdsp — enable vector DSP instructions.

Okay next up: Epiphany era 🧚

The following options are available when as is configured for an Epiphany processor.

  • -mepiphany — says both 32 and 16 bit instructions are allowed. This is the default behavior, iykyk.
  • -mepiphany16 — restricts the permitted instructions to just the 16 bit set. tiny mode 💅

And now H8/300 o'clock 🎀

The following options are available when as is configured for an H8/300 processor.

@chapter H8/300 Dependent Features

Options

The Renesas H8/300 version of as has exactly one machine-dependent option, no more no less:

  • -h-tick-hex — support H'00 style hex constants in addition to 0x00 style. both?? yes bestie, both. ✨
  • -mach=name — sets the H8300 machine variant. The recognised machine names are: h8300h, h8300hn, h8300s, h8300sn, h8300sx and h8300sxn.

And for our i386 girlies 🔥

The following options are available when as is configured for an i386 processor.

  • --32 | --x32 | --64 — pick the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.

Heads up though: these options are only available with the ELF object file format, and they require that the necessary BFD support has been included. (On a 32-bit platform you have to add --enable-64-bit-bfd to configure to enable 64-bit usage and use x86-64 as target platform.) 😭

  • -n — by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.
  • --divide — on SVR4-derived platforms, the character / is treated as a comment character, which means it can't be used in expressions. The --divide option turns / into a normal character. Note that this does not disable / at the beginning of a line starting a comment, and it doesn't affect using # for starting a comment.
  • -march=CPU[+EXTENSION...] — this option specifies the target processor. The assembler will throw an error message if you try to assemble an instruction that won't execute on the target processor. The following processor names are recognized: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, btver1, btver2, generic32 and generic64.

On top of the basic instruction set, the assembler can be told to accept various extension mnemonics. For example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. The following extensions are currently supported: 8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_tile, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, snp, invlpgb, tlbsync, svme and padlock. Fun fact: these extension mnemonics can be prefixed with no to revoke the respective (and any dependent) functionality. 💀

And when the .arch directive is used with -march, the .arch directive takes precedent. periodt.

  • -mtune=CPU — this option specifies a processor to optimize for. When used in conjunction with the -march option, only instructions of the processor specified by the -march option will be generated.

Valid CPU values are identical to the processor list of -march=CPU. 👑

  • -msse2avx — says the assembler should encode SSE instructions with VEX prefix.
  • -muse-unaligned-vector-move — says the assembler should encode aligned vector move as unaligned vector move.
  • -msse-check=none, -msse-check=warning, -msse-check=error — these control whether the assembler checks SSE instructions. -msse-check=none makes the assembler not check SSE instructions, which is the default. -msse-check=warning makes the assembler issue a warning for any SSE instruction. -msse-check=error makes the assembler issue an error for any SSE instruction. choose your fighter ✨
  • -mavxscalar=128, -mavxscalar=256 — these control how the assembler encodes scalar AVX instructions. -mavxscalar=128 encodes scalar AVX instructions with 128bit vector length, which is the default. -mavxscalar=256 encodes scalar AVX instructions with 256bit vector length.
⚠️ WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. fr fr, do not ship this. 😭
  • -mvexwig=0, -mvexwig=1 — these control how the assembler encodes VEX.W-ignored (WIG) VEX instructions. -mvexwig=0 encodes WIG VEX instructions with vex.w = 0, which is the default. -mvexwig=1 encodes WIG EVEX instructions with vex.w = 1.
⚠️ WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. 💀
  • -mevexlig=128, -mevexlig=256, -mevexlig=512 — these control how the assembler encodes length-ignored (LIG) EVEX instructions. -mevexlig=128 encodes LIG EVEX instructions with 128bit vector length, which is the default. -mevexlig=256 and -mevexlig=512 encode LIG EVEX instructions with 256bit and 512bit vector length, respectively.
  • -mevexwig=0, -mevexwig=1 — these control how the assembler encodes w-ignored (WIG) EVEX instructions. -mevexwig=0 encodes WIG EVEX instructions with evex.w = 0, which is the default. -mevexwig=1 encodes WIG EVEX instructions with evex.w = 1.
  • -mmnemonic=att, -mmnemonic=intel — this specifies instruction mnemonic for matching instructions. The .att_mnemonic and .intel_mnemonic directives take precedent. 👑
  • -msyntax=att, -msyntax=intel — this specifies instruction syntax when processing instructions. The .att_syntax and .intel_syntax directives take precedent.
  • -mnaked-reg — this specifies that registers don't require a % prefix. The .att_syntax and .intel_syntax directives take precedent.
  • -madd-bnd-prefix — this forces the assembler to add BND prefix to all branches, even if that prefix wasn't explicitly specified in the source code. every single one, bestie. 💅
  • -mno-shared — okay so on ELF targets the assembler is normally out here optimizing out non-PLT relocations against defined non-weak global branch targets with default visibility 💅. But -mshared says bestie, this code might end up in a shared library where all those non-weak global branch targets with default visibility can get preempted 👀. The resulting code is slightly bigger. This one only messes with branch instruction handling, no cap.
  • -mbig-obj — on PE/COFF targets this forces the big object file format, which lets you have more than 32768 sections. more sections than your ex has red flags 🚩
  • -momit-lock-prefix=no, -momit-lock-prefix=yes — these control how the assembler encodes the lock prefix. It's meant as a workaround for processors that literally fail on lock prefix 😭.
fr fr, this can only be safely used on single-core, single-thread computers. -momit-lock-prefix=yes omits all lock prefixes. -momit-lock-prefix=no encodes the lock prefix as usual, and that's the default.
  • -mfence-as-lock-add=no, -mfence-as-lock-add=yes — these control how the assembler encodes lfence, mfence and sfence. -mfence-as-lock-add=yes encodes them as lock addl $0x0, (%rsp) in 64-bit mode and lock addl $0x0, (%esp) in 32-bit mode ✨. -mfence-as-lock-add=no encodes lfence, mfence and sfence as usual, which is the default.
  • -mrelax-relocations=no, -mrelax-relocations=yes — these control whether the assembler generates relax relocations: R_386_GOT32X in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX in 64-bit mode. -mrelax-relocations=yes generates them, -mrelax-relocations=no does not. The default can be controlled by a configure option --enable-x86-relax-relocations.
  • -malign-branch-boundary=NUM — controls how the assembler aligns branches using segment prefixes or NOP. NUM must be a power of 2, and it should be 0 or no less than 16. Branches get aligned within a NUM byte boundary. -malign-branch-boundary=0, which is the default, doesn't align branches at all.
  • -malign-branch=TYPE[+TYPE...] — specifies which types of branches to align 👑. TYPE is a combo of jcc (aligns conditional jumps), fused (aligns fused conditional jumps), jmp (aligns unconditional jumps), call (aligns calls), ret (aligns rets), and indirect (aligns indirect jumps and calls). The default is -malign-branch=jcc+fused+jmp.
  • -malign-branch-prefix-size=NUM — the max number of prefixes on an instruction for aligning branches. NUM should be between 0 and 5. The default NUM is 5.
  • -mbranches-within-32B-boundaries — aligns conditional jumps, fused conditional jumps and unconditional jumps within a 32 byte boundary, with up to 5 segment prefixes on an instruction 🦋. It's equivalent to -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5. The default doesn't align branches.
  • -mlfence-after-load=no, -mlfence-after-load=yes — control whether the assembler generates lfence after load instructions. -mlfence-after-load=yes generates it. -mlfence-after-load=no doesn't, and that's the default.
  • -mlfence-before-indirect-branch=none, -mlfence-before-indirect-branch=all, -mlfence-before-indirect-branch=register, -mlfence-before-indirect-branch=memory — control whether the assembler generates lfence before indirect near branch instructions 💅.
    • -mlfence-before-indirect-branch=all generates lfence before indirect near branch via register and issues a warning before indirect near branch via memory. It also implicitly sets -mlfence-before-ret=shl when there's no explicit -mlfence-before-ret=.
    • -mlfence-before-indirect-branch=register generates lfence before indirect near branch via register.
    • -mlfence-before-indirect-branch=memory issues a warning before indirect near branch via memory.
    • -mlfence-before-indirect-branch=none generates no lfence and issues no warning, which is the default.
Note that lfence won't be generated before an indirect near branch via register with -mlfence-after-load=yes, since lfence gets generated after loading the branch target register. iykyk 💖
  • -mlfence-before-ret=none, -mlfence-before-ret=shl, -mlfence-before-ret=or, -mlfence-before-ret=yes, -mlfence-before-ret=not — control whether the assembler generates lfence before ret ✨. -mlfence-before-ret=or generates an or instruction with lfence. -mlfence-before-ret=shl/yes generates an shl instruction with lfence. -mlfence-before-ret=not generates a not instruction with lfence. -mlfence-before-ret=none generates no lfence, which is the default.
  • -mx86-used-note=no, -mx86-used-note=yes — control whether the assembler generates GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes. The default can be controlled by the --enable-x86-used-note configure option.
  • -mevexrcig=rne, -mevexrcig=rd, -mevexrcig=ru, -mevexrcig=rz — control how the assembler encodes SAE-only EVEX instructions 🌈. -mevexrcig=rne encodes the RC bits of an EVEX instruction with 00, which is the default. -mevexrcig=rd, -mevexrcig=ru and -mevexrcig=rz encode SAE-only EVEX instructions with 01, 10 and 11 RC bits, respectively.
  • -mamd64, -mintel64 — specifies that the assembler should accept only AMD64 or Intel64 ISA in 64-bit mode 👀. The default is to accept common, Intel64 only and AMD64 ISAs.
  • -O0 | -O | -O1 | -O2 | -Os — optimize instruction encoding for a smaller instruction size 🎀.
    • -O and -O1 encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with 32-bit register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions, encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions, and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical.
    • -O2 includes the -O1 optimization plus encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions. In 64-bit mode, VEX encoded instructions with commutative source operands will also have their source operands swapped if that allows using the 2-byte VEX prefix form instead of the 3-byte one. Certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST ✨.
    • -Os includes the -O2 optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. -O0 turns off this optimization.

The following options are available when as is configured for the Ubicom IP2K series 💖.

  • -mip2022ext — specifies that the extended IP2022 instructions are allowed.
  • -mip2022 — restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones.

The following options are available when as is configured for the Renesas M32C and M16C processors 🦋.

  • -m32c — assemble M32C instructions.
  • -m16c — assemble M16C instructions (the default).
  • -relax — enable support for link-time relaxations.
  • -h-tick-hex — support H'00 style hex constants in addition to 0x00 style.

The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series 👑.

  • --m32rx — specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.
  • --warn-explicit-parallel-conflicts or --Wp — produce warning messages when questionable parallel constructs are encountered.
  • --no-warn-explicit-parallel-conflicts or --Wnp — do not produce warning messages when questionable parallel constructs are encountered.

The following options are available when as is configured for the Motorola 68000 series 🌸.

  • -l — shorten references to undefined symbols, to one word instead of two.
  • -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 — specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time.
  • -m68881 | -m68882 | -mno-68881 | -mno-68882 — the target machine does (or does not) have a floating-point coprocessor 💅. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to emulate the coprocessor instructions with the main processor. slay.
  • -m68851 | -mno-68851 — the target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up.

The following options are available when as is configured for an Altera Nios II processor 🌈.

  • -relax-section — replace identified out-of-range branches with PC-relative "jmp" sequences when possible. The generated code sequences are suitable for use in position-independent code, but there's a practical limit on the extended branch range because of the length of the sequences. This option is the default ✨.
  • -relax-all — replace branch instructions not determinable to be in range and all call instructions with "jmp" and "callr" sequences (respectively). This option generates absolute relocations against the target symbols and is not appropriate for position-independent code 🚩.
  • -no-relax — do not replace any branches or calls.
  • -EB — generate big-endian output.
  • -EL — generate little-endian output. This is the default.
  • -march=architecture — this one picks your target architecture, bestie. If you try to assemble an instruction that just will not run on that target architecture, the assembler throws an error message at you. Recognized architecture names are "r1" and "r2". Default is "r1".

and now… the PRU processor era 🫶 these next ones only show up when as is configured for a PRU processor.

  • -mlink-relax — tells the assembler to assume LD is gonna optimize LDI32 instructions by peeking at the upper 16 bits of the expression. If those bits are all zeros, then LD would shorten the LDI32 down to a single LDI. When that happens, as outputs DIFF relocations for diff expressions. teamwork fr.
  • -mno-link-relax — opposite vibe: assume LD will not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted.
  • -mno-warn-regname-label — do not warn when a label name matches a register name. Usually assembler programmers actually want that warning, lowkey. C compilers may wanna turn it off though.

and here comes the MIPS processor section 👑 so many flags, so little time.

  • -G num — sets the largest size of an object that can be referenced implicitly with the "gp" register. Only accepted for targets that use ECOFF format, like a DECstation running Ultrix. Default value is 8.
  • -EB — generate "big endian" format output.
  • -EL — generate "little endian" format output.
  • -mips1, -mips2, -mips3, -mips4, -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, -mips64r6 — generate code for a particular MIPS Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000, and -mips4 is an alias for -march=r8000. Then -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. alphabet soup but make it silicon ✨
  • -march=cpu — generate code for a particular MIPS CPU.
  • -mtune=cpu — schedule and tune for a particular MIPS CPU.
  • -mfix7000, -mno-fix7000 — cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
  • -mfix-rm7000, -mno-fix-rm7000 — cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.
  • -mfix-r5900, -mno-fix-r5900 — don't even attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer, and always schedule a "nop" instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, thanks to a hardware bug in the R5900 chip. hardware said no 💀
  • -mdebug, -no-mdebug — cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections.
  • -mpdr, -mno-pdr — control generation of ".pdr" sections.
  • -mgp32, -mfp32 — register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.
  • -mgp64, -mfp64 — same deal, but these flags force a certain group of registers to be treated as 64 bits wide at all times. -mgp64 controls the size of general-purpose registers and -mfp64 controls the size of floating-point registers.
  • -mfpxx — register sizes are normally inferred from the ISA and ABI, but using this flag in combination with -mabi=32 enables an ABI variant which will operate correctly with floating-point registers that are 32 or 64 bits wide.
  • -modd-spreg, -mno-odd-spreg — enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA. -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg.
  • -mips16, -no-mips16 — generate code for the MIPS 16 processor. This is equivalent to putting ".module mips16" at the start of the assembly file. -no-mips16 turns off this option.
  • -mmips16e2, -mno-mips16e2 — enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting ".module mips16e2" at the start of the assembly file. -mno-mips16e2 turns off this option.
  • -mmicromips, -mno-micromips — generate code for the microMIPS processor. This is equivalent to putting ".module micromips" at the start of the assembly file. -mno-micromips turns off this option. This is equivalent to putting ".module nomicromips" at the start of the assembly file.
  • -msmartmips, -mno-smartmips — enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting ".module smartmips" at the start of the assembly file. -mno-smartmips turns off this option.
  • -mips3d, -no-mips3d — generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option.
  • -mdmx, -no-mdmx — generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.
  • -mdsp, -mno-dsp — generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option.
  • -mdspr2, -mno-dspr2 — generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option.
  • -mdspr3, -mno-dspr3 — generate code for the DSP Release 3 Application Specific Extension. This option implies -mdsp and -mdspr2. This tells the assembler to accept DSP Release 3 instructions. -mno-dspr3 turns off this option.
  • -mmsa, -mno-msa — generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. -mno-msa turns off this option.
  • -mxpa, -mno-xpa — generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions. -mno-xpa turns off this option.
  • -mmt, -mno-mt — generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns off this option.
  • -mmcu, -mno-mcu — generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. -mno-mcu turns off this option.
  • -mcrc, -mno-crc — generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. This tells the assembler to accept CRC instructions. -mno-crc turns off this option.
  • -mginv, -mno-ginv — generate code for the Global INValidate (GINV) Application Specific Extension. This tells the assembler to accept GINV instructions. -mno-ginv turns off this option.
  • -mloongson-mmi, -mno-loongson-mmi — generate code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. This tells the assembler to accept MMI instructions. -mno-loongson-mmi turns off this option.
  • -mloongson-cam, -mno-loongson-cam — generate code for the Loongson Content Address Memory (CAM) instructions. This tells the assembler to accept Loongson CAM instructions. -mno-loongson-cam turns off this option.
  • -mloongson-ext, -mno-loongson-ext — generate code for the Loongson EXTensions (EXT) instructions. This tells the assembler to accept Loongson EXT instructions. -mno-loongson-ext turns off this option.
  • -mloongson-ext2, -mno-loongson-ext2 — generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies -mloongson-ext. This tells the assembler to accept Loongson EXT2 instructions. -mno-loongson-ext2 turns off this option.
  • -minsn32, -mno-insn32 — only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions. This is equivalent to putting ".set insn32" at the start of the assembly file. -mno-insn32 turns off this option. This is equivalent to putting ".set noinsn32" at the start of the assembly file. By default -mno-insn32 is selected, allowing all instructions to be used.
  • --construct-floats, --no-construct-floats — the --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default --construct-floats is selected, allowing construction of these floating point constants.
  • --relax-branch, --no-relax-branch — the --relax-branch option enables the relaxation of out-of-range branches. By default --no-relax-branch is selected, causing any out-of-range branches to produce an error.
  • -mignore-branch-isa, -mno-ignore-branch-isa — ignore branch checks for invalid transitions between ISA modes. The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. Therefore GAS has checks implemented that verify in branch assembly that the two ISA modes match. -mignore-branch-isa disables these checks. By default -mno-ignore-branch-isa is selected, causing any invalid branch requiring a transition between ISA modes to produce an error.
  • -mnan=encoding — select between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format. The latter is the default.
  • --emulation=name — okay so back in the day this was the switch between ELF and ECOFF output on targets like IRIX 5 that supported both, bestie. But MIPS ECOFF support got yeeted in GAS 2.24, so now this option is kinda just vibing there doing nothing. It's kept around purely for backwards compatibility. 💀

The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, because the output is always ELF, periodt. mipslelf and mipsbelf select little- and big-endian output respectively, but ngl -EL and -EB are the preferred options now.

  • -nocpp — as literally ignores this option. It's just accepted for compatibility with the native tools. 🙈
  • --trap
  • --no-trap
  • --break
  • --no-break — these four control how to deal with multiplication overflow and division by zero. --trap or --no-break (which are synonyms) take a trap exception — and heads up, they only work for Instruction Set Architecture level 2 and higher. --break or --no-trap (also synonyms, and the default) take a break exception. ✨
  • -n — when this option is used, as will issue a warning every time it generates a nop instruction from a macro. Not me getting warned every single time 💅

🦋 The following options are available when as is configured for a LoongArch processor

  • -fpic
  • -fPIC — Generate position-independent code
  • -fno-pic — Don't generate position-independent code (default)

🎀 The following options are available when as is configured for a Meta processor

  • -mcpu=metac11 — Generate code for Meta 1.1.
  • -mcpu=metac12 — Generate code for Meta 1.2.
  • -mcpu=metac21 — Generate code for Meta 2.1.
  • -mfpu=metac21 — Allow code to use FPU hardware of Meta 2.1.

See the info pages for documentation of the MMIX-specific options. 👑

🌸 The following options are available when as is configured for a NDS32 processor

  • -O1 — Optimize for performance.
  • -Os — Optimize for space.
  • -EL — Produce little endian data output.
  • -EB — Produce little endian data output.
  • -mpic — Generate PIC.
  • -mno-fp-as-gp-relax — Suppress fp-as-gp relaxation for this file.
  • -mb2bb-relax — Back-to-back branch optimization.
  • -mno-all-relax — Suppress all relaxation for this file.
  • -march=<arch name> — Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.
  • -mbaseline=<baseline> — Assemble for baseline <baseline> which could be v2, v3, v3m.
  • -mfpu-freg=FREG — Specify a FPU configuration.
"0      8 SP /  4 DP registers"
"1     16 SP /  8 DP registers"
"2     32 SP / 16 DP registers"
"3     32 SP / 32 DP registers"
  • -mabi=abi — Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
  • -m[no-]mac — Enable/Disable Multiply instructions support.
  • -m[no-]div — Enable/Disable Divide instructions support.
  • -m[no-]16bit-ext — Enable/Disable 16-bit extension
  • -m[no-]dx-regs — Enable/Disable d0/d1 registers
  • -m[no-]perf-ext — Enable/Disable Performance extension
  • -m[no-]perf2-ext — Enable/Disable Performance extension 2
  • -m[no-]string-ext — Enable/Disable String extension
  • -m[no-]reduced-regs — Enable/Disable Reduced Register configuration (GPR16) option
  • -m[no-]audio-isa-ext — Enable/Disable AUDIO ISA extension
  • -m[no-]fpu-sp-ext — Enable/Disable FPU SP extension
  • -m[no-]fpu-dp-ext — Enable/Disable FPU DP extension
  • -m[no-]fpu-fma — Enable/Disable FPU fused-multiply-add instructions
  • -mall-ext — Turn on all extensions and instructions support 🔥

💜 The following options are available when as is configured for a PowerPC processor

  • -a32 — Generate ELF32 or XCOFF32.
  • -a64 — Generate ELF64 or XCOFF64.
  • -K PIC — Set EF_PPC_RELOCATABLE_LIB in ELF flags.
  • -mpwrx | -mpwr2 — Generate code for POWER/2 (RIOS2).
  • -mpwr — Generate code for POWER (RIOS1)
  • -m601 — Generate code for PowerPC 601.
  • -mppc, -mppc32, -m603, -m604 — Generate code for PowerPC 603/604.
  • -m403, -m405 — Generate code for PowerPC 403/405.
  • -m440 — Generate code for PowerPC 440. BookE and some 405 instructions.
  • -m464 — Generate code for PowerPC 464.
  • -m476 — Generate code for PowerPC 476.
  • -m7400, -m7410, -m7450, -m7455 — Generate code for PowerPC 7400/7410/7450/7455.
  • -m750cl, -mgekko, -mbroadway — Generate code for PowerPC 750CL/Gekko/Broadway.
  • -m821, -m850, -m860 — Generate code for PowerPC 821/850/860.
  • -mppc64, -m620 — Generate code for PowerPC 620/625/630.
  • -me200z2, -me200z4 — Generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.
  • -me300 — Generate code for PowerPC e300 family.
  • -me500, -me500x2 — Generate code for Motorola e500 core complex.
  • -me500mc — Generate code for Freescale e500mc core complex.
  • -me500mc64 — Generate code for Freescale e500mc64 core complex.
  • -me5500 — Generate code for Freescale e5500 core complex.
  • -me6500 — Generate code for Freescale e6500 core complex.
  • -mlsp — Enable LSP instructions. (Disables SPE and SPE2.)
  • -mspe — Generate code for Motorola SPE instructions. (Disables LSP.)
  • -mspe2 — Generate code for Freescale SPE2 instructions. (Disables LSP.)
  • -mtitan — Generate code for AppliedMicro Titan core complex.
  • -mppc64bridge — Generate code for PowerPC 64, including bridge insns.
  • -mbooke — Generate code for 32-bit BookE.
  • -ma2 — Generate code for A2 architecture.
  • -maltivec — Generate code for processors with AltiVec instructions.
  • -mvle — Generate code for Freescale PowerPC VLE instructions.
  • -mvsx — Generate code for processors with Vector-Scalar (VSX) instructions.
  • -mhtm — Generate code for processors with Hardware Transactional Memory instructions.
  • -mpower4, -mpwr4 — Generate code for Power4 architecture.
  • -mpower5, -mpwr5, -mpwr5x — Generate code for Power5 architecture.
  • -mpower6, -mpwr6 — Generate code for Power6 architecture.
  • -mpower7, -mpwr7 — Generate code for Power7 architecture.
  • -mpower8, -mpwr8 — Generate code for Power8 architecture.
  • -mpower9, -mpwr9 — Generate code for Power9 architecture.
  • -mpower10, -mpwr10 — Generate code for Power10 architecture.
  • -mfuture — Generate code for 'future' architecture.
  • -mcell
  • -mcell — Generate code for Cell Broadband Engine architecture.
  • -mcom — Generate code Power/PowerPC common instructions.
  • -many — Generate code for any architecture (PWR/PWRX/PPC).
  • -mregnames — Allow symbolic names for registers.
  • -mno-regnames — Do not allow symbolic names for registers.
  • -mrelocatable — Support for GCC's -mrelocatable option.
  • -mrelocatable-lib — Support for GCC's -mrelocatable-lib option.
  • -memb — Set PPC_EMB bit in ELF flags.
  • -mlittle, -mlittle-endian, -le — Generate code for a little endian machine.
  • -mbig, -mbig-endian, -be — Generate code for a big endian machine.
  • -msolaris — Generate code for Solaris.
  • -mno-solaris — Do not generate code for Solaris.
  • -nops=count — If an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops.

🌈 The following options are available when as is configured for a RISC-V processor

  • -fpic
  • -fPIC — Generate position-independent code
  • -fno-pic — Don't generate position-independent code (default)
  • -march=ISA — Select the base isa, as specified by ISA. For example -march=rv32ima. If this option and the architecture attributes aren't set, then assembler will check the default configure setting --with-arch=ISA.
  • -misa-spec=ISAspec — Select the default isa spec version. If the version of ISA isn't set by -march, then assembler helps to set the version according to the default chosen spec. If this option isn't set, then assembler will check the default configure setting --with-isa-spec=ISAspec.
  • -mpriv-spec=PRIVspec — Select the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren't set, then assembler will check the default configure setting --with-priv-spec=PRIVspec.
  • -mabi=ABI — Selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none to indicate the soft-float calling convention. Also, "ilp32" can optionally be followed by "e" to indicate the RVE ABI, which is always soft-float.
  • -mrelax — Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default)
  • -mno-relax — Don't do linker relaxations.
  • -march-attr — Generate the default contents for the riscv elf attribute section if the .attribute directives are not set. This section is used to record the information that a linker or runtime loader needs to check compatibility. This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification.
  • -mno-arch-attr — Don't generate the default riscv elf attribute section if the .attribute directives are not set.
  • -mcsr-check — Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions.
  • -mno-csr-check — Don't do CSR checking.
  • -mlittle-endian — Generate code for a little endian machine.
  • -mbig-endian — Generate code for a big endian machine.

See the info pages for documentation of the RX-specific options. 🦋

⭐ The following options are available when as is configured for the s390 processor family

  • -m31
  • -m64 — Select the word size, either 31/32 bits or 64 bits.
  • -mesa
  • -mzarch — Select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).
  • -march=processor — tells as which s390 processor variant is the target, bestie. Your choices are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14). 💅
  • -mregnames, -mno-regnames — allow or disallow symbolic names for registers. It's giving very "name your registers" energy. ✨
  • -mwarn-areg-zero — warn whenever the operand for a base or index register has been specified but evaluates to zero. She will absolutely let you know. 🚨

The following options are available when as is configured for a TMS320C6000 processor. 🫶

  • -march=arch — enable (only) instructions from architecture arch. By default, all instructions are permitted. Lowkey generous of her.

The following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x".

  • -mdsbt, -mno-dsbt — the -mdsbt option causes the assembler to generate the "Tag_ABI_DSBT" attribute with a value of 1, indicating that the code is using DSBT addressing. The -mno-dsbt option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. So messy, don't mix them. 😭
  • -mpid=no, -mpid=near, -mpid=far — the -mpid= option causes the assembler to generate the "Tag_ABI_PID" attribute with a value indicating the form of data addressing used by the code. -mpid=no, the default, indicates position-dependent data addressing, -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing, and -mpid=far indicates position-independent addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together. ⚠️
  • -mpic, -mno-pic — the -mpic option causes the assembler to generate the "Tag_ABI_PIC" attribute with a value of 1, indicating that the code is using position-independent code addressing, The "-mno-pic" option, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together. 💀
  • -mbig-endian, -mlittle-endian — generate code for the specified endianness. The default is little-endian. Pick your vibe: big or little. 🐘🐭

The following options are available when as is configured for a TILE-Gx processor. 🌈

  • -m32 | -m64 — select the word size, either 32 bits or 64 bits.
  • -EB | -EL — select the endianness, either big-endian (-EB) or little-endian (-EL).

The following option is available when as is configured for a Visium processor. 🦋

  • -mtune=arch — this option specifies the target architecture. If an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. No cap, she will read you. 😤

The following names are recognized: "mcm24" "mcm" "gr5" "gr6"

The following options are available when as is configured for an Xtensa processor. 💅

  • --text-section-literals | --no-text-section-literals — control the treatment of literal pools. The default is --no-text-section-literals, which places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With --text-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the "L32R" instructions in the text section. Literals are grouped into pools following .literal_position directives or preceding ENTRY instructions. These options only affect literals referenced via PC-relative "L32R" instructions; literals for absolute mode "L32R" instructions are handled separately.
  • --auto-litpools | --no-auto-litpools — control the treatment of literal pools. The default is --no-auto-litpools, which in the absence of --text-section-literals places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With --auto-litpools, the literals are interspersed in the text section in order to keep them as close as possible to their references, explicit .literal_position directives are not required. This may be necessary for very large functions, where single literal pool at the beginning of the function may not be reachable by "L32R" instructions at the end. These options only affect literals referenced via PC-relative "L32R" instructions; literals for absolute mode "L32R" instructions are handled separately. When used together with --text-section-literals, --auto-litpools takes precedence.
  • --absolute-literals | --no-absolute-literals — indicate to the assembler whether "L32R" instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute "L32R" relocations. Otherwise, only the PC-relative "L32R" relocations can be used.
  • --target-align | --no-target-align — enable or disable automatic alignment to reduce branch penalties at some expense in code size. This optimization is enabled by default. Note that the assembler will always align instructions like "LOOP" that have fixed alignment requirements.
  • --longcalls | --no-longcalls — enable or disable transformation of call instructions to allow calls across a greater range of addresses. This option should be used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. The default is --no-longcalls.
  • --transform | --no-transform — enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The default is --transform; --no-transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source. Using --no-transform causes out of range instruction operands to be errors.
  • --rename-section oldname=newname — rename the oldname section to newname. This option can be used multiple times to rename multiple sections. Glow-up for sections, periodt. 💖
  • --trampolines | --no-trampolines — enable or disable transformation of jump instructions to allow jumps across a greater range of addresses. This option should be used when jump targets can potentially be out of range. In the absence of such jumps this option does not affect code size or performance. The default is --trampolines.
  • --abi-windowed | --abi-call0 — choose ABI tag written to the .xtensa.info section. ABI tag indicates ABI of the assembly code. A warning is issued by the linker on an attempt to link object files with inconsistent ABI tags. Default ABI is chosen by the Xtensa core configuration.

The following options are available when as is configured for an Z80 processor. 🎮

@chapter Z80 Dependent Features

Command-line Options

  • -march=CPU[-EXT...][+EXT...] — this option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: "z80", "z180", "ez80", "gbz80", "z80n", "r800". In addition to the basic instruction set, the assembler can be told to accept some extension mnemonics. For example, "-march=z180+sli+infc" extends z180 with SLI instructions and IN F,(C). The following extensions are currently supported: "full" (all known instructions), "adl" (ADL CPU mode by default, eZ80 only), "sli" (instruction known as SLI, SLL or SL1), "xyhl" (instructions with halves of index registers: IXL, IXH, IYL, IYH), "xdcb" (instructions like RotOp (II+d),R and BitOp n,(II+d),R), "infc" (instruction IN F,(C) or IN (C)), "outc0" (instruction OUT (C),0). Note that rather than extending a basic instruction set, the extension mnemonics starting with "-" revoke the respective functionality: "-march=z80-full+xyhl" first removes all default extensions and adds support for index registers halves only.

If this option is not specified then "-march=z80+xyhl+infc" is assumed.

  • -local-prefix=prefix — mark all labels with specified prefix as local. But such label can be marked global explicitly in the code. This option do not change default local label prefix .L, it is just adds new one.
  • -colonless — accept colonless labels. All symbols at line begin are treated as labels.
  • -sdcc — accept assembler code produced by SDCC.
  • -fp-s=FORMAT — single precision floating point numbers format. Default: ieee754 (32 bit).
  • -fp-d=FORMAT — double precision floating point numbers format. Default: ieee754 (64 bit).

👀 SEE ALSO 👀

gcc(1), ld(1), and the Info entries for binutils and ld.

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This page is from binutils-2.40.50, dated 2023-07-04, and it's the AS(1) man page. Stay iconic, bestie — you ate this whole manual 💖✨👑

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