AS(1)
💖 AS(1) — the portable GNU assembler 💖
okay so bestie, welcome to the GNU Development Tools corner of the manual, section 1. This is the page for as, and yes, the title line up top literally says AS(1) and GNU Development Tools and AS(1) again, because manpages love a little symmetrical moment. We're folding the manual name in right here so you don't have to scroll. ✨
This is part 1 of 9, so don't go anywhere — we are NOT signing off, we're just getting comfy. 🫶
🌸 NAME 🌸
AS — the portable GNU assembler. that's it. that's the name. short, iconic, does exactly what it says. 👑
✨ SYNOPSIS ✨
okay so here's the whole vibe in one block. every flag, every bracket, exactly as written, no cap:
as [-a[cdghilns][=file]]
[--alternate]
[--compress-debug-sections] [--nocompress-debug-sections]
[-D]
[--dump-config]
[--debug-prefix-map old=new]
[--defsym sym=val]
[--elf-stt-common=[no|yes]]
[--emulation=name]
[-f]
[-g] [--gstabs] [--gstabs+]
[--gdwarf-<N>] [--gdwarf-sections]
[--gdwarf-cie-version=VERSION]
[--generate-missing-build-notes=[no|yes]]
[--gsframe] [--gsframe=[no|yes]]
[--hash-size=N]
[--help] [--target-help]
[--info] [--no-info]
[-I dir]
[-J]
[-K]
[--keep-locals]
[-L]
[--listing-lhs-width=NUM]
[--listing-lhs-width2=NUM]
[--listing-rhs-width=NUM]
[--listing-cont-lines=NUM]
[--multibyte-handling=[allow|warn|warn-sym-only]]
[--no-pad-sections]
[-o objfile] [-R]
[--scfi=experimental]
[--sectname-subst]
[--size-check=[error|warning]]
[--statistics]
[-v] [--verbose]
[-version] [--version]
[-W] [--no-warn] [--warn] [--fatal-warnings]
[-w] [-x]
[-Z] [@FILE]
[target-options]
[--|files ...]🦋 the brackets are not decorative, bestie — they mean "optional". the | means "pick one". it's giving choose-your-own-adventure but for assembly.
🌈 TARGET 🌈
okay so this is the part where it gets LONG and we love her for it. Every architecture gets its own little menu of target-specific options. We're keeping every single one, exactly as written, because the facts do not change even when the vibe does. 💅
🎀 Target AArch64 options
[-EB|-EL]
[-mabi=ABI]two options. two. she's lowkey minimal and that's her right. ✨
🎀 Target Alpha options
[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]🎀 Target ARC options
[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]🎀 Target ARM options
[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
-mapcs-reentrant]
[-mthumb-interwork] [-k]note the +extension... situation — you can stack extensions on top of a processor or an architecture, iykyk. 🧚
🎀 Target Blackfin options
[-mcpu=processor[-sirevision]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]🎀 Target BPF options
[-EL] [-EB]tiny. mighty. endianness only. periodt. 💀
🎀 Target CRIS options
[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
[--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]🎀 Target C-SKY options
[-march=arch] [-mcpu=cpu]
[-EL] [-mlittle-endian] [-EB] [-mbig-endian]
[-fpic] [-pic]
[-mljump] [-mno-ljump]
[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
[-mnolrw ] [-mno-lrw]
[-melrw] [-mno-elrw]
[-mlaf ] [-mliterals-after-func]
[-mno-laf] [-mno-literals-after-func]
[-mlabr] [-mliterals-after-br]
[-mno-labr] [-mnoliterals-after-br]
[-mistack] [-mno-istack]
[-mhard-float] [-mmp] [-mcp] [-mcache]
[-msecurity] [-mtrust]
[-mdsp] [-medsp] [-mvdsp]🌸 yes, there really are a couple of stray spaces before a]up in there ([-no-jsri2bsr ],[-mnolrw ],[-mlaf ]). we do not "fix" the original, we preserve her exactly as she is. main character behaviour only.
🎀 Target D10V options
[-O]🎀 Target D30V options
[-O|-n|-N]🎀 Target EPIPHANY options
[-mepiphany|-mepiphany16]🎀 Target H8/300 options
[-h-tick-hex]🎀 Target i386 options
[--32|--x32|--64] [-n]
[-march=CPU[+EXTENSION...]] [-mtune=CPU]🎀 Target IA-64 options
[-mconstant-gp|-mauto-pic]
[-milp32|-milp64|-mlp64|-mp64]
[-mle|mbe]
[-mtune=itanium1|-mtune=itanium2]
[-munwind-check=warning|-munwind-check=error]
[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
[-x|-xexplicit] [-xauto] [-xdebug]🎀 Target IP2K options
[-mip2022|-mip2022ext]🎀 Target M32C options
[-m32c|-m16c] [-relax] [-h-tick-hex]🎀 Target M32R options
[--m32rx|--[no-]warn-explicit-parallel-conflicts|
--W[n]p]🎀 Target M680X0 options
[-l] [-m68000|-m68010|-m68020|...]the ... is doing so much heavy lifting there and honestly? respect. ⭐
🎀 Target M68HC11 options
[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branches] [--short-branches]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]🎀 Target MCORE options
[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]🎀 Target Meta options
[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu]and immediately after, with zero line break in the original — the legend herself:
🎀 Target MICROBLAZE options
[-mlittle-endian] [-mbig-endian]🙈 fr fr, in the original text these two got squished onto one line —Target Meta options:runs straight intoTarget MICROBLAZE options:. we split them so your eyes can breathe, but nothing got lost.
🎀 Target MIPS options
[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot [-mvxworks-pic]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-mfp64] [-mgp64] [-mfpxx]
[-modd-spreg] [-mno-odd-spreg]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
[-mips64r3] [-mips64r5] [-mips64r6]
[-construct-floats] [-no-construct-floats]
[-mignore-branch-isa] [-mno-ignore-branch-isa]
[-mnan=encoding]
[-trap] [-no-break] [-break] [-no-trap]
[-mips16] [-no-mips16]
[-mmips16e2] [-mno-mips16e2]
[-mmicromips] [-mno-micromips]
[-msmartmips] [-mno-smartmips]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdsp] [-mno-dsp]
[-mdspr2] [-mno-dspr2]
[-mdspr3] [-mno-dspr3]
[-mmsa] [-mno-msa]
[-mxpa] [-mno-xpa]
[-mmt] [-mno-mt]
[-mmcu] [-mno-mcu]
[-mcrc] [-mno-crc]
[-mginv] [-mno-ginv]
[-mloongson-mmi] [-mno-loongson-mmi]
[-mloongson-cam] [-mno-loongson-cam]
[-mloongson-ext] [-mno-loongson-ext]
[-mloongson-ext2] [-mno-loongson-ext2]
[-minsn32] [-mno-insn32]
[-mfix7000] [-mno-fix7000]
[-mfix-rm7000] [-mno-fix-rm7000]
[-mfix-vr4120] [-mno-fix-vr4120]
[-mfix-vr4130] [-mno-fix-vr4130]
[-mfix-r5900] [-mno-fix-r5900]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]this list is a whole meal. she ate. every -m and every -mno- counterpart is here and we are not skipping a single crumb. 💅
🎀 Target MMIX options
[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]🎀 Target NDS32 options
[-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
[-misa=isa] [-mabi=abi] [-mall-ext]
[-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
[-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
[-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
[-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
[-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
[-mb2bb]the [no-] pattern is everywhere here and honestly it's a whole aesthetic. yes to the thing, or no- to the thing. pick. 🎀
🎀 Target PDP11 options
[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]🎀 Target picoJava options
[-mb|-me]🎀 Target PowerPC options
[-a32|-a64]
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
-m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
-mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
-me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
-mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
-mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
[-many] [-maltivec|-mvsx|-mhtm|-mvle]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
[-nops=count]that first cluster? a whole family reunion. we copied every single one, including -mpwr9-ma2, exactly as she appears. 🌈
🎀 Target PRU options
[-link-relax]
[-mnolink-relax]
[-mno-warn-regname-label]🎀 Target RISC-V options
[-fpic|-fPIC|-fno-pic]
[-march=ISA|Profiles|Profiles_ISA]
[-mabi=ABI]
[-mlittle-endian|-mbig-endian]🎀 Target RL78 options
[-mg10]
[-m32bit-doubles|-m64bit-doubles]🎀 Target RX options
[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]🎀 Target s390 options
[-m31|-m64] [-mesa|-mzarch] [-march=CPU]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]
[-mwarn-regtype-mismatch=strict
-mwarn-regtype-mismatch=relaxed
-mwarn-regtype-mismatch=no
-mno-warn-regtype-mismatch]🎀 Target SCORE options
[-EB][-EL][-FIXDD][-NWARN]
[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
[-march=score7][-march=score3]
[-USE_R1][-KPIC][-O0][-G num][-V]🎀 Target SPARC options
[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
-Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
-Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
-Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
-Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
-Asparcvisr|-Asparc5]
[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
-xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
-xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
-xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
-xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
-xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
-bump]
[-32|-64]
[--enforce-aligned-data][--dcti-couples-detect]💀 heads up bestie — the bracket placement in the-xarch=block is exactly as the original has it, including that]sitting right after-xarch=v8plusa. we are preserving, not editing. do not @ me.
🎀 Target TIC54X options
[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]🎀 Target TIC6X options
[-march=arch] [-mbig-endian|-mlittle-endian]
[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
[-mpic|-mno-pic]🎀 Target TILE-Gx options
[-m32|-m64][-EB][-EL]🎀 Target Visium options
[-mtune=arch]🎀 Target Xtensa options
[--[no-]text-section-literals] [--[no-]auto-litpools]
[--[no-]absolute-literals]
[--[no-]target-align] [--[no-]longcalls]
[--[no-]transform]
[--rename-section oldname=newname]
[--[no-]trampolines]
[--abi-windowed|--abi-call0]look at --rename-section oldname=newname just sitting there being the most self-explanatory icon in the building. ✨
🎀 Target Z80 options
[-march=CPU[-EXT][+EXT]]
[-local-prefix=PREFIX]
[-colonless]
[-sdcc]
[-fp-s=FORMAT]
[-fp-d=FORMAT]and that's where part 1 wraps for now — but we are NOT done, bestie. more parts are coming, so keep your terminal open and your eyes hydrated. 💖 🦋
GNU as is literally a whole family of assemblers — not one single program, a whole squad. 💅 So if you've used the GNU assembler on one architecture, bestie, you're gonna walk into another architecture and feel right at home. Every version shares so much: object file formats, most assembler directives (the girlies call them pseudo-ops), and the assembler syntax itself. It's giving consistent, honestly. ✨
as is mainly built to assemble the output of the GNU C compiler gcc, so the linker ld can do its thing with it. But no cap, we really did try to make as assemble everything correctly that other assemblers for the same machine would assemble. Any exceptions are documented explicitly — we're not hiding anything. 🙈 That said, it does not mean as always uses the same syntax as some other assembler for the same architecture. Like, we know of several incompatible versions of 680x0 assembly language syntax. Several. 😭 So yeah, vibe check your syntax before you assume.
Every single time you run as, it assembles exactly one source program. That source program can be made up of one or more files. (And yes, standard input counts as a file too. 🎀)
You hand as a command line with zero or more input file names. The input files get read left to right, in order. And here's the thing — a command-line argument (in any position) that has no special meaning? It's just taken as an input file name. Simple as that. 💖
If you give as no file names at all, it tries to read one input file from the as standard input, which is normally your terminal. You may have to type ctl-D to tell as there's no more program left to assemble. Like, "that's it bestie, I'm done typing." 🫶
Use -- if you need to explicitly name the standard input file in your command line. Periodt.
If the source is empty, as produces a small, empty object file. Tiny. Little baby object file. 🦋
as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly. So like, a warning is "hmm okay we're rolling with it 💀" and an error is "we're DONE here, assembly halted." 🛑
If you're invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and from -Wa) by commas. For example:
gcc -c -g -O -Wa,-alh,-L file.cThis passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table). Look at us, communicating. 😌
Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.) Lowkey the compiler's already handling it, but now you know how to peek. 👑
✨ OPTIONS ✨
@file— Read command-line options from file. The options read are inserted in place of the original@fileoption. If file does not exist, or cannot be read, then the option will be treated literally, and not removed. 🫠
Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively. It's @files all the way down, bestie. 🌀
-a[cdghilmns]— Turn on listings, in any of a variety of ways:-ac— omit false conditionals-ad— omit debugging directives-ag— include general information, likeasversion and options passed-ah— include high-level source-al— include assembly-ali— include assembly with ginsn-am— include macro expansions-an— omit forms processing-as— include symbols=file— set the name of the listing file
You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls. Mix and match, just respect the order. 💅
--alternate— Begin in alternate macro mode.--compress-debug-sections— Compress DWARF debug sections usingzlibwithSHF_COMPRESSEDfrom the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities. ⚠️ Note if compression would make a given section larger, then it is not compressed. We're not out here making your files bigger for the aesthetic, bestie. 🙅--compress-debug-sections=none--compress-debug-sections=zlib--compress-debug-sections=zlib-gnu--compress-debug-sections=zlib-gabi--compress-debug-sections=zstd— These options control how DWARF debug sections are compressed.--compress-debug-sections=noneis equivalent to--nocompress-debug-sections.--compress-debug-sections=zliband--compress-debug-sections=zlib-gabiare equivalent to--compress-debug-sections.--compress-debug-sections=zlib-gnucompresses DWARF debug sections using the obsoletedzlib-gnuformat. The debug sections are renamed to begin with.zdebug.--compress-debug-sections=zstdcompresses DWARF debug sections usingzstd. Note — if compression would actually make a section larger, then it is not compressed nor renamed. 👑--nocompress-debug-sections— Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.-D— Enable debugging in target specific backends, if supported. Otherwise ignored. Even if ignored, this option is accepted for script compatibility with calls to other assemblers. It's giving "we'll take it even if we don't use it." 😌--debug-prefix-map old=new— When assembling files in directory old, record debugging information describing them as in new instead.--defsym sym=value— Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading0xindicates a hexadecimal value, and a leading0indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a.setpseudo-op. 🎀--dump-config— Displays how the assembler is configured and then exits. Peek behind the curtain. ✨--elf-stt-common=no--elf-stt-common=yes— These options control whether the ELF assembler should generate common symbols with theSTT_COMMONtype. The default can be controlled by a configure option--enable-elf-stt-common.--emit-local-absolute— Emit even pre-defined (local) absolute symbols to the outgoing symbol table. Note that this isn't the exact opposite of--strip-local-absolute. Okay so like, related but not the reverse. Don't get it twisted. 💀--emulation=name— If the assembler is configured to support multiple different target configurations then this option can be used to select the desired form.-f— "fast" — skip whitespace and comment preprocessing (assume source is compiler output). Zoom zoom. 🏎️-g--gen-debug— Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means eitherSTABS,ECOFForDWARF2. When the debug format is DWARF then a.debug_infoand.debug_linesection is only emitted when the assembly file doesn't generate one itself.--gstabs— Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.--gstabs+— Generate stabs debugging information for each assembler line, with GNU extensions that probably onlygdbcan handle, and that could make other debuggers crash or refuse to read your program. ⚠️ This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time. It's giving main character energy that other debuggers simply cannot handle. 💅--gdwarf-2— Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note — this option is only supported by some targets, not all of them. So check your target first, bestie. 🫶--gdwarf-3— This option is the same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.--gdwarf-4— This option is the same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.--gdwarf-5— This option is the same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis. (Yes, 3, 4, and 5 all say the exact same "maybe, maybe not" thing. That's the bit. 🌈)--gdwarf-sections— Instead of creating a.debug_linesection, create a series of.debug_line.foosections where foo is the name of the corresponding code section. For example a code section called.text.funcwill have its dwarf line number information placed into a section called.debug_line.text.func. If the code section is just called.textthen debug line section will still be called just.debug_linewithout any suffix. Organized. Obsessed. 🎀--gdwarf-cie-version=version— Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specified the default is version 1, though some targets can modify this default. Other possible values for version are3or4.--generate-missing-build-notes=yes--generate-missing-build-notes=no— These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the--enable-generate-build-notesconfigure option.--gsframe,--gsframe,--gsframe=no,--gsframe=yes— Create.sframesection from CFI directives. The explicit--gsframe=yesoption behaves the same as--gsframe. Generation can be suppressed with--gsframe=no. The default can be controlled by a configure option--enable-default-sframe. 🦋--hash-size N— Ignored. Supported for command line compatibility with other assemblers. It's just there to be polite. 🙈--help— Print a summary of the command-line options and exit. Your rescue text. 💖--target-help— Print a summary of all target specific options and exit.--info— Don't suppress informational messages.--no-info— Suppress informational messages. 🤫-I dir— adds the directory dir to the search list for.includedirectives. So when your code pulls an.include, as goes hunting in dir too. Bestie behavior, fr fr. 🫶-J— don't warn about signed overflow. That's it. Not me being chill about overflow, it's literally just the flag. ✨-K— issue warnings when difference tables are altered for long displacements. Niche? Yes. Iconic? Also yes. 💅-L,--keep-locals— keeps local symbols in the symbol table. These lil guys start with system-specific local label prefixes — typically.Lon ELF systems, orLon traditionala.outsystems. Hold onto your locals, queen. 👑--listing-lhs-width=number— sets the maximum width, in words, of the output data column for an assembler listing to number.--listing-lhs-width2=number— same vibe, but for continuation lines in an assembler listing. Max width in words of the output data column = number.--listing-rhs-width=number— sets the maximum width of an input source line, as displayed in a listing, to number bytes. Bytes, not words. Read the units, bestie. 🦋--listing-cont-lines=number— sets the maximum number of lines printed in a listing for a single line of input to number + 1. The+1is real and it's not a typo. The math is mathing. 😭--multibyte-handling=allow,--multibyte-handling=warn,--multibyte-handling=warn-sym-only,--multibyte-handling=warn_sym_only— this one controls how the assembler handles multibyte characters in the input. Lowkey important, here's the tea:allowis the default, and it lets those characters through without complaint. You can restore this default by passing theallowargument.warnmakes the assembler generate a warning message whenever any multibyte character is encountered.warn-sym-onlyonly triggers a warning when a symbol is defined with a name that contains multibyte characters. (References to undefined symbols will not generate a warning.) Note thatwarn-sym-onlyandwarn_sym_onlyare the same thing, just with different punctuation energy.
--no-pad-sections— stops the assembler from padding the ends of output sections to the alignment of that section. The default is to pad the sections, but that can waste space, and space might be exactly what you're missing on targets with tight memory constraints. 🫣-o objfile— names the object-file output from as objfile. The classic. The blueprint. ✨-R— folds the data section into the text section. Sections merging, we love to see it. 🌈--reduce-memory-overheads— ignored. It's only supported for compatibility with tools that pass the same option to both the assembler and the linker. So it does nothing, but it does nothing politely. 🙈--scfi=experimental— controls whether the assembler should synthesize CFI for hand-written input. Buckle up, here's the full tea:- If the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning.
--scfi=experimentalis not intended to be used for compiler-generated code, including inline assembly.- This experimental support is work in progress.
- Only System V AMD64 ABI is supported.
- Each input function in assembly must begin with the
.typedirective, and should ideally be closed off using a.sizedirective. - When using SCFI, each
.typedirective prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry). Which implies that with each.typedirective, a previous block of instructions, if any, is finalised as a distinct FDE.
Okay so the takeaways: experimental, work in progress, AMD64 System V only, and .type is not optional. Respect the rules or get clowned by the assembler. 💀
--sectname-subst— honor substitution sequences in section names. Periodt.--size-check=error,--size-check=warning— issue an error or warning for an invalid ELF.sizedirective. Pick your fighter. 🥊--statistics— prints the maximum space (in bytes) and total time (in seconds) used by assembly. Receipts!! ✨--strip-local-absolute— removes local absolute symbols from the outgoing symbol table. Bye bestie, we won't miss you. 💜-v,--verbose— print the as version.--version,-version— print the as version and exit. Same info as above but it dips immediately. Main character exit. 👑-W,--no-warn— suppresses warning messages.--warn— don't suppress warning messages, and don't treat them as errors either. Just let them live.--fatal-warnings— treats warnings as errors. Every warning is now a whole situation. 😭-w— ignored.-x— ignored.-Z— generate an object file even after errors. Chaotic. Respect. 🔥-- | files ...— standard input, or source files to assemble.
The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64) 🦋
-EB— specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.-EL— specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.-mabi=abi— specifies which ABI the source code uses. The recognized arguments are:ilp32andlp64, which decide whether the generated object file is in ELF32 or ELF64 format respectively. The default islp64.-mcpu=processor[+extension...]— specifies the target processor. The assembler will issue an error message if you try to assemble an instruction which will not execute on the target processor. The following processor names are recognized:cortex-a34,cortex-a35,cortex-a53,cortex-a55,cortex-a57,cortex-a65,cortex-a65ae,cortex-a72,cortex-a73,cortex-a75,cortex-a76,cortex-a76ae,cortex-a77,cortex-a78,cortex-a78ae,cortex-a78c,cortex-a510,cortex-a520,cortex-a710,cortex-a720,ares,exynos-m1,falkor,neoverse-n1,neoverse-n2,neoverse-e1,neoverse-v1,qdf24xx,saphira,thunderx,vulcan,xgene1xgene2,cortex-r82,cortex-x1,cortex-x2,cortex-x3, andcortex-x4. (And yes,xgene1andxgene2are missing a comma between them in the source — I'm not fixing the lore, I'm just reporting it. 🙈) The special nameallmay be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions.
In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.
If some implementations of a particular processor can have an extension, then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions. Slay, auto-config. 💅
-march=architecture[+extension...]— specifies the target architecture. The assembler will issue an error message if you try to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized:armv8-a,armv8.1-a,armv8.2-a,armv8.3-a,armv8.4-aarmv8.5-a,armv8.6-a,armv8.7-a,armv8.8-a,armv8.9-a,armv8-r,armv9-a,armv9.1-a,armv9.2-a,armv9.3-a,armv9.4-aandarmv9.5-a.
If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assembler will default to -mcpu=all.
The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu, extensions are not always enabled by default. So don't assume, bestie. 🌸
-mverbose-error— enables verbose error messages for AArch64 gas. This option is enabled by default.-mno-verbose-error— disables verbose error messages in AArch64 gas.-menable-sysreg-checking— enables error messages that are issued if an attempt is made to assemble a system register access which will not execute on the target architecture. Vibe check: failed. 🚫
The following options are available when as is configured for an Alpha processor 🧚
-mcpu— specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the.archdirective.
The following processor names are recognized: 21064, 21064a, 21066, 21068, 21164, 21164a, 21164pc, 21264, 21264a, 21264b, ev4, ev5, lca45, ev5, ev56, pca56, ev6, ev67, ev68. (Yes, ev5 is in there twice. No, I'm not removing it. The list is the list. 💀) The special name all may be used to allow the assembler to accept instructions valid for any Alpha processor.
In order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the electro-vlasic names (e.g. ev4) do not.
-mdebug,-no-mdebug— enables or disables the generation of.mdebugencapsulation for stabs directives and procedure descriptors. The default is to automatically enable.mdebugwhen the first stabs directive is seen.-relax— forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Heads up though: this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications.-replace,-noreplace— enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets, and-replaceis the default. See section 1.4.1 of the OpenVMS Linker Utility Manual.-g— used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect.-Gsize— a local common symbol larger than size is placed in.bss, while smaller symbols are placed in.sbss. Size-based sorting, we love a decisive king. ⭐-F,-32addr— these options are ignored for backward compatibility.
The following options are available when as is configured for an ARC processor 🌈
-mcpu=cpu— selects the core processor variant.-EB|-EL— select either big-endian (-EB) or little-endian (-EL) output.-mcode-density— enable Code Density extension instructions.
The following options are available when as is configured for the ARM processor family 🎀
-mcpu=processor[+extension...]— specify which ARM processor variant is the target.-march=architecture[+extension...]— specify which ARM architecture variant is used by the target.-mfpu=floating-point-format— select which Floating Point architecture is the target.-mfloat-abi=abi— select which floating point ABI is in use.-mthumb— enable Thumb only instruction decoding.-mapcs-32|-mapcs-26|-mapcs-float|-mapcs-reentrant— select which procedure calling convention is in use.-EB|-EL— select either big-endian (-EB) or little-endian (-EL) output.-mthumb-interwork— specify that the code has been generated with interworking between Thumb and ARM code in mind.-mccs— flips on CodeComposer Studio assembly syntax compatibility mode. slay ✨-k— announces that PIC code has been generated. that's it, that's the whole job 💅
The following options are available when as is configured for the Blackfin processor family. 👑
-mcpu=processor[-sirevision]— picks your target processor. the optional-sirevisionis literally not used by the assembler at all — it's just hanging out here so GCC can easily pass down its own-mcpu=option. if you try to assemble an instruction that won't run on the target processor, the assembler WILL throw an error at you. the processor names it recognizes are:bf504,bf506,bf512,bf514,bf516,bf518,bf522,bf523,bf524,bf525,bf526,bf527,bf531,bf532,bf533,bf534,bf535(not implemented yet 🙈),bf536,bf537,bf538,bf539,bf542,bf542m,bf544,bf544m,bf547,bf547m,bf548,bf548m,bf549,bf549m,bf561, andbf592.-mfdpic— assemble for the FDPIC ABI.-mno-fdpic-mnopic— disable-mfdpic.
The following options are available when as is configured for the Linux kernel BPF processor family. 🦋
@chapter BPF Dependent FeaturesBPF Options
-EB— tells the assembler to emit big-endian eBPF.-EL— tells the assembler to emit little-endian eBPF.-mdialect=dialect— picks which assembly language dialect to recognize while assembling. the assembler supportsnormalandpseudoc.-misa-spec=spec— picks which version of the BPF instruction set to use when assembling. the supported BPF ISA versions arev1v2,v3andv4.
you can also pass the value xbpf to recognize extra instructions that GCC uses for testing purposes. but bestie, beware 🚨 — that is not valid BPF.
-mno-relax— tells the assembler to not relax instructions.
ngl, if no endianness option is specified on the command line, the host endianness gets used. see the info pages for documentation of the CRIS-specific options. 🎀
The following options are available when as is configured for the C-SKY processor family. 🌸
-march=archname— assemble for architecture archname. the--helpoption lists the valid values for archname.-mcpu=cpuname— assemble for architecture cpuname. the--helpoption lists the valid values for cpuname.-EL-mlittle-endian— generate little-endian output.-EB-mbig-endian— generate big-endian output.-fpic-pic— generate position-independent code.-mljump-mno-ljump— enable/disable the transformation of the short branch instructionsjbf,jbt, andjbrintojmpi. this one is for V2 processors only. it gets ignored on CK801 and CK802 targets (they don't support thejmpiinstruction), and it's enabled by default for the other processors.-mbranch-stub-mno-branch-stub— pass throughR_CKCORE_PCREL_IMM26BY2relocations forbsrinstructions to the linker.
this option is only available for bare-metal C-SKY V2 ELF targets, where it's enabled by default. it cannot be used in code that will be dynamically linked against shared libraries. 💀
-force2bsr-mforce2bsr-no-force2bsr-mno-force2bsr— enable/disable the transformation ofjbsrinstructions intobsr. this option is always enabled (and-mno-force2bsris straight-up ignored) for CK801/CK802 targets. it's also always enabled when-mbranch-stubis in effect.-jsri2bsr-mjsri2bsr-no-jsri2bsr-mno-jsri2bsr— enable/disable the transformation ofjsriinstructions intobsr. enabled by default.-mnolrw-mno-lrw— enable/disable the transformation oflrwinstructions into amovih/oripair.-melrw-mno-elrw— enable/disable extendedlrwinstructions. enabled by default for CK800-series processors.-mlaf-mliterals-after-func-mno-laf-mno-literals-after-func— enable/disable placement of literal pools after each function.-mlabr-mliterals-after-br-mno-labr-mnoliterals-after-br— enable/disable placement of literal pools after unconditional branches. enabled by default.-mistack-mno-istack— enable/disable interrupt stack instructions. enabled by default on CK801, CK802, and CK802 processors.
The following options explicitly enable certain optional instructions. these features also get enabled implicitly by using -mcpu= to specify a processor that supports them. ✨
-mhard-float— enable hard float instructions.-mmp— enable multiprocessor instructions.-mcp— enable coprocessor instructions.-mcache— enable cache prefetch instruction.-msecurity— enable C-SKY security instructions.-mtrust— enable C-SKY trust instructions.-mdsp— enable DSP instructions.-medsp— enable enhanced DSP instructions.-mvdsp— enable vector DSP instructions.
The following options are available when as is configured for an Epiphany processor. 🧚
-mepiphany— specifies that both 32 and 16 bit instructions are allowed. this is the default behavior.-mepiphany16— restricts the permitted instructions to just the 16 bit set.
The following options are available when as is configured for an H8/300 processor. 💜
@chapter H8/300 Dependent FeaturesOptions
The Renesas H8/300 version of as has one machine-dependent option:
-h-tick-hex— supportH'00style hex constants in addition to0x00style.-mach=name— sets the H8300 machine variant. the machine names recognized are:h8300h,h8300hn,h8300s,h8300sn,h8300sxandh8300sxn.
The following options are available when as is configured for an i386 processor. 👑
--32|--x32|--64— select the word size, either 32 bits or 64 bits.--32implies Intel i386 architecture, while--x32and--64imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.
these options are only available with the ELF object file format, and they require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure to enable 64-bit usage and use x86-64 as the target platform).
-n— by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such asleal 0(%esi,1),%esi. this switch disables that optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.--divide— on SVR4-derived platforms, the character/is treated as a comment character, which means it can't be used in expressions. the--divideoption turns/into a normal character. this does not disable/at the beginning of a line starting a comment, and it doesn't affect using#for starting a comment.-march=CPU[+EXTENSION...]— picks the target processor. the assembler will throw an error message if you attempt to assemble an instruction that won't execute on the target processor. the processor names recognized are:i8086,i186,i286,i386,i486,i586,i686,pentium,pentiumpro,pentiumii,pentiumiii,pentium4,prescott,nocona,core,core2,corei7,iamcu,k6,k6_2,athlon,opteron,k8,amdfam10,bdver1,bdver2,bdver3,bdver4,znver1,znver2,znver3,znver4,znver5,znver6,btver1,btver2,generic32andgeneric64.
on top of the basic instruction set, the assembler can be told to accept various extension mnemonics. for example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. the extensions currently supported are:
8087, 287, 387, 687, "cmov", "fxsr", "mmx", "sse", "sse2", "sse3",
"sse4a", "ssse3", "sse4.1", "sse4.2", "sse4", "avx", "avx2",
"lahf_sahf", "monitor", "adx", "rdseed", "prfchw", "smap", "mpx", "sha",
"rdpid", "ptwrite", "cet", "gfni", "vaes", "vpclmulqdq", "prefetchwt1",
"clflushopt", "se1", "clwb", "movdiri", "movdir64b", "enqcmd",
"serialize", "tsxldtrk", "kl", "widekl", "hreset", "avx512f",
"avx512cd", "avx512er", "avx512pf", "avx512vl", "avx512bw", "avx512dq",
"avx512ifma", "avx512vbmi", "avx512_4fmaps", "avx512_4vnniw",
"avx512_vpopcntdq", "avx512_vbmi2", "avx512_vnni", "avx512_bitalg",
"avx512_vp2intersect", "tdx", "avx512_bf16", "avx_vnni", "avx512_fp16",
"avx512_bmm", "prefetchi", "avx_ifma", "avx_vnni_int8", "cmpccxadd",
"wrmsrns", "msrlist", "avx_ne_convert", "rao_int", "fred", "lkgs",
"avx_vnni_int16", "sha512", "sm3", "sm4", "pbndkb", "avx10.1",
"avx10.1/512", "avx10.1/256", "avx10.1/128", "user_msr", "msr_imm",
"apx_f", "apx_nci", "apx_ndd", "apx_nf", "apx_nci_ndd_nf", "avx10.2",
"avx10.2/512", "avx10.2/256", "avx10.2/128", "movrs", "amx_int8",
"amx_bf16", "amx_fp16", "amx_complex", "amx_transpose", "amx_tf32",
"amx_fp8" "amx_movrs", "amx_avx512", "amx_tile", "vmx", "vmfunc", "smx",
"xsave", "xsaveopt", "xsavec", "xsaves", "aes", "pclmul", "fsgsbase",
"rdrnd", "f16c", "bmi2", "fma", "movbe", "ept", "lzcnt", "popcnt",
"hle", "rtm", "tsx", "invpcid", "clflush", "mwaitx", "clzero",
"wbnoinvd", "pconfig", "waitpkg", "uintr", "cldemote", "rdpru",
"mcommit", "sev_es", "lwp", "fma4", "xop", "cx16", "syscall", "rdtscp",
"3dnow", "3dnowa", "sse4a", "sse5", "snp", "invlpgb", "tlbsync",
"rmpquery", "rmpread", "svme", "gmism2", "gmiccs", "padlockrng2",
"padlockphe2", "padlockxmodx" and "padlock".heads up 🫶 — these extension mnemonics can be prefixed with no to revoke the respective (and any dependent) functionality. and note further that the suffixes permitted on -march=avx10.<N> enforce a vector length restriction, i.e. despite these otherwise being "enabling" options, using these suffixes will disable all insns with wider vector or mask register operands.
and when the.archdirective is used with-march, the.archdirective will take precedent. periodt.
-mtune=CPU— picks a processor to optimize for. when used in conjunction with the-marchoption, only instructions of the processor specified by the-marchoption will be generated.
valid CPU values are identical to the processor list of -march=CPU. 🌈
okay bestie, next up we got the operand check options, and they're giving safety inspector energy 💅
these options control if the assembler checks certain instruction operands or operand combos. like, for example, instructions where the operand size can't be inferred from its operands and you also didn't specify it with an instruction suffix. then:
-moperand-check=none— assembler skips these checks entirely.-moperand-check=warning— assembler warns you when checks fail. this is the default, bestie.-moperand-check=error— assembler throws an error when checks fail.
-msse2avx— tells the assembler to encode SSE instructions with VEX prefix, which means you need AVX available. and if those SSE instructions use extended GPRs, they get encoded with EVEX prefix, so you need AVX512 or AVX10. slay but make sure your CPU is ready ✨-muse-unaligned-vector-move— makes the assembler encode aligned vector moves as unaligned vector moves. lowkey wild but ok.
these options control whether the assembler checks SSE instructions:
-msse-check=none— no checks on SSE instructions. this is the default.-msse-check=warning— warns you for any SSE instruction.-msse-check=error— errors out for any SSE instruction.
these control how scalar AVX instructions get encoded:
-mavxscalar=128— encodes scalar AVX instructions with 128-bit vector length. this is the default.-mavxscalar=256— encodes scalar AVX instructions with 256-bit vector length.
⚠️ WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models.
these control how VEX.W-ignored (WIG) VEX instructions get encoded:
-mvexwig=0— encodes WIG VEX instructions withvex.w = 0. this is the default.-mvexwig=1— encodes WIG EVEX instructions withvex.w = 1.
⚠️ WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models.
these control how length-ignored (LIG) EVEX instructions get encoded:
-mevexlig=128— encodes LIG EVEX instructions with 128-bit vector length. default.-mevexlig=256— encodes LIG EVEX instructions with 256-bit vector length.-mevexlig=512— encodes LIG EVEX instructions with 512-bit vector length.
these control how w-ignored (WIG) EVEX instructions get encoded:
-mevexwig=0— encodes WIG EVEX instructions withevex.w = 0. default.-mevexwig=1— encodes WIG EVEX instructions withevex.w = 1.
-mmnemonic=att— sets instruction mnemonic for matching instructions to AT&T.-mmnemonic=intel— sets instruction mnemonic for matching instructions to Intel.- The
.att_mnemonicand.intel_mnemonicdirectives take precedence over this.
-msyntax=att— sets instruction syntax to AT&T when processing instructions.-msyntax=intel— sets instruction syntax to Intel when processing instructions.- The
.att_syntaxand.intel_syntaxdirectives take precedence over this.
-mnaked-reg— says registers don't need the%prefix. but the.att_syntaxand.intel_syntaxdirectives take precedence.
-madd-bnd-prefix— forces the assembler to slap BND prefix on all branches, even if you didn't write it in the source. bold 👑
-mno-shared— on ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. the-msharedoption tells the assembler to generate code that may go into a shared library where all non-weak global branch targets with default visibility can be preempted. the resulting code is slightly bigger. this option only affects the handling of branch instructions.
-mbig-obj— on PE/COFF target, forces the use of big object file format, which lets you have more than 32768 sections. huge.
these control how the assembler encodes the lock prefix. it's a workaround for processors that fail on lock prefix. can only be safely used with single-core, single-thread computers, bestie.
-momit-lock-prefix=yes— omits all lock prefixes.-momit-lock-prefix=no— encodes lock prefix as usual. this is the default.
these control how the assembler encodes lfence, mfence and sfence:
-mfence-as-lock-add=yes— encodeslfence,mfenceandsfenceaslock addl $0x0, (%rsp)in 64-bit mode andlock addl $0x0, (%esp)in 32-bit mode.-mfence-as-lock-add=no— encodes them as usual. this is the default.
these control whether the assembler generates relax relocations: R_386_GOT32X in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX in 64-bit mode.
-mrelax-relocations=yes— generates relax relocations.-mrelax-relocations=no— doesn't generate relax relocations.
these control whether the assembler checks tls relocation:
-mtls-check=yes— checks tls relocation.-mtls-check=no— doesn't check tls relocation. the default can be controlled by the configure option--enable-x86-tls-check.
-malign-branch-boundary=NUM— controls how the assembler aligns branches with segment prefixes or NOP.NUMmust be a power of 2. it should be0or no less than16. branches get aligned within aNUMbyte boundary.-malign-branch-boundary=0(the default) doesn't align branches.
-malign-branch=TYPE[+TYPE...]— picks which types of branches to align.TYPEis a combo of:jcc(aligns conditional jumps),fused(aligns fused conditional jumps),jmp(aligns unconditional jumps),call(aligns calls),ret(aligns rets),indirect(aligns indirect jumps and calls). the default is-malign-branch=jcc+fused+jmp.
-malign-branch-prefix-size=NUM— sets the max number of prefixes on an instruction to align branches.NUMshould be between0and5. defaultNUMis5.
-mbranches-within-32B-boundaries— aligns conditional jumps, fused conditional jumps and unconditional jumps within a 32-byte boundary with up to 5 segment prefixes on an instruction. it's equivalent to-malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5. the default doesn't align branches.
these control whether the assembler generates lfence after load instructions:
-mlfence-after-load=yes— generateslfence.-mlfence-after-load=no— doesn't generatelfence. this is the default.
these control whether the assembler generates lfence before indirect near branch instructions:
-mlfence-before-indirect-branch=all— generateslfencebefore indirect near branch via register and issues a warning before indirect near branch via memory. it also implicitly sets-mlfence-before-ret=shlwhen there's no explicit-mlfence-before-ret=.-mlfence-before-indirect-branch=register— generateslfencebefore indirect near branch via register.-mlfence-before-indirect-branch=memory— issues a warning before indirect near branch via memory.-mlfence-before-indirect-branch=none— nolfence, no warning. this is the default.
heads up: lfence won't be generated before indirect near branch via register with -mlfence-after-load=yes since lfence will be generated after loading branch target register.
these control whether the assembler generates lfence before ret:
-mlfence-before-ret=or— generates anorinstruction withlfence.-mlfence-before-ret=shland-mlfence-before-ret=yes— generate ashlinstruction withlfence.-mlfence-before-ret=not— generates anotinstruction withlfence.-mlfence-before-ret=none— nolfence. this is the default.
these control whether the assembler generates GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes. the default can be controlled by the --enable-x86-used-note configure option.
-mx86-used-note=no— don't generate those notes.-mx86-used-note=yes— generate those notes.
these control how the assembler encodes SAE-only EVEX instructions:
-mevexrcig=rne— encodes RC bits of EVEX instruction with00. this is the default.-mevexrcig=rd— encodes with01RC bits.-mevexrcig=ru— encodes with10RC bits.-mevexrcig=rz— encodes with11RC bits.
-mamd64— in 64-bit mode, accept only AMD64 ISA.-mintel64— in 64-bit mode, accept only Intel64 ISA.- the default is to accept common, Intel64 only and AMD64 ISAs.
-O0,-O,-O1,-O2,-Os— optimize instruction encoding for smaller instruction size.-Oand-O1do a bunch of stuff: encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with 32-bit register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions, encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions, and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical.
that's a whole lot of encoding magic, bestie 🪄✨
-O2— this is-O1optimization plus it encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions. And bestie, in 64-bit mode, VEX encoded instructions that have commutative source operands will also get their source operands swapped if that lets it use the 2-byte VEX prefix form instead of the 3-byte one. Certain forms ofANDas well asORwith the same (register) operand specified twice will also be changed toTEST. iconic behavior tbh 💅-Os— this one is-O2optimization plus it encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. And-O0turns off this optimization. periodt ✨
🌸 IP2K, but make it extended 🌸
The following options are available when as is configured for the Ubicom IP2K series. 🦋
-mip2022ext— says the extended IP2022 instructions are allowed. go off 💅-mip2022— restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. back to basics bestie 🙈
🎀 Renesas M32C and M16C 🎀
The following options are available when as is configured for the Renesas M32C and M16C processors. ✨
-m32c— assemble M32C instructions.-m16c— assemble M16C instructions (this one is the default).-relax— enable support for link-time relaxations. chill vibes 🧘-h-tick-hex— supportH'00style hex constants in addition to0x00style. two hexes, one assembler 💜
🌈 Renesas M32R (formerly Mitsubishi M32R) 🌈
The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series. 🦋
--m32rx— specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX. glow-up moment ⭐--warn-explicit-parallel-conflictsor--Wp— produce warning messages when questionable parallel constructs are encountered. 👀--no-warn-explicit-parallel-conflictsor--Wnp— do not produce warning messages when questionable parallel constructs are encountered. minding my own business fr fr 🙈
💀 Motorola 68000 series 💀
The following options are available when as is configured for the Motorola 68000 series. 🔥
-l— shorten references to undefined symbols, to one word instead of two. efficiency queen 👑-m68000|-m68008|-m68010|-m68020|-m68030|-m68040|-m68060|-m68302|-m68331|-m68332|-m68333|-m68340|-mcpu32|-m5200— specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time. pick your fighter 💅-m68881|-m68882|-mno-68881|-mno-68882— the target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor. weird combo but ok we love a crossover episode 🫶-m68851|-mno-68851— the target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up.
For details about the PDP-11 machine dependent features options, see PDP-11-Options. no cap, go read that one 💖
-mpic|-mno-pic— generate position-independent (or position-dependent) code. The default is-mpic. ✨-mall-mall-extensions— enable all instruction set extensions. This is the default. everything everywhere all at once 🦋-mno-extensions— disable all instruction set extensions. nope, none, zero 🙅♀️-mextension|-mno-extension— enable (or disable) a particular instruction set extension. à la carte bestie 🍓-mcpu— enable the instruction set extensions supported by a particular CPU, and disable all other extensions.-mmachine— enable the instruction set extensions supported by a particular machine model, and disable all other extensions.
🧚 picoJava, little and big 🧚
The following options are available when as is configured for a picoJava processor. 🌸
-mb— generate "big endian" format output.-ml— generate "little endian" format output.
🔥 PRU processor 🔥
The following options are available when as is configured for a PRU processor. 💜
-mlink-relax— assume thatLDwould optimizeLDI32instructions by checking the upper 16 bits of the expression. If they are all zeros, thenLDwould shorten theLDI32instruction to a singleLDI. In such case"as"will outputDIFFrelocations for diff expressions. manifesting that shortening 🕯️-mno-link-relax— assume thatLDwould not optimizeLDI32instructions. As a consequence,DIFFrelocations will not be emitted.-mno-warn-regname-label— do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off. iykyk 💅
👑 MIPS processor, the main character 👑
The following options are available when as is configured for a MIPS processor. ✨
-Gnum — this option sets the largest size of an object that can be referenced implicitly with the"gp"register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8.-EB— generate "big endian" format output.-EL— generate "little endian" format output.-mips1-mips2-mips3-mips4-mips5-mips32-mips32r2-mips32r3-mips32r5-mips32r6-mips64-mips64r2-mips64r3-mips64r5-mips64r6— generate code for a particular MIPS Instruction Set Architecture level.-mips1is an alias for-march=r3000,-mips2is an alias for-march=r6000,-mips3is an alias for-march=r4000and-mips4is an alias for-march=r8000.-mips5,-mips32,-mips32r2,-mips32r3,-mips32r5,-mips32r6,-mips64,-mips64r2,-mips64r3,-mips64r5, and-mips64r6correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. so many eras, all valid 💖-march=cpu — generate code for a particular MIPS CPU.-mtune=cpu — schedule and tune for a particular MIPS CPU.-mfix7000-mno-fix7000— cause nops to be inserted if the read of the destination register of anmfhiormfloinstruction occurs in the following two instructions.-mfix-rm7000-mno-fix-rm7000— cause nops to be inserted if admultordmultuinstruction is followed by a load instruction.-mfix-r5900-mno-fix-r5900— do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a"nop"instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. hardware said no 😭-mdebug-no-mdebug— cause stabs-style debugging output to go into an ECOFF-style.mdebugsection instead of the standard ELF.stabssections.-mpdr-mno-pdr— control generation of".pdr"sections.-mgp32-mfp32— the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times.-mgp32controls the size of general-purpose registers and-mfp32controls the size of floating-point registers.-mgp64-mfp64— the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times.-mgp64controls the size of general-purpose registers and-mfp64controls the size of floating-point registers.-mfpxx— the register sizes are normally inferred from the ISA and ABI, but using this flag in combination with-mabi=32enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide. flexible queen 💅-modd-spreg-mno-odd-spreg— enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA.-mfpxximplies-mno-odd-spreg, otherwise the default is-modd-spreg.-mips16-no-mips16— generate code for the MIPS 16 processor. This is equivalent to putting".module mips16"at the start of the assembly file.-no-mips16turns off this option.-mmips16e2-mno-mips16e2— enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting".module mips16e2"at the start of the assembly file.-mno-mips16e2turns off this option.-mmicromips-mno-micromips— generate code for the microMIPS processor. This is equivalent to putting".module micromips"at the start of the assembly file.-mno-micromipsturns off this option. This is equivalent to putting".module nomicromips"at the start of the assembly file.-msmartmips-mno-smartmips— enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting".module smartmips"at the start of the assembly file.-mno-smartmipsturns off this option. big brain energy 🧠-mips3d-no-mips3d— generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions.-no-mips3dturns off this option.-mdmx-no-mdmx— generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions.-no-mdmxturns off this option.-mdsp-mno-dsp— generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions.-mno-dspturns off this option.-mdspr2-mno-dspr2— generate code for the DSP Release 2 Application Specific Extension. This option implies-mdsp. This tells the assembler to accept DSP Release 2 instructions.-mno-dspr2turns off this option.-mdspr3-mno-dspr3— generate code for the DSP Release 3 Application Specific Extension. This option implies-mdspand-mdspr2. This tells the assembler to accept DSP Release 3 instructions.-mno-dspr3turns off this option.-mmsa-mno-msa— generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions.-mno-msaturns off this option.-mxpa-mno-xpa— generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions.-mno-xpaturns off this option.-mmt-mno-mt— generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions.-mno-mtturns off this option.
-mmcu,-mno-mcu— makes code for the MCU Application Specific Extension ✨ basically you're telling the assembler "hey bestie, accept MCU instructions pls".-mno-mcuturns it right back off 💅-mcrc,-mno-crc— generates code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. Same deal: the assembler starts accepting CRC instructions.-mno-crcshuts it down.-mginv,-mno-ginv— for the Global INValidate (GINV) Application Specific Extension 🌸 tells the assembler to accept GINV instructions.-mno-ginv= off.-mloongson-mmi,-mno-loongson-mmi— generates code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. The assembler accepts MMI instructions.-mno-loongson-mmiturns it off.-mloongson-cam,-mno-loongson-cam— code for the Loongson Content Address Memory (CAM) instructions 🧚 the assembler accepts Loongson CAM instructions.-mno-loongson-cam= nope, off.-mloongson-ext,-mno-loongson-ext— generates code for the Loongson EXTensions (EXT) instructions. Assembler accepts Loongson EXT instructions.-mno-loongson-extturns it off.-mloongson-ext2,-mno-loongson-ext2— code for the Loongson EXTensions R2 (EXT2) instructions. Heads up bestie: this one implies-mloongson-ext👀 and it tells the assembler to accept Loongson EXT2 instructions.-mno-loongson-ext2turns this option off.-minsn32,-mno-insn32— only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions. It's equivalent to putting.set insn32at the start of the assembly file.-mno-insn32turns this option off — equivalent to putting.set noinsn32at the start of the assembly file. By default-mno-insn32is selected, so like, all instructions are fair game 💅--construct-floats,--no-construct-floats—--no-construct-floatsdisables building double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default--construct-floatsis selected, which does allow construction of these floating point constants ✨--relax-branch,--no-relax-branch—--relax-branchenables the relaxation of out-of-range branches 🌈 By default--no-relax-branchis selected, which means any out-of-range branches produce an error. no chill, honestly.-mignore-branch-isa,-mno-ignore-branch-isa— ignore branch checks for invalid transitions between ISA modes 🦋 The semantics of branches don't provide for an ISA mode switch, so in most cases the ISA mode a branch was encoded for has to match the ISA mode of the branch's target label. That's why GAS has checks built in that verify, during branch assembly, that the two ISA modes match.-mignore-branch-isadisables those checks. By default-mno-ignore-branch-isais selected, so any invalid branch that needs a transition between ISA modes throws an error at you 😭-mnan=encoding— pick between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format. The latter is the default. periodt.--emulation=name— okay so this one's giving legacy. It used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so honestly the option serves little purpose now 💀 it's just retained for backwards compatibility.
The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferred options instead 💅
-nocpp—asjust... ignores this option 🙈 it's accepted for compatibility with the native tools.--trap,--no-trap,--break,--no-break— controls how to deal with multiplication overflow and division by zero 🔥--trapor--no-break(they're synonyms) take a trap exception — and they only work for Instruction Set Architecture level 2 and higher, just so you know.--breakor--no-trap(also synonyms, and the default) take a break exception.-n— when this is used,aswill issue a warning every single time it generates anopinstruction from a macro. loud and proud about it, honestly 🎀
🌸 The following options are available when as is configured for a LoongArch processor 🌸
-fpic,-fPIC— generate position-independent code ✨-fno-pic— don't generate position-independent code (default)
💜 The following options are available when as is configured for a Meta processor 💜
-mcpu=metac11— generate code for Meta 1.1.-mcpu=metac12— generate code for Meta 1.2.-mcpu=metac21— generate code for Meta 2.1.-mfpu=metac21— allow code to use FPU hardware of Meta 2.1.
See the info pages for documentation of the MMIX-specific options 👑
🦋 The following options are available when as is configured for a NDS32 processor 🦋
-O1— optimize for performance.-Os— optimize for space.-EL— produce little endian data output.-EB— produce little endian data output. (yep bestie, the page literally says "little endian" for-EBtoo. i don't make the rules, i just report them 💀)-mpic— generate PIC.-mno-fp-as-gp-relax— suppress fp-as-gp relaxation for this file.-mb2bb-relax— back-to-back branch optimization.-mno-all-relax— suppress all relaxation for this file.-march=<arch name>— assemble for architecture <arch name>, which could bev3,v3j,v3m,v3f,v3s,v2,v2j,v2f,v2s.-mbaseline=<baseline>— assemble for baseline <baseline>, which could bev2,v3,v3m.-mfpu-freg=FREG— specify a FPU configuration. TheFREGvalues are:
0 8 SP / 4 DP registers
1 16 SP / 8 DP registers
2 32 SP / 16 DP registers
3 32 SP / 32 DP registers-mabi=abi— specify a abi version; <abi> could bev1,v2,v2fp,v2fpp.-m[no-]mac— enable/disable Multiply instructions support.-m[no-]div— enable/disable Divide instructions support.-m[no-]16bit-ext— enable/disable 16-bit extension.-m[no-]dx-regs— enable/disable d0/d1 registers.-m[no-]perf-ext— enable/disable Performance extension.-m[no-]perf2-ext— enable/disable Performance extension 2.-m[no-]string-ext— enable/disable String extension.-m[no-]reduced-regs— enable/disable Reduced Register configuration (GPR16) option.-m[no-]audio-isa-ext— enable/disable AUDIO ISA extension.-m[no-]fpu-sp-ext— enable/disable FPU SP extension.-m[no-]fpu-dp-ext— enable/disable FPU DP extension.-m[no-]fpu-fma— enable/disable FPU fused-multiply-add instructions.-mall-ext— turn on all extensions and instructions support 🔥 the everything bagel option.
👑 The following options are available when as is configured for a PowerPC processor 👑
-a32— generate ELF32 or XCOFF32.-a64— generate ELF64 or XCOFF64.-K PIC— setEF_PPC_RELOCATABLE_LIBin ELF flags.-mpwrx|-mpwr2— generate code for POWER/2 (RIOS2).-mpwr— generate code for POWER (RIOS1).-m601— generate code for PowerPC 601.-mppc,-mppc32,-m603,-m604— generate code for PowerPC 603/604.-m403,-m405— generate code for PowerPC 403/405.-m440— generate code for PowerPC 440. BookE and some 405 instructions.-m464— generate code for PowerPC 464.-m476— generate code for PowerPC 476.-m7400,-m7410,-m7450,-m7455— generate code for PowerPC 7400/7410/7450/7455.-m750cl,-mgekko,-mbroadway— generate code for PowerPC 750CL/Gekko/Broadway.-m821,-m850,-m860— generate code for PowerPC 821/850/860.-mppc64,-m620— generate code for PowerPC 620/625/630.-me200z2,-me200z4— generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.-me300— generate code for PowerPC e300 family.-me500,-me500x2— generate code for Motorola e500 core complex.-me500mc— generate code for Freescale e500mc core complex.-me500mc64— generate code for Freescale e500mc64 core complex.-me5500— generate code for Freescale e5500 core complex.-me6500— generate code for Freescale e6500 core complex.-mlsp— enable LSP instructions. (Disables SPE and SPE2.)-mspe— generate code for Motorola SPE instructions. (Disables LSP.)-mspe2— generate code for Freescale SPE2 instructions. (Disables LSP.)-mtitan— generate code for AppliedMicro Titan core complex.-mppc64bridge— generate code for PowerPC 64, including bridge insns.-mbooke— generate code for 32-bit BookE.-ma2— generate code for A2 architecture.-maltivec— generate code for processors with AltiVec instructions.-mvle— generate code for Freescale PowerPC VLE instructions.-mvsx— generate code for processors with Vector-Scalar (VSX) instructions.-mhtm— generate code for processors with Hardware Transactional Memory instructions.-mpower4,-mpwr4— generate code for Power4 architecture.-mpower5,-mpwr5,-mpwr5x— generate code for Power5 architecture.-mpower6,-mpwr6— generate code for Power6 architecture.-mpower7,-mpwr7— generate code for Power7 architecture.-mpower8,-mpwr8— generate code for Power8 architecture.-mpower9,-mpwr9— generate code for Power9 architecture.-mpower10,-mpwr10— generate code for Power10 architecture.-mpower11,-mpwr11— generate code for Power11 architecture.-mfuture— generate code for'future'architecture.-mcell— generate code for Cell Broadband Engine architecture.-mcell— generate code for Cell Broadband Engine architecture. (yes it's listed twice in the page. and honestly? iconic. we love a repeat 👑)-mcom— generate code Power/PowerPC common instructions.-many— generate code for any architecture (PWR/PWRX/PPC).-mregnames— allow symbolic names for registers.-mno-regnames— do not allow symbolic names for registers.-mrelocatable— support for GCC's-mrelocatableoption.-mrelocatable-lib— support for GCC's-mrelocatable-liboption.-memb— setPPC_EMBbit in ELF flags.-mlittle,-mlittle-endian,-le— generate code for a little endian machine.-mbig,-mbig-endian,-be— bestie, this one generates code for a big endian machine 💅-nops=count— if an alignment directive ends up inserting more than count nops, it drops a branch at the beginning to skip executing all those nops. so like... strategic skipping, we love efficiency ✨
okay so when as is configured for a RISC-V processor, these are your options, no cap 🫶
-fpic,-fPIC— generate position-independent code 💫-fno-pic— don't generate position-independent code. this is the default, btw ✋-march=ISA|Profiles|Profiles_ISA— picks the base isa, whatever you set withISAorProfilesorProfies_ISA. for example-march=rv32ima,-march=RVI20U64,-march=RVI20U64_d. and if this option and the architecture attributes aren't set, the assembler checks the default configure setting--with-arch=ISA👑-misa-spec=ISAspec— selects the default isa spec version. if the version of ISA isn't set by-march, then the assembler helps set the version according to the default chosen spec. and if this option isn't set, the assembler checks the default configure setting--with-isa-spec=ISAspec🎀-mpriv-spec=PRIVspec— selects the privileged spec version. we can decide whether the CSR is valid or not according to the chosen spec. if this option and the privilege attributes aren't set, the assembler checks the default configure setting--with-priv-spec=PRIVspec🔥-mabi=ABI— selects the ABI, which is either"ilp32"or"lp64", optionally followed by"f","d", or"q"to indicate single-precision, double-precision, or quad-precision floating-point calling convention, ornoneor"e"to indicate the soft-float calling convention (and"e"means a soft-float RVE ABI). so many little letters, so much power 😭-mrelax— takes advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. this is the default 💅-mno-relax— don't do linker relaxations, periodt.-march-attr— generates the default contents for the riscv elf attribute section if the.attributedirectives aren't set. this section records the info a linker or runtime loader needs to check compatibility — the ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of the privileged specification 🌸-mno-arch-attr— don't generate the default riscv elf attribute section if the.attributedirectives aren't set. iconic "no thank you" energy ✨-mcsr-check— enables CSR checking for the ISA-dependent CRS and the read-only CSR. the ISA-dependent CSR are only valid when the specific ISA is set, and the read-only CSR can not be written by the CSR instructions 👀-mno-csr-check— don't do CSR checking. simple as 🦋-mlittle-endian— generate code for a little endian machine 🍓-mbig-endian— generate code for a big endian machine 🍓
fr fr, see the info pages for documentation of the RX-specific options — that's the whole vibe, go read 'em 💖
when as is configured for the s390 processor family, here's what's up:
-m31,-m64— selects the word size, either 31/32 bits or 64 bits 🔢-mesa,-mzarch— selects the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch) 👑-march=processor— specifies which s390 processor variant is the target:g5(orarch3),g6,z900(orarch5),z990(orarch6),z9-109,z9-ec(orarch7),z10(orarch8),z196(orarch9),zEC12(orarch10),z13(orarch11),z14(orarch12),z15(orarch13),z16(orarch14), orz17(orarch15). the way there's a whole family tree in here 😭-mregnames,-mno-regnames— allow or disallow symbolic names for registers ✨-mwarn-areg-zero— warn whenever the operand for a base or index register has been specified but evaluates to zero 🚨-mwarn-regtype-mismatch=strict,-mwarn-regtype-mismatch=relaxed,-mwarn-regtype-mismatch=no,-mno-warn-regtype-mismatch— controls whether the assembler does register name type checks and generates a warning message in case of a mismatch with the operand register type. the default (which you can restore by using therelaxedargument) is to perform relaxed register name type checks, which allow floating point register (FPR) names%f0to%f15to be specified as argument to vector register (VR) operands, and vector register (VR) names%v0to%v15to be specified as argument to floating point register (FPR) operands. this is acceptable because the FPR are embedded into the lower half of the VR 💅 using thestrictargument, strict register name type checks are performed. thenoargument, which is equivalent to-mno-warn-regtype-mismatch, disables any register name type checks 🫶
when as is configured for a TMS320C6000 processor:
-march=arch— enable (only) instructions from architecture arch. by default, all instructions are permitted ✨
the following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x" 🎀
-mdsbt,-mno-dsbt— the-mdsbtoption makes the assembler generate the"Tag_ABI_DSBT"attribute with a value of1, indicating that the code is using DSBT addressing. the-mno-dsbtoption, which is the default, makes the tag have a value of0, indicating that the code does not use DSBT addressing. and bestie, the linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together 😭-mpid=no,-mpid=near,-mpid=far— the-mpid=option makes the assembler generate the"Tag_ABI_PID"attribute with a value indicating the form of data addressing used by the code.-mpid=no, the default, indicates position-dependent data addressing,-mpid=nearindicates position-independent addressing with GOT accesses using near DP addressing, and-mpid=farindicates position-independent addressing with GOT accesses using far DP addressing. the linker will emit a warning if objects built with different settings of this option are linked together 🚨-mpic,-mno-pic— the-mpicoption makes the assembler generate the"Tag_ABI_PIC"attribute with a value of1, indicating that the code is using position-independent code addressing. the"-mno-pic"option, the default, makes the tag have a value of0, indicating position-dependent code addressing. the linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together 💀-mbig-endian,-mlittle-endian— generate code for the specified endianness. the default is little-endian 🍓
when as is configured for a TILE-Gx processor:
-m32|-m64— select the word size, either 32 bits or 64 bits 🔢-EB|-EL— select the endianness, either big-endian (-EB) or little-endian (-EL) 🌈
when as is configured for a Visium processor, there's this one:
-mtune=arch— specifies the target architecture. if an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message 🚨
the following names are recognized: "mcm24" "mcm" "gr5" "gr6" 👑
and when as is configured for an Xtensa processor, we got a whole lil collection, bestie:
--text-section-literals|--no-text-section-literals— control the treatment of literal pools. the default is--no-text-section-literals, which places literals in separate sections in the output file. this allows the literal pool to be placed in a data RAM/ROM. with--text-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. this may be necessary for large assembly files, where the literals would otherwise be out of range of the"L32R"instructions in the text section. literals are grouped into pools following.literal_positiondirectives or preceding"ENTRY"instructions. these options only affect literals referenced via PC-relative"L32R"instructions; literals for absolute mode"L32R"instructions are handled separately 💅--auto-litpools|--no-auto-litpools— control the treatment of literal pools. the default is--no-auto-litpools, which in the absence of--text-section-literalsplaces literals in separate sections in the output file. this allows the literal pool to be placed in a data RAM/ROM. with--auto-litpools, the literals are interspersed in the text section in order to keep them as close as possible to their references, and explicit.literal_positiondirectives are not required. this may be necessary for very large functions, where a single literal pool at the beginning of the function may not be reachable by"L32R"instructions at the end. these options only affect literals referenced via PC-relative"L32R"instructions; literals for absolute mode"L32R"instructions are handled separately. and when used together with--text-section-literals,--auto-litpoolstakes precedence 👑✨--absolute-literals|--no-absolute-literals— indicate to the assembler whether"L32R"instructions use absolute or PC-relative addressing. if the processor includes the absolute addressing option, the default is to use absolute"L32R"relocations. otherwise, only the PC-relative"L32R"relocations can be used 🦋--target-align|--no-target-align— enable or disable automatic alignment to reduce branch penalties at some expense in code size. this optimization is enabled by default. note that the assembler will always align instructions like"LOOP"that have fixed alignment requirements 💖--longcalls|--no-longcalls— enable or disable transformation of call instructions to allow calls across a greater range of addresses. this option should be used when call targets can potentially be out of range. it may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. the default is--no-longcalls🔥--transform|--no-transform— enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. the default is--transform;--no-transformshould only be used in the rare cases when the instructions must be exactly as specified in the assembly source. using--no-transformcauses out of range instruction operands to be errors 🚨--rename-section oldname=newname— rename the oldname section to newname. this option can be used multiple times to rename multiple sections 🎀--trampolines,--no-trampolines— turns on/off the transformation of jump instructions so jumps can reach a way bigger range of addresses 💫 You want this when jump targets could potentially be out of range. And if there are no such jumps? Then it changes nothing — not code size, not performance, zero. Default is--trampolines.--abi-windowed,--abi-call0— picks which ABI tag gets written into the.xtensa.infosection 🏷️ That tag is basically a little name-badge telling everyone what ABI the assembly code is. If you try to link object files with inconsistent ABI tags, the linker WILL issue a warning, bestie, it's giving conflict. The default ABI is chosen by the Xtensa core configuration.
The following options are available when as is configured for an Z80 processor. (yes, the Z80 is still out here living its best life, iconic 💅)
🎮 Z80 Dependent Features 🎮
(the original literally writes this as @chapter Z80 Dependent Features — we're just giving it the main-character heading it deserves ✨)
Command-line Options
-march=CPU[-EXT...][+EXT...]— this one specifies the target processor, no cap 🎯 If you try to assemble an instruction that won't execute on that target processor, the assembler will throw an error message at you. The processor names it recognizes are:z80,z180,ez80,gbz80,z80n,r800.
On top of the basic instruction set, you can tell the assembler to accept certain extension mnemonics. For example, -march=z180+sli+infc extends z180 with SLI instructions and IN F,(C). The extensions currently supported are:
full— all known instructionsadl— ADL CPU mode by default, eZ80 onlysli— the instruction known as SLI, SLL or SL1xyhl— instructions with halves of index registers:IXL,IXH,IYL,IYHxdcb— instructions likeRotOp (II+d),RandBitOp n,(II+d),Rinfc— the instructionIN F,(C)orIN (C)outc0— the instructionOUT (C),0
Heads up though — instead of extending a basic instruction set, extension mnemonics that start with-revoke that functionality. So-march=z80-full+xyhlfirst removes all default extensions and then adds support for index register halves only. Subtractive slay, honestly 😌
If this option is not specified, then -march=z80+xyhl+infc is assumed.
-local-prefix=prefix — marks every label with the specified prefix as local 🫶 But! Such a label can still be marked global explicitly in the code. This option does **not change the default local label prefix.L, it just adds a new one on top. Bestie energy: not replacing, just joining.-colonless— accepts colonless labels. Every symbol at the beginning of a line gets treated as a label. No:required, we're free now 🦋-sdcc— accepts assembler code produced by SDCC.- *
-fp-s=FORMAT* — single precision floating point numbers format. Default:ieee754(32 bit). - *
-fp-d=FORMAT* — double precision floating point numbers format. Default:ieee754(64 bit).
👀 SEE ALSO 👀
gcc(1), ld(1), and the Info entries for binutils and ld.
📜 COPYRIGHT 📜
Copyright (c) 1991-2025 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".
and that's a wrap on the whole page, bestie 🎀 This one's from binutils-2.45.50, dated 2026-01-13, and it lives at AS(1). Go forth and assemble something iconic 👑💖
📦 where this page comes from
- ubuntu resolute: binutils-m68hc1x 1:2.45.50.20251209+3.5.3build1 · GPL-3.0-or-later
- ubuntu stonking: binutils-m68hc1x 1:2.45.50.20251209+3.5.3build1 · GPL-3.0-or-later
- 💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms