AS(1)

👑 AS(1) — GNU Development Tools

okay so bestie, buckle up 💖 this is AS(1), from GNU Development Tools, and she is the portable GNU assembler. like, the whole family tree of architectures shows up to her party. we're doing this in chunks because there's genuinely So Much, so stay with me 🫶

---

🌸 NAME

as — the portable GNU assembler. that's it, that's the vibe. periodt.

---

✨ SYNOPSIS

here's the whole incantation, literally character for character, no cap:

as [-a[cdghilns][=file]]
 [--alternate]
 [--compress-debug-sections] [--nocompress-debug-sections]
 [-D]
 [--dump-config]
 [--debug-prefix-map old=new]
 [--defsym sym=val]
 [--elf-stt-common=[no|yes]]
 [--emulation=name]
 [-f]
 [-g] [--gstabs] [--gstabs+]
 [--gdwarf-<N>] [--gdwarf-sections]
 [--gdwarf-cie-version=VERSION]
 [--generate-missing-build-notes=[no|yes]]
 [--gsframe] [--gsframe=[no|yes]]
 [--gsframe-3]
 [--hash-size=N]
 [--help] [--target-help]
 [--info] [--no-info]
 [-I dir]
 [-J]
 [-K]
 [--keep-locals]
 [-L]
 [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM]
 [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM]
 [--multibyte-handling=[allow|warn|warn-sym-only]]
 [--no-pad-sections]
 [-o objfile] [-R]
 [--reloc-section-sym=[all|internal|none]]
 [--scfi=experimental]
 [--sectname-subst]
 [--size-check=[error|warning]]
 [--statistics]
 [-v] [--verbose]
 [-version] [--version]
 [-W] [--no-warn] [--warn] [--fatal-warnings]
 [-w] [-x]
 [-Z] [@FILE]
 [target-options]
 [--|files ...]

don't panic at the wall of brackets, we'll get to all of it 💅

---

🦋 TARGET

okay so this is the part where as flexes. every architecture below has its own little menu of target options. i'm listing them all, exactly as they are, because we do not gatekeep here 💖

💠 Target AArch64 options

[-EB|-EL]
[-mabi=ABI]

💠 Target Alpha options

[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]

💠 Target ARC options

[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]

💠 Target ARM options

[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
 -mapcs-reentrant]
[-mthumb-interwork] [-k]

💠 Target Blackfin options

[-mcpu=processor[-sirevision]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]

💠 Target BPF options

[-EL] [-EB]

💠 Target CRIS options

[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
[--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]

💠 Target C-SKY options

[-march=arch] [-mcpu=cpu]
[-EL] [-mlittle-endian] [-EB] [-mbig-endian]
[-fpic] [-pic]
[-mljump] [-mno-ljump]
[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
[-mnolrw ] [-mno-lrw]
[-melrw] [-mno-elrw]
[-mlaf ] [-mliterals-after-func]
[-mno-laf] [-mno-literals-after-func]
[-mlabr] [-mliterals-after-br]
[-mno-labr] [-mnoliterals-after-br]
[-mistack] [-mno-istack]
[-mhard-float] [-mmp] [-mcp] [-mcache]
[-msecurity] [-mtrust]
[-mdsp] [-medsp] [-mvdsp]

(those stray spaces inside [-no-jsri2bsr ], [-mnolrw ] and [-mlaf ] are canon, bestie, i don't make the rules 🌸)

💠 Target D10V options

[-O]

💠 Target D30V options

[-O|-n|-N]

💠 Target EPIPHANY options

[-mepiphany|-mepiphany16]

💠 Target H8/300 options

[-h-tick-hex]

💠 Target i386 options

[--32|--x32|--64] [-n]
[-march=CPU[+EXTENSION...]] [-mtune=CPU]

💠 Target IA-64 options

[-mconstant-gp|-mauto-pic]
[-milp32|-milp64|-mlp64|-mp64]
[-mle|mbe]
[-mtune=itanium1|-mtune=itanium2]
[-munwind-check=warning|-munwind-check=error]
[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
[-x|-xexplicit] [-xauto] [-xdebug]

💠 Target IP2K options

[-mip2022|-mip2022ext]

💠 Target M32C options

[-m32c|-m16c] [-relax] [-h-tick-hex]

💠 Target M32R options

[--m32rx|--[no-]warn-explicit-parallel-conflicts|
--W[n]p]

💠 Target M680X0 options

[-l] [-m68000|-m68010|-m68020|...]

the ... is doing a lot of heavy lifting there and honestly? iconic 😌

💠 Target M68HC11 options

[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branches] [--short-branches]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]

💠 Target MCORE options

[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]

💠 Target Meta options

[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu]

💠 Target MICROBLAZE options

[-mlittle-endian] [-mbig-endian]

💠 Target MIPS options

this one is long, bestie, hydrate before reading:

[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot [-mvxworks-pic]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-mfp64] [-mgp64] [-mfpxx]
[-modd-spreg] [-mno-odd-spreg]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
[-mips64r3] [-mips64r5] [-mips64r6]
[-construct-floats] [-no-construct-floats]
[-mignore-branch-isa] [-mno-ignore-branch-isa]
[-mnan=encoding]
[-trap] [-no-break] [-break] [-no-trap]
[-mips16] [-no-mips16]
[-mmips16e2] [-mno-mips16e2]
[-mmicromips] [-mno-micromips]
[-msmartmips] [-mno-smartmips]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdsp] [-mno-dsp]
[-mdspr2] [-mno-dspr2]
[-mdspr3] [-mno-dspr3]
[-mmsa] [-mno-msa]
[-mxpa] [-mno-xpa]
[-mmt] [-mno-mt]
[-mmcu] [-mno-mcu]
[-mcrc] [-mno-crc]
[-mginv] [-mno-ginv]
[-mloongson-mmi] [-mno-loongson-mmi]
[-mloongson-cam] [-mno-loongson-cam]
[-mloongson-ext] [-mno-loongson-ext]
[-mloongson-ext2] [-mno-loongson-ext2]
[-minsn32] [-mno-insn32]
[-mfix7000] [-mno-fix7000]
[-mfix-rm7000] [-mno-fix-rm7000]
[-mfix-vr4120] [-mno-fix-vr4120]
[-mfix-vr4130] [-mno-fix-vr4130]
[-mfix-r5900] [-mno-fix-r5900]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]

okay she ate that 💅

💠 Target MMIX options

[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]

💠 Target NDS32 options

 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
 [-misa=isa] [-mabi=abi] [-mall-ext]
 [-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
 [-mb2bb]

💠 Target PDP11 options

[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]

💠 Target picoJava options

[-mb|-me]

💠 Target PowerPC options

[-a32|-a64]
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
[-many] [-maltivec|-mvsx|-mhtm|-mvle]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
[-nops=count]

💠 Target PRU options

[-link-relax]
[-mnolink-relax]
[-mno-warn-regname-label]

💠 Target RISC-V options

[-fpic|-fPIC|-fno-pic]
[-march=ISA|Profiles|Profiles_ISA]
[-mabi=ABI]
[-mlittle-endian|-mbig-endian]

💠 Target RL78 options

[-mg10]
[-m32bit-doubles|-m64bit-doubles]

💠 Target RX options

[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]

💠 Target s390 options

[-m31|-m64] [-mesa|-mzarch] [-march=CPU]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]
[-mwarn-regtype-mismatch=strict
 -mwarn-regtype-mismatch=relaxed
 -mwarn-regtype-mismatch=no
 -mno-warn-regtype-mismatch]

💠 Target SCORE options

[-EB][-EL][-FIXDD][-NWARN]
[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
[-march=score7][-march=score3]
[-USE_R1][-KPIC][-O0][-G num][-V]

💠 Target SPARC options

copying this one exactly, brackets and all, because it's a lot of brackets 🫶:

[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
 -Asparcvisr|-Asparc5]
[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
 -bump]
[-32|-64]
[--enforce-aligned-data][--dcti-couples-detect]

💠 Target TIC54X options

[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]

💠 Target TIC6X options

[-march=arch] [-mbig-endian|-mlittle-endian]
[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
[-mpic|-mno-pic]

💠 Target TILE-Gx options

[-m32|-m64][-EB][-EL]

💠 Target Visium options

[-mtune=arch]

💠 Target Xtensa options

[--[no-]text-section-literals] [--[no-]auto-litpools]
[--[no-]absolute-literals]
[--[no-]target-align] [--[no-]longcalls]
[--[no-]transform]
[--rename-section oldname=newname]
[--[no-]trampolines]
[--abi-windowed|--abi-call0]

💠 Target Z80 options

[-march=CPU[-EXT][+EXT]]
[-local-prefix=PREFIX]
[-colonless]
[-sdcc]
[-fp-s=FORMAT]
[-fp-d=FORMAT]

---

and that's just the target menu, bestie 😭 we haven't even gotten to the actual DESCRIPTION yet. stay tuned, there's more incoming 💀✨

💖 DESCRIPTION 💖

okay so here's the tea, bestie: GNU as isn't just one assembler, it's literally a whole family of assemblers, like a friend group that all shares the same aesthetic. 🫶 If you've used (or ever used) the GNU assembler on one architecture, you'll walk into another architecture and it'll feel super similar. Each version has a ton in common with the others — object file formats, most assembler directives (which everyone calls pseudo-ops, iykyk), and assembler syntax. it's giving consistency, honestly. ✨

as is primarily intended to assemble the output of the GNU C compiler gcc so the linker ld can do its thing with it. that's the main character purpose. but ngl, we've tried to make as correctly assemble everything that other assemblers for the same machine would assemble — any exceptions are documented explicitly, so no surprises. that does not mean as always uses the same syntax as another assembler for the same architecture, though. for example, we know of several incompatible versions of 680x0 assembly language syntax. 💀 it's a whole thing.

Every time you run as, it assembles exactly one source program. periodt. that source program is made up of one or more files — and yes, the standard input counts as a file too. 🎀

You give as a command line that has zero or more input file names. the input files get read from left file name to right. a command-line argument (in any position) that has no special meaning is taken to be an input file name. simple as that.

If you give as no file names at all, it attempts to read one input file from the as standard input, which is normally your terminal. you may have to type ctl-D to tell as there is no more program to assemble. 🦋 (yes, ctl-D. the vibe check that says "we're done here".)

Use -- if you need to explicitly name the standard input file in your command line. 🫡

If the source is empty, as produces a small, empty object file. iconic minimalism, honestly. 💅

as may write warnings and error messages to the standard error file (usually your terminal). this should not happen when a compiler runs as automatically. warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly. so warnings = "girl, I made it work but heads up 🌸", errors = "bestie, this is not happening 😭".

If you are invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. the assembler arguments must be separated from each other (and from -Wa) by commas. for example:

gcc -c -g -O -Wa,-alh,-L file.c

This passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain internal symbols in the symbol table). two-for-one, we love a combo deal ✨

Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.) very "show me the receipts" of it all 💜

---

✨ OPTIONS ✨

• @file — read command-line options from file. the options read get inserted right in place of the original @file option, like a little swap. if file does not exist, or can't be read, then the option gets treated literally and is not removed. 🫶 Options in file are separated by whitespace. a whitespace character may be included in an option by surrounding the entire option in either single or double quotes. any character (including a backslash) may be included by prefixing the character to be included with a backslash. and the file may itself contain additional @file options — any such options will be processed recursively. it's giving inception, and we're obsessed. 🌀
• -a[cdghilmns] — turn on listings, in any of a variety of ways. pick your fighter:
  • -ac — omit false conditionals
  • -ad — omit debugging directives
  • -ag — include general information, like as version and options passed
  • -ah — include high-level source
  • -al — include assembly
  • -ali — include assembly with ginsn
  • -am — include macro expansions
  • -an — omit forms processing
  • -as — include symbols
  • =file — set the name of the listing file

You may combine these options; for example, use -aln for assembly listing without forms processing. the =file option, if used, must be the last one. and by itself, -a defaults to -ahls. 🎀

• --alternate — begin in alternate macro mode.
• --compress-debug-sections — compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. heads up: the resulting object file may not be compatible with older linkers and object file utilities. ⚠️ note that if compression would make a given section larger, then it is not compressed.
• --compress-debug-sections=none
• --compress-debug-sections=zlib
• --compress-debug-sections=zlib-gnu
• --compress-debug-sections=zlib-gabi
• --compress-debug-sections=zstd — these options control how DWARF debug sections get compressed. here's the breakdown, bestie:
  • --compress-debug-sections=none is equivalent to --nocompress-debug-sections.
  • --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to --compress-debug-sections.
  • --compress-debug-sections=zlib-gnu compresses DWARF debug sections using the obsoleted zlib-gnu format. the debug sections are renamed to begin with .zdebug.
  • --compress-debug-sections=zstd compresses DWARF debug sections using zstd.

note — if compression would actually make a section larger, then it is not compressed nor renamed. 🦋

• --nocompress-debug-sections — do not compress DWARF debug sections. this is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.
• -D — enable debugging in target specific backends, if supported. otherwise ignored. and even if ignored, this option is accepted for script compatibility with calls to other assemblers. it's just here being polite. 🙈
• --debug-prefix-map old=new — when assembling files in directory old, record debugging information describing them as in new instead. a little glow-up for your debug paths ✨
• --defsym sym=value — define the symbol sym to be value before assembling the input file. value must be an integer constant. as in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. the value of the symbol can be overridden inside a source file via the use of a .set pseudo-op. 🫶
• --dump-config — displays how the assembler is configured and then exits. a little "here's my whole personality" moment 💅
• --elf-stt-common=no
• --elf-stt-common=yes — these options control whether the ELF assembler should generate common symbols with the STT_COMMON type. the default can be controlled by a configure option --enable-elf-stt-common.
• --emit-local-absolute — emit even pre-defined (local) absolute symbols to the outgoing symbol table. note that this isn't the exact opposite of --strip-local-absolute. don't let anyone tell you otherwise. 💀
• --emulation=name — if the assembler is configured to support multiple different target configurations, then this option can be used to select the desired form.
• -f — "fast" — skip whitespace and comment preprocessing (assume source is compiler output). speedy girl behaviour ⚡
• -g
• --gen-debug — generate debugging information for each assembler source line using whichever debug format is preferred by the target. this currently means either STABS, ECOFF or DWARF2. when the debug format is DWARF then a .debug_info and .debug_line section is only emitted when the assembly file doesn't generate one itself. ✨
• --gstabs — generate stabs debugging information for each assembler line. this may help debugging assembler code, if the debugger can handle it.
• --gstabs+ — generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. 😭 this may help debugging assembler code. currently the only GNU extension is the location of the current working directory at assembling time.
• --gdwarf-2 — generate DWARF2 debugging information for each assembler line. this may help debugging assembler code, if the debugger can handle it. note — this option is only supported by some targets, not all of them. ⚠️
• --gdwarf-3 — this option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. note — enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis. 🙈
• --gdwarf-4 — this option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. note — enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis.
• --gdwarf-5 — this option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. note — enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis.
• --gdwarf-sections — instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. for example, a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. if the code section is just called .text then the debug line section will still be called just .debug_line without any suffix. one section per vibe 🎀
• --gdwarf-cie-version=version — control which version of DWARF Common Information Entries (CIEs) are produced. when this flag is not specified the default is version 1, though some targets can modify this default. other possible values for version are 3 or 4.
• --generate-missing-build-notes=yes
• --generate-missing-build-notes=no — these options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. the default can be controlled by the --enable-generate-build-notes configure option.
• --gsframe
• --gsframe
• --gsframe=no
• --gsframe=yes — create .sframe section from CFI directives. the explicit --gsframe=yes option behaves the same as --gsframe. generation can be suppressed with --gsframe=no. the default can be controlled by a configure option --enable-default-sframe. the current version of the emitted SFrame stack trace data is SFRAME_VERSION_3. 🔥
• --gsframe-3 — generate SFrame stack trace information as per Version 3 of the specification.
• --hash-size N — ignored. supported for command line compatibility with other assemblers. it's literally just standing there, being supportive 🫶
• --help — print a summary of the command-line options and exit. the "wait, what were my options again?" button, we've all been there 💜
• --target-help — prints a summary of all target specific options and then exits. That’s it, bestie. 👋
• --info — tells as not to suppress informational messages.
• --no-info — suppresses informational messages.
• -I dir — adds dir to the search list for .include directives.
• -J — don’t warn about signed overflow.
• -K — issue warnings when difference tables are altered for long displacements.
• -L, --keep-locals — keeps internal symbols in the symbol table. These symbols start with system-specific local label prefixes, typically .L for ELF systems or L for traditional a.out systems. 💅
• --listing-lhs-width=number — sets the maximum width, in words, of the output data column for an assembler listing to number.
• --listing-lhs-width2=number — sets the maximum width, in words, of the output data column for continuation lines in an assembler listing to number.
• --listing-rhs-width=number — sets the maximum width of an input source line, as displayed in a listing, to number bytes.
• --listing-cont-lines=number — sets the maximum number of lines printed in a listing for a single line of input to number + 1.
• --multibyte-handling=allow, --multibyte-handling=warn, --multibyte-handling=warn-sym-only, --multibyte-handling=warn_sym_only — controls how the assembler handles multibyte characters in the input. The default (which can be restored by using the allow argument) is to allow such characters without complaint. Using the warn argument makes the assembler generate a warning message whenever any multibyte character is encountered. Using the warn-sym-only argument only causes a warning when a symbol is defined with a name that contains multibyte characters. (References to undefined symbols will not generate a warning.)
• --no-pad-sections — stops the assembler from padding the ends of output sections to the alignment of that section. The default is to pad the sections, but this can waste space which might be needed on targets which have tight memory constraints.
• -o objfile — names the object-file output from as objfile.
• -R — folds the data section into the text section.
• --reduce-memory-overheads — ignored. Supported for compatibility with tools that pass the same option to both the assembler and the linker.
• --reloc-section-sym=all, --reloc-section-sym=internal, --reloc-section-sym=none — controls whether relocations referencing local binding symbols are adjusted to use section symbols instead. With "all" (the default), relocations against all eligible local binding symbols are converted. With "internal", only relocations against internal labels (symbols matching the ".L" prefix) are converted. With "none", no such conversions are performed.
• --scfi=experimental — controls whether the assembler should synthesize CFI for hand-written input. If the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning. Note that --scfi=experimental is not intended to be used for compiler-generated code, including inline assembly. This experimental support is work in progress. Only System V AMD64 ABI is supported. 😭

Each input function in assembly must begin with the .type directive, and should ideally be closed off using a .size directive. When using SCFI, each .type directive prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry). This implies that with each .type directive, a previous block of instructions, if any, is finalised as a distinct FDE.

• --sectname-subst — honors substitution sequences in section names.
• --size-check=error, --size-check=warning — issue an error or warning for an invalid ELF .size directive.
• --statistics — prints the maximum space (in bytes) and total time (in seconds) used by assembly.
• --strip-local-absolute — removes local absolute symbols from the outgoing symbol table.
• -v, --verbose — prints the as version.
• --version, -version — prints the as version and exits.
• -W, --no-warn — suppresses warning messages.
• --warn — doesn’t suppress warning messages or treat them as errors.
• --fatal-warnings — treats warnings as errors. 💀
• -w — ignored.
• -x — ignored.
• -Z — generates an object file even after errors.
• -- | files ... — standard input, or source files to assemble.

---

✨ Okay, next up: when as is configured for the 64-bit mode of the ARM Architecture (AArch64), these are the options you get:

• -EB — this option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.
• -EL — this option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.
• -mabi=abi — specifies which ABI the source code uses. The recognized arguments are "ilp32" and "lp64", which decide the generated object file in ELF32 and ELF64 format respectively. The default is "lp64".
• -mcpu=processor[+extension...] — specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized:

"cortex-a34", "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57",
"cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73", "cortex-a75",
"cortex-a76", "cortex-a76ae", "cortex-a77", "cortex-a78", "cortex-a78ae",
"cortex-a78c", "cortex-a510", "cortex-a520", "cortex-a710", "cortex-a720",
"ares", "exynos-m1", "falkor", "neoverse-n1", "neoverse-n2", "neoverse-e1",
"neoverse-v1", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1"
"xgene2", "cortex-r82", "cortex-x1", "cortex-x2", "cortex-x3", and "cortex-x4"

The special name "all" may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions.

In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.

If some implementations of a particular processor can have an extension, then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions.

• -march=architecture[+extension...] — specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized:

"armv8-a", "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a",
"armv8.6-a", "armv8.7-a", "armv8.8-a", "armv8.9-a", "armv8-r", "armv9-a",
"armv9.1-a", "armv9.2-a", "armv9.3-a", "armv9.4-a" and "armv9.5-a"

If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assembler will default to -mcpu=all.

The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu, extensions are not always enabled by default.

• -mbig-obj — on PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections.
• -mverbose-error — this option enables verbose error messages for AArch64 gas. This option is enabled by default.
• -mno-verbose-error — this option disables verbose error messages in AArch64 gas.
• -menable-sysreg-checking — this option enables error messages that are issued if an attempt is made to assemble a system register access which will not execute on the target architecture.

---

🌸 And if as is configured for an Alpha processor, here’s the little lineup:

• -mcpu — this option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the .arch directive.

The following processor names are recognized:

21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264,
"21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56",
"ev6", "ev67", "ev68"

The special name "all" may be used to allow the assembler to accept instructions valid for any Alpha processor.

In order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. "ev4") do not.

• -mdebug, -no-mdebug — enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. The default is to automatically enable .mdebug when the first stabs directive is seen.
• -relax — this option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications.
• -replace, -noreplace — enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets and -replace is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual.
• -g — this option is used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect.
• -Gsize — a local common symbol larger than size is placed in .bss, while smaller symbols are placed in .sbss.
• -F, -32addr — these options are ignored for backward compatibility.

---

🫶 Finally, when as is configured for an ARC processor, you get:

• -mcpu=cpu — this option selects the core processor variant.
• -EB | -EL — select either big-endian (-EB) or little-endian (-EL) output.
• -mcode-density — enable Code Density extension instructions.

🦋 when as is built for ARM

okay so if your as is configured for the ARM processor family, here's your whole menu, bestie:

• -mcpu=processor[+extension...] — tells it which ARM processor variant you're targeting 🎯
• -march=architecture[+extension...] — tells it which ARM architecture variant the target is using
• -mfpu=floating-point-format — picks which Floating Point architecture is the target 💅
• -mfloat-abi=abi — picks which floating point ABI is in use
• -mthumb — turns on Thumb only instruction decoding
• -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant — pick which procedure calling convention is in use
• -EB | -EL — big-endian (-EB) or little-endian (-EL) output, choose your fighter ✨
• -mthumb-interwork — says the code was generated with interworking between Thumb and ARM code in mind
• -mccs — flips on CodeComposer Studio assembly syntax compatibility mode
• -k — says that PIC code has been generated

---

🖤 when as is built for Blackfin

• -mcpu=processor[-sirevision] — specifies the target processor. The optional sirevision is not used in the assembler — it's literally just here so GCC can easily pass down its -mcpu= option. The assembler will throw an error message if you try to assemble an instruction that won't execute on the target processor 😤

The recognized processor names are: bf504, bf506, bf512, bf514, bf516, bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf535 (not implemented yet 🙈), bf536, bf537, bf538, bf539, bf542, bf542m, bf544, bf544m, bf547, bf547m, bf548, bf548m, bf549, bf549m, bf561, and bf592.

• -mfdpic — assemble for the FDPIC ABI
• -mno-fdpic, -mnopic — disable -mfdpic

---

🔥 when as is built for the Linux kernel BPF family

ngl the original literally has a stray @chapter BPF Dependent Features line chilling in the middle of it 😭 keeping it here because we do not drop details in this house

BPF Options

• -EB — the assembler should emit big-endian eBPF
• -EL — the assembler should emit little-endian eBPF
• -mdialect=dialect — specifies the assembly language dialect to recognize while assembling. The assembler supports normal and pseudoc.
• -misa-spec=spec — specifies the version of the BPF instruction set to use when assembling. The supported BPF ISA versions are v1 v2, v3 and v4.

You can also pass the value xbpf to recognize extra instructions that GCC uses for testing purposes — but beware, this is not valid BPF 💀

• -mno-relax — tells the assembler to not relax instructions

heads up: if no endianness option is specified on the command line, the host endianness is used. And the CRIS-specific options are documented in the info pages, iykyk.

---

🌸 when as is built for the C-SKY processor family

• -march=archname — assemble for architecture archname. The --help option lists valid values for archname ✨
• -mcpu=cpuname — assemble for architecture cpuname. The --help option lists valid values for cpuname
• -EL, -mlittle-endian — generate little-endian output
• -EB, -mbig-endian — generate big-endian output
• -fpic, -pic — generate position-independent code
• -mljump, -mno-ljump — enable/disable transformation of the short branch instructions jbf, jbt, and jbr to jmpi. This one is for V2 processors only. It's ignored on CK801 and CK802 targets, which do not support the jmpi instruction, and it's enabled by default for other processors.
• -mbranch-stub, -mno-branch-stub — pass through R_CKCORE_PCREL_IMM26BY2 relocations for bsr instructions to the linker.

This option is only available for bare-metal C-SKY V2 ELF targets, where it's enabled by default. It cannot be used in code that will be dynamically linked against shared libraries 🚫

• -force2bsr, -mforce2bsr, -no-force2bsr, -mno-force2bsr — enable/disable transformation of jbsr instructions to bsr. This option is always enabled (and -mno-force2bsr is ignored) for CK801/CK802 targets. It's also always enabled when -mbranch-stub is in effect.
• -jsri2bsr, -mjsri2bsr, -no-jsri2bsr, -mno-jsri2bsr — enable/disable transformation of jsri instructions to bsr. This option is enabled by default.
• -mnolrw, -mno-lrw — enable/disable transformation of lrw instructions into a movih/ori pair
• -melrw, -mno-elrw — enable/disable extended lrw instructions. This option is enabled by default for CK800-series processors.
• -mlaf, -mliterals-after-func, -mno-laf, -mno-literals-after-func — enable/disable placement of literal pools after each function
• -mlabr, -mliterals-after-br, -mno-labr, -mnoliterals-after-br — enable/disable placement of literal pools after unconditional branches. This option is enabled by default.
• -mistack, -mno-istack — enable/disable interrupt stack instructions. This option is enabled by default on CK801, CK802, and CK802 processors.

---

ooh and here are the options that explicitly enable certain optional instructions. These features are also enabled implicitly by using -mcpu= to specify a processor that supports it 👑

• -mhard-float — enable hard float instructions
• -mmp — enable multiprocessor instructions
• -mcp — enable coprocessor instructions
• -mcache — enable cache prefetch instruction
• -msecurity — enable C-SKY security instructions
• -mtrust — enable C-SKY trust instructions
• -mdsp — enable DSP instructions
• -medsp — enable enhanced DSP instructions
• -mvdsp — enable vector DSP instructions

---

🧚 when as is built for an Epiphany processor

• -mepiphany — specifies that both 32 and 16 bit instructions are allowed. This is the default behavior 💖
• -mepiphany16 — restricts the permitted instructions to just the 16 bit set

---

🎀 when as is built for an H8/300 processor

another stray @chapter H8/300 Dependent Features snuck in here in the original 😭 we love a messy queen

Options

The Renesas H8/300 version of as has one machine-dependent option (the original says "one" but then lists two, and honestly? iconic. both are below 👇):

• -h-tick-hex — support H'00 style hex constants in addition to 0x00 style
• -mach=name — sets the H8300 machine variant. The recognized machine names are: h8300h, h8300hn, h8300s, h8300sn, h8300sx and h8300sxn.

---

💜 when as is built for an i386 processor

• --32 | --x32 | --64 — select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.

These options are only available with the ELF object file format, and they require that the necessary BFD support has been included — on a 32-bit platform you have to add --enable-64-bit-bfd to configure to enable 64-bit usage and use x86-64 as target platform 🫶

• -n — by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.
• --divide — on SVR4-derived platforms, the character / is treated as a comment character, which means it cannot be used in expressions. The --divide option turns / into a normal character. This does not disable / at the beginning of a line starting a comment, and doesn't affect using # for starting a comment.
• -march=CPU[+EXTENSION...] — specifies the target processor. The assembler will issue an error message if you attempt to assemble an instruction which will not execute on the target processor 😤

The recognized processor names are: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, znver5, znver6, btver1, btver2, generic32 and generic64.

So, still on -march — in addition to the basic instruction set, the assembler can be told to accept a whole buffet of extension mnemonics. Like, -march=i686+sse4+vmx extends i686 with sse4 and vmx, slay. The extensions it currently supports are: 8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, avx512_bmm, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb, avx10.1, avx10.1/512, avx10.1/256, avx10.1/128, user_msr, msr_imm, apx_f, apx_nci, apx_ndd, apx_nf, apx_nci_ndd_nf, avx10.2, avx10.2/512, avx10.2/256, avx10.2/128, movrs, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8 amx_movrs, amx_avx512, amx_tile, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, snp, invlpgb, tlbsync, rmpquery, rmpread, svme, gmism2, gmiccs, padlockrng2, padlockphe2, padlockxmodx and padlock. 😮‍💨 no cap, that's the whole roster.

Bestie, note that these extension mnemonics can be prefixed with no to revoke the respective (and any dependent) functionality. Like, un-inviting them from the party. Also note — and this is lowkey important — the suffixes permitted on -march=avx10.<N> enforce a vector length restriction, i.e. despite these otherwise being "enabling" options, using these suffixes will disable all insns with wider vector or mask register operands. So it's giving "yes but actually no" 💅.

And when the .arch directive is used with -march, the .arch directive will take precedent. .arch said what it said. 👑

• -mtune=CPU — picks a processor to optimize for. When it's used together with the -march option, only instructions of the processor specified by the -march option will be generated. Valid CPU values are identical to the processor list of -march=CPU. Same menu, different vibe check.
• -moperand-check=none, -moperand-check=warning, -moperand-check=error — these control if the assembler should check certain instruction operands or operand combinations. Example of the kind of thing it's looking at: instructions where operand size cannot be inferred from its operands and also hasn't been specified by way of an instruction suffix. -moperand-check=none makes the assembler not perform these checks at all (living dangerously 🙈). -moperand-check=warning makes it issue a warning when respective checks fail, which is the default. -moperand-check=error makes it issue an error when respective checks fail, so it's a full stop, not a lil nudge.
• -msse2avx — tells the assembler it should encode SSE instructions with VEX prefix, requiring AVX to be available. And SSE instructions using extended GPRs will be encoded with EVEX prefix, requiring AVX512 or AVX10 to be available. Glow-up for your SSE, but only if the CPU's got the receipts.
• -muse-unaligned-vector-move — says the assembler should encode aligned vector move as unaligned vector move. Chaotic, honestly, but it's your call.
• -msse-check=none, -msse-check=warning, -msse-check=error — control if the assembler should check SSE instructions. -msse-check=none makes it not check SSE instructions, which is the default. -msse-check=warning makes it issue a warning for any SSE instruction. -msse-check=error makes it issue an error for any SSE instruction. Pick your level of surveillance, bestie 🫶.
• -mavxscalar=128, -mavxscalar=256 — control how the assembler should encode scalar AVX instructions. -mavxscalar=128 encodes scalar AVX instructions with 128bit vector length, which is the default. -mavxscalar=256 encodes them with 256bit vector length.

WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. Like, fr fr, don't. 😭

• -mvexwig=0, -mvexwig=1 — control how the assembler should encode VEX.W-ignored (WIG) VEX instructions. -mvexwig=0 encodes WIG VEX instructions with vex.w = 0, which is the default. -mvexwig=1 encodes WIG EVEX instructions with vex.w = 1. Yes, the original text says EVEX in that second sentence — not me, I just work here 💀.

WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. Same warning, same energy, still not a joke.

• -mevexlig=128, -mevexlig=256, -mevexlig=512 — control how the assembler should encode length-ignored (LIG) EVEX instructions. -mevexlig=128 encodes LIG EVEX instructions with 128bit vector length, which is the default. -mevexlig=256 and -mevexlig=512 encode LIG EVEX instructions with 256bit and 512bit vector length, respectively. Bigger vector, bigger main character energy.
• -mevexwig=0, -mevexwig=1 — control how the assembler should encode w-ignored (WIG) EVEX instructions. -mevexwig=0 encodes WIG EVEX instructions with evex.w = 0, which is the default. -mevexwig=1 encodes WIG EVEX instructions with evex.w = 1.
• -mmnemonic=att, -mmnemonic=intel — specifies instruction mnemonic for matching instructions. The .att_mnemonic and .intel_mnemonic directives will take precedent. (Directives stay winning, sorry.)
• -msyntax=att, -msyntax=intel — specifies instruction syntax when processing instructions. The .att_syntax and .intel_syntax directives will take precedent.
• -mnaked-reg — specifies that registers don't require a % prefix. The .att_syntax and .intel_syntax directives will take precedent. Naked registers, scandalous 🍓.
• -madd-bnd-prefix — forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in the source code. It's giving "I added it for you, you're welcome."
• -mno-shared — okay so on ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The -mshared option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions. Tiny bloat, big shareability trade-off ✨.
• -mbig-obj — on PE/COFF target this forces the use of big object file format, which allows more than 32768 sections. 32768 sections was not enough, apparently. Iconic.
• -momit-lock-prefix=no, -momit-lock-prefix=yes — control how the assembler should encode lock prefix. This option is intended as a workaround for processors that fail on lock prefix. This option can only be safely used with single-core, single-thread computers — -momit-lock-prefix=yes will omit all lock prefixes. -momit-lock-prefix=no will encode lock prefix as usual, which is the default.

Seriously, "can only be safely used with single-core, single-thread computers" — read it again, bestie. Not a group-chat-safe flex. 😭

• -mfence-as-lock-add=no, -mfence-as-lock-add=yes — control how the assembler should encode lfence, mfence and sfence. -mfence-as-lock-add=yes will encode lfence, mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will encode lfence, mfence and sfence as usual, which is the default.
• -mrelax-relocations=no, -mrelax-relocations=yes — control whether the assembler should generate relax relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX, in 64-bit mode. -mrelax-relocations=yes will generate relax relocations. -mrelax-relocations=no will not generate relax relocations. Relax, it's just relocations 🧘‍♀️.
• -mtls-check=no, -mtls-check=yes — control whether the assembler checks tls relocation. -mtls-check=yes will check tls relocation. -mtls-check=no will not check tls relocation. The default can be controlled by a configure option --enable-x86-tls-check.
• -malign-branch-boundary=NUM — controls how the assembler should align branches with segment prefixes or NOP. NUM must be a power of 2. It should be 0 or no less than 16. Branches will be aligned within NUM byte boundary. -malign-branch-boundary=0, which is the default, doesn't align branches.
• -malign-branch=TYPE[+TYPE...] — specifies types of branches to align. TYPE is a combination of jcc, which aligns conditional jumps, fused, which aligns fused conditional jumps, jmp, which aligns unconditional jumps, call which aligns calls, ret, which aligns rets, indirect, which aligns indirect jumps and calls. The default is -malign-branch=jcc+fused+jmp.
• -malign-branch-prefix-size=NUM — specifies the maximum number of prefixes on an instruction to align branches. NUM should be between 0 and 5. The default NUM is 5.
• -mbranches-within-32B-boundaries — aligns conditional jumps, fused conditional jumps and unconditional jumps within 32 byte boundary with up to 5 segment prefixes on an instruction. It is equivalent to -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5. The default doesn't align branches. One flag, three flags' worth of work — efficiency queen 👑.
• -mlfence-after-load=no, -mlfence-after-load=yes — control whether the assembler should generate lfence after load instructions. -mlfence-after-load=yes will generate lfence. -mlfence-after-load=no will not generate lfence, which is the default.
• -mlfence-before-indirect-branch=none / =all / =register / =memory — ok so these four control whether the assembler drops an lfence in front of indirect near branch instructions. Let's break it down, bestie:
  • =all generates lfence before an indirect near branch via register, and throws a warning before an indirect near branch via memory. It also implicitly sets -mlfence-before-ret=shl when there's no explicit -mlfence-before-ret= given. Two-for-one deal ✨
  • =register generates lfence before indirect near branch via register.
  • =memory just issues a warning before indirect near branch via memory.
  • =none generates no lfence and issues no warning — and that's the default, periodt.

Heads up: lfence won't be generated before an indirect near branch via register if you're using -mlfence-after-load=yes, because in that case lfence gets generated after loading the branch target register instead. No double-dipping 💅

• -mlfence-before-ret=none / =shl / =or / =yes / =not — same energy but for ret. =or generates an or instruction with lfence. =shl and =yes generate a shl instruction with lfence. =not generates a not instruction with lfence. =none generates no lfence at all, and that's the default. Pick your fighter 🎀
• -mx86-used-note=no / -mx86-used-note=yes — controls whether the assembler generates the GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes. The default? That's decided by the --enable-x86-used-note configure option, so it's a build-time vibe. 🦋
• -mevexrcig=rne / =rd / =ru / =rz — how should the assembler encode SAE-only EVEX instructions? =rne encodes the RC bits of the EVEX instruction with 00, and that's the default. =rd, =ru and =rz encode SAE-only EVEX instructions with 01, 10 and 11 RC bits respectively. Bit-twiddling slay 🔥
• -mamd64 / -mintel64 — tells the assembler to accept only AMD64 or Intel64 ISA in 64-bit mode. Default is to accept common, Intel64 only and AMD64 ISAs (so, everything, no gatekeeping). 👑
• -O0 | -O | -O1 | -O2 | -Os — optimize instruction encoding so the instruction size gets smaller. Here's the tea:
  • -O and -O1 encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with 32-bit register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions, encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions, and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical.
  • -O2 includes the -O1 optimization plus it encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions. In 64-bit mode, VEX encoded instructions with commutative source operands will also have their source operands swapped if that lets it use the 2-byte VEX prefix form instead of the 3-byte one. Certain forms of AND as well as OR with the same (register) operand specified twice also get changed to TEST. Glow-up central ✨
  • -Os includes the -O2 optimization plus it encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate.
  • -O0 turns this optimization off. Chill mode 😌

---

💜 if as is configured for the Ubicom IP2K series

• -mip2022ext — says the extended IP2022 instructions are allowed. Go wild.
• -mip2022 — restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. Back to basics, no cap.

🌸 if as is configured for the Renesas M32C and M16C processors

• -m32c — assemble M32C instructions.
• -m16c — assemble M16C instructions (this is the default).
• -relax — enable support for link-time relaxations.
• -h-tick-hex — supports H'00 style hex constants in addition to 0x00 style. Both vibes welcome 🫶

🎀 if as is configured for the Renesas M32R (formerly Mitsubishi M32R) series

• --m32rx — specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.
• --warn-explicit-parallel-conflicts or --Wp — produce warning messages when questionable parallel constructs are encountered. Not me side-eyeing your parallel code 👀
• --no-warn-explicit-parallel-conflicts or --Wnp — do not produce warning messages when questionable parallel constructs are encountered.

🦋 if as is configured for the Motorola 68000 series

• -l — shorten references to undefined symbols, to one word instead of two.
• -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 — specify what processor in the 68000 family is the target. The default is normally the -m68020, but this can be changed at configuration time. Pick your era, bestie 💅
• -m68881 | -m68882 | -mno-68881 | -mno-68882 — the target machine does (or does not) have a floating-point coprocessor. Default is to assume a coprocessor for -m68020, -m68030, and -mcpu32. And yes — even though the basic 68000 is not compatible with the 68881, you can specify a combination of the two, since it's possible to emulate the coprocessor instructions with the main processor. Girl math that actually maths ✨
• -m68851 | -mno-68851 — the target machine does (or does not) have a memory-management unit coprocessor. Default is to assume an MMU for -m68020 and up.

For the deets about the PDP-11 machine dependent features options, go see PDP-11-Options. 💖

• -mpic | -mno-pic — generate position-independent (or position-dependent) code. The default is -mpic.
• -mall / -mall-extensions — enable all instruction set extensions. This is the default — maximalist queen 👑
• -mno-extensions — disable all instruction set extensions. Minimalist era.
• -mextension | -mno-extension — enable (or disable) a particular instruction set extension.
• -mcpu — enable the instruction set extensions supported by a particular CPU, and disable all other extensions.
• -mmachine — enable the instruction set extensions supported by a particular machine model, and disable all other extensions.

🧚 if as is configured for a picoJava processor

• -mb — generate "big endian" format output.
• -ml — generate "little endian" format output.

🍓 if as is configured for a PRU processor

• -mlink-relax — assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they're all zeros, then LD would shorten the LDI32 instruction to a single LDI. In that case, as will output DIFF relocations for diff expressions. Optimist energy 🫶
• -mno-link-relax — assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted. Pessimist energy 😭
• -mno-warn-regname-label — do not warn if a label name matches a register name. Usually assembler programmers will want this warning emitted. C compilers may want to turn this off.
• *-mcore-revision=revision* — this one specifies the PRU core revision to assemble for. These revisions are recognized: "V1", "V2", "V3" and "V4". The assembler defaults to "V3".

🌈 if as is configured for a MIPS processor

• -G num — sets the largest size of an object that can be referenced implicitly with the "gp" register. It's only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
• -EB — generate "big endian" format output.
• -EL — generate "little endian" format output.
• -mips1 / -mips2 / -mips3 / -mips4 / -mips5 / -mips32 / -mips32r2 / -mips32r3 / -mips32r5 / -mips32r6 / -mips64 / -mips64r2 / -mips64r3 / -mips64r5 / -mips64r6 — generate code for a particular MIPS Instruction Set Architecture level. The aliases, because there are so many, ok:
  • -mips1 is an alias for -march=r3000
  • -mips2 is an alias for -march=r6000
  • -mips3 is an alias for -march=r4000
  • -mips4 is an alias for -march=r8000
  • -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. Whew 😮‍💨
• -march= cpu — generate code for a particular MIPS CPU.
• -mtune= cpu — schedule and tune for a particular MIPS CPU.
• -mfix7000 / -mno-fix7000 — cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
• -mfix-rm7000 / -mno-fix-rm7000 — cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.
• -mfix-r5900 / -mno-fix-r5900 — do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer, and always schedule a "nop" instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. Hardware betrayal, truly 💀
• -mdebug / -no-mdebug — cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections.
• -mpdr / -mno-pdr — control generation of ".pdr" sections.
• -mgp32 / -mfp32 — register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers. Forcing it, iconic 💅
• -mgp64, -mfp64 — okay so register widths are normally inferred from the ISA and ABI, but these two flags force a certain group of registers to always be treated as 64 bits wide. -mgp64 controls the size of the general-purpose registers, and -mfp64 controls the size of the floating-point registers. Forced. Locked in. 💅
• -mfpxx — same deal, register sizes usually come from the ISA and ABI, but using this flag combined with -mabi=32 enables an ABI variant that operates correctly with floating-point registers that are 32 or 64 bits wide. Flexible queen behavior ✨
• -modd-spreg, -mno-odd-spreg — enables use of floating-point operations on odd-numbered single-precision registers when the ISA supports it. Heads up: -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg. 🎀
• -mips16, -no-mips16 — generate code for the MIPS 16 processor. This is equivalent to putting .module mips16 at the start of the assembly file. -no-mips16 turns off this option.
• -mmips16e2, -mno-mips16e2 — enable the use of MIPS16e2 instructions in MIPS16 mode. Equivalent to putting .module mips16e2 at the start of the assembly file. -mno-mips16e2 turns off this option.
• -mmicromips, -mno-micromips — generate code for the microMIPS processor. Equivalent to putting .module micromips at the start of the assembly file. -mno-micromips turns off this option — and that one is equivalent to putting .module nomicromips at the start of the assembly file. 🦋
• -msmartmips, -mno-smartmips — enables the SmartMIPS extension to the MIPS32 instruction set. Equivalent to putting .module smartmips at the start of the assembly file. -mno-smartmips turns off this option.
• -mips3d, -no-mips3d — generate code for the MIPS-3D Application Specific Extension. Tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option.
• -mdmx, -no-mdmx — generate code for the MDMX Application Specific Extension. Tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.
• -mdsp, -mno-dsp — generate code for the DSP Release 1 Application Specific Extension. Tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option.
• -mdspr2, -mno-dspr2 — generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. Tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option.
• -mdspr3, -mno-dspr3 — generate code for the DSP Release 3 Application Specific Extension. Implies -mdsp and -mdspr2. Tells the assembler to accept DSP Release 3 instructions. -mno-dspr3 turns off this option. Look at her stacking implications, we love a generous icon 👑
• -mmsa, -mno-msa — generate code for the MIPS SIMD Architecture Extension. Tells the assembler to accept MSA instructions. -mno-msa turns off this option.
• -mxpa, -mno-xpa — generate code for the MIPS eXtended Physical Address (XPA) Extension. Tells the assembler to accept XPA instructions. -mno-xpa turns off this option.
• -mmt, -mno-mt — generate code for the MT Application Specific Extension. Tells the assembler to accept MT instructions. -mno-mt turns off this option.
• -mmcu, -mno-mcu — generate code for the MCU Application Specific Extension. Tells the assembler to accept MCU instructions. -mno-mcu turns off this option.
• -mcrc, -mno-crc — generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. Tells the assembler to accept CRC instructions. -mno-crc turns off this option.
• -mginv, -mno-ginv — generate code for the Global INValidate (GINV) Application Specific Extension. Tells the assembler to accept GINV instructions. -mno-ginv turns off this option.
• -mloongson-mmi, -mno-loongson-mmi — generate code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. Tells the assembler to accept MMI instructions. -mno-loongson-mmi turns off this option.
• -mloongson-cam, -mno-loongson-cam — generate code for the Loongson Content Address Memory (CAM) instructions. Tells the assembler to accept Loongson CAM instructions. -mno-loongson-cam turns off this option.
• -mloongson-ext, -mno-loongson-ext — generate code for the Loongson EXTensions (EXT) instructions. Tells the assembler to accept Loongson EXT instructions. -mno-loongson-ext turns off this option.
• -mloongson-ext2, -mno-loongson-ext2 — generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies -mloongson-ext. Tells the assembler to accept Loongson EXT2 instructions. -mno-loongson-ext2 turns off this option.
• -minsn32, -mno-insn32 — only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions. Equivalent to putting .set insn32 at the start of the assembly file. -mno-insn32 turns off this option — equivalent to putting .set noinsn32 at the start of the assembly file. By default -mno-insn32 is selected, allowing all instructions to be used. 🫶
• --construct-floats, --no-construct-floats — the --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default --construct-floats is selected, allowing construction of these floating point constants.
• --relax-branch, --no-relax-branch — --relax-branch enables the relaxation of out-of-range branches. By default --no-relax-branch is selected, which means any out-of-range branches produce an error. 😭
• -mignore-branch-isa, -mno-ignore-branch-isa — ignore branch checks for invalid transitions between ISA modes. The semantics of branches doesn't provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. So GAS has checks built in that verify the two ISA modes match during branch assembly. -mignore-branch-isa disables those checks. By default -mno-ignore-branch-isa is selected, causing any invalid branch that requires a transition between ISA modes to produce an error.
• -mnan=encoding — pick between the IEEE 754-2008 NaN encoding format (-mnan=2008) or the legacy one (-mnan=legacy). The latter is the default. 💜
• --emulation=name — ok this one has lore. It was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. It's retained for backwards compatibility only. 🕰️

The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferred options instead.

• -nocpp — as ignores this option. It's accepted for compatibility with the native tools. she's just being polite bestie 🙈
• --trap, --no-trap, --break, --no-break — control how to deal with multiplication overflow and division by zero. --trap or --no-break (synonyms) take a trap exception — and those only work for Instruction Set Architecture level 2 and higher. --break or --no-trap (also synonyms, and the default) take a break exception. ⚠️
• -n — when this option is used, as will issue a warning every time it generates a nop instruction from a macro. Not me getting a warning every time 💀

---

The following options are available when as is configured for a LoongArch processor. 🌸

• -fpic, -fPIC — generate position-independent code.
• -fno-pic — don't generate position-independent code (default).

The following options are available when as is configured for a Meta processor.

• -mcpu=metac11 — generate code for Meta 1.1.
• -mcpu=metac12 — generate code for Meta 1.2.
• -mcpu=metac21 — generate code for Meta 2.1.
• -mfpu=metac21 — allow code to use FPU hardware of Meta 2.1.

See the info pages for documentation of the MMIX-specific options. 👀

The following options are available when as is configured for a NDS32 processor.

• -O1 — optimize for performance.
• -Os — optimize for space.
• -EL — produce little endian data output.
• -EB — produce little endian data output. (yes, that's literally what the page says, no I'm not fixing it 🙈)
• -mpic — generate PIC.
• -mno-fp-as-gp-relax — suppress fp-as-gp relaxation for this file.
• -mb2bb-relax — back-to-back branch optimization.
• -mno-all-relax — suppress all relaxation for this file.
• -march=<arch name> — assemble for architecture <arch name>, which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.
• -mbaseline=<baseline> — assemble for baseline <baseline>, which could be v2, v3, v3m.
• -mfpu-freg=FREG — specify a FPU configuration:
  • 0 — 8 SP / 4 DP registers
  • 1 — 16 SP / 8 DP registers
  • 2 — 32 SP / 16 DP registers
  • 3 — 32 SP / 32 DP registers
• -mabi=abi — specify an abi version, <abi> could be v1, v2, v2fp, v2fpp.
• -m[no-]mac — enable/disable Multiply instructions support.
• -m[no-]div — enable/disable Divide instructions support.
• -m[no-]16bit-ext — enable/disable 16-bit extension.
• -m[no-]dx-regs — enable/disable d0/d1 registers.
• -m[no-]perf-ext — enable/disable Performance extension.
• -m[no-]perf2-ext — enable/disable Performance extension 2.
• -m[no-]string-ext — enable/disable String extension.
• -m[no-]reduced-regs — enable/disable Reduced Register configuration (GPR16) option.
• -m[no-]audio-isa-ext — enable/disable AUDIO ISA extension.
• -m[no-]fpu-sp-ext — enable/disable FPU SP extension.
• -m[no-]fpu-dp-ext — enable/disable FPU DP extension.
• -m[no-]fpu-fma — enable/disable FPU fused-multiply-add instructions.
• -mall-ext — turn on all extensions and instructions support. the everything bagel of flags 🥯✨

The following options are available when as is configured for a PowerPC processor.

• -a32 — generate ELF32 or XCOFF32.
• -a64 — generate ELF64 or XCOFF64.
• -K PIC — drops EF_PPC_RELOCATABLE_LIB into the ELF flags. ✨
• -mpwrx, -mpwr2 — code for POWER/2 (RIOS2). 💅
• -mpwr — code for POWER (RIOS1). (note the missing period, that's the original's vibe, not mine, iykyk)
• -m601 — code for PowerPC 601.
• -mppc, -mppc32, -m603, -m604 — code for PowerPC 603/604.
• -m403, -m405 — code for PowerPC 403/405.
• -m440 — code for PowerPC 440. BookE and some 405 instructions, bestie. 🦋
• -m464 — code for PowerPC 464.
• -m476 — code for PowerPC 476.
• -m7400, -m7410, -m7450, -m7455 — code for PowerPC 7400/7410/7450/7455.
• -m750cl, -mgekko, -mbroadway — code for PowerPC 750CL/Gekko/Broadway. (GameCube girlies rise 🎮)
• -m821, -m850, -m860 — code for PowerPC 821/850/860.
• -mppc64, -m620 — code for PowerPC 620/625/630.
• -me200z2, -me200z4 — code for e200 variants: e200z2 with LSP, e200z4 with SPE.
• -me300 — code for the PowerPC e300 family.
• -me500, -me500x2 — code for the Motorola e500 core complex.
• -me500mc — code for the Freescale e500mc core complex.
• -me500mc64 — code for the Freescale e500mc64 core complex.
• -me5500 — code for the Freescale e5500 core complex.
• -me6500 — code for the Freescale e6500 core complex.
• -mlsp — turns on LSP instructions. (Heads up: this disables SPE and SPE2 — you can't have it all, babe. 💀)
• -mspe — code for Motorola SPE instructions. (Also disables LSP. pick a lane 💅)
• -mspe2 — code for Freescale SPE2 instructions. (Disables LSP too, same deal.)
• -mtitan — code for the AppliedMicro Titan core complex.
• -mppc64bridge — code for PowerPC 64, including bridge insns. 🌉
• -mbooke — code for 32-bit BookE.
• -ma2 — code for the A2 architecture.
• -maltivec — code for processors with AltiVec instructions.
• -mvle — code for Freescale PowerPC VLE instructions.
• -mvsx — code for processors with Vector-Scalar (VSX) instructions.
• -mhtm — code for processors with Hardware Transactional Memory instructions.
• -mpower4, -mpwr4 — code for the Power4 architecture.
• -mpower5, -mpwr5, -mpwr5x — code for the Power5 architecture.
• -mpower6, -mpwr6 — code for the Power6 architecture.
• -mpower7, -mpwr7 — code for the Power7 architecture.
• -mpower8, -mpwr8 — code for the Power8 architecture.
• -mpower9, -mpwr9 — code for the Power9 architecture.
• -mpower10, -mpwr10 — code for the Power10 architecture.
• -mpower11, -mpwr11 — code for the Power11 architecture. (yes we're at 11, we been knew 👑)
• -mfuture — code for the 'future' architecture. main character energy only ✨
• -mcell, -mcell — code for the Cell Broadband Engine architecture. (And yeah, the original literally lists it twice — iconic of it, we keep it. 🫶)
• -mcom — code for Power/PowerPC common instructions.
• -many — code for any architecture (PWR/PWRX/PPC). "any" as in genuinely any fr.
• -mregnames — allow symbolic names for registers.
• -mno-regnames — do not allow symbolic names for registers. (the hater option 🙈)
• -mrelocatable — support for GCC's -mrelocatable option.
• -mrelocatable-lib — support for GCC's -mrelocatable-lib option.
• -memb — sets the PPC_EMB bit in ELF flags.
• -mlittle, -mlittle-endian, -le — code for a little endian machine.
• -mbig, -mbig-endian, -be — code for a big endian machine.
• -nops=count — okay so if an alignment directive wants to insert more than count nops, this puts a branch at the beginning so the CPU just skips executing all those nops. Efficiency slay. 🔥

---

The following options are available when as is configured for a RISC-V processor. 🌸

• -fpic, -fPIC — generate position-independent code.
• -fno-pic — don't generate position-independent code. This one's the default, ngl.
• -march=ISA|Profiles|Profiles_ISA — selects the base isa, as specified by ISA or Profiles or Profies_ISA. (That last spelling is straight from the original — not me, don't come for me 💀) For example -march=rv32ima -march=RVI20U64 -march=RVI20U64_d. And if this option and the architecture attributes aren't set, then the assembler will check the default configure setting --with-arch=ISA.
• -misa-spec=ISAspec — selects the default isa spec version. If the version of ISA isn't set by -march, then the assembler helps to set the version according to the default chosen spec. If this option isn't set, then the assembler will check the default configure setting --with-isa-spec=ISAspec.
• -mpriv-spec=PRIVspec — selects the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren't set, then the assembler will check the default configure setting --with-priv-spec=PRIVspec.
• -mabi=ABI — selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or "e" to indicate the soft-float calling convention ("e" indicates a soft-float RVE ABI). A lot of letters, but they all mean something, bestie. ✨
• -mrelax — takes advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. This is the default 🫶
• -mno-relax — don't do linker relaxations.
• -march-attr — generates the default contents for the riscv elf attribute section if the .attribute directives are not set. This section is used to record the info that a linker or runtime loader needs to check compatibility. That info includes the ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of the privileged specification. very "receipts" of it all 💅
• -mno-arch-attr — don't generate the default riscv elf attribute section if the .attribute directives are not set.
• -mcsr-check — enables CSR checking for the ISA-dependent CRS and the read-only CSR. (Yes, CRS — original's spelling, keeping it.) The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR cannot be written by the CSR instructions. Not me policing your writes 😭
• -mno-csr-check — don't do CSR checking.
• -mlittle-endian — code for a little endian machine.
• -mbig-endian — code for a big endian machine.

---

See the info pages for documentation of the RX-specific options. (Not here, bestie — different page, go look 👀)

---

The following options are available when as is configured for the s390 processor family. 💜

• -m31, -m64 — selects the word size, either 31/32 bits or 64 bits.
• -mesa, -mzarch — selects the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).
• -march=processor — specify which s390 processor variant is the target: g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or z17 (or arch15). That's the whole roster, no skips. 🌈
• -mregnames, -mno-regnames — allow or disallow symbolic names for registers. Pick your fighter.
• -mwarn-areg-zero — warns whenever the operand for a base or index register has been specified but evaluates to zero. Like, hello? you gave me nothing? 😭
• -mwarn-regtype-mismatch=strict, -mwarn-regtype-mismatch=relaxed, -mwarn-regtype-mismatch=no, -mno-warn-regtype-mismatch — controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type. The default (which can be restored by using the relaxed argument) is to perform relaxed register name type checks, which allow floating point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating point register (FPR) operands. This is acceptable as the FPR are embedded into the lower half of the VR. Using the strict argument, strict register name type checks are performed. The no argument, which is equivalent to -mno-warn-regtype-mismatch, disables any register name type checks entirely. 💀

Okay real talk: relaxed = chill default, strict = no mixing FPR and VR names, no = zero checks. Don't get it twisted, those are the three moods.

---

The following options are available when as is configured for a TMS320C6000 processor. 🎀

• -march=arch — enable (only) instructions from architecture arch. By default, all instructions are permitted.

The following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x". ✨

• -mdsbt, -mno-dsbt — the -mdsbt option causes the assembler to generate the "Tag_ABI_DSBT" attribute with a value of 1, indicating that the code is using DSBT addressing. The -mno-dsbt option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. So like… don't mix them, or the linker will absolutely call you out. 🔥
• -mpid=no, -mpid=near, -mpid=far — the -mpid= option causes the assembler to generate the "Tag_ABI_PID" attribute with a value indicating the form of data addressing used by the code. -mpid=no, the default, indicates position-dependent data addressing; -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing; and -mpid=far indicates position-independent addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together. 👀
• -mpic, -mno-pic — the -mpic option causes the assembler to generate the "Tag_ABI_PIC" attribute with a value of 1, indicating that the code is using position-independent code addressing. (Yes, there's a stray double space in the original sentence, she's got quirks. 🫶) The "-mno-pic" option, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together.
• -mbig-endian, -mlittle-endian — generate code for the specified endianness. The default is little-endian. 🦋

---

The following options are available when as is configured for a TILE-Gx processor. ⭐

• -m32 | -m64 — selects the word size, either 32 bits or 64 bits.
• -EB | -EL — selects the endianness, either big-endian (-EB) or little-endian (-EL). B for big, L for little, see how easy that is 💅

---

The following option is available when as is configured for a Visium processor. 🌸

• -mtune=arch — this option specifies the target architecture. If an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. No quietly-wrong code here, she'll tell you. 😭

The following names are recognized: "mcm24" "mcm" "gr5" "gr6"

---

The following options are available when as is configured for an Xtensa processor. 🧚

• --text-section-literals | --no-text-section-literals — Okay so this one controls literal pools, bestie. The default is --no-text-section-literals, which puts literals in separate sections in the output file. That means the literal pool can live in a data RAM/ROM. With --text-section-literals, literals get interspersed in the text section so they stay as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the L32R instructions in the text section. Literals are grouped into pools following .literal_position directives or preceding ENTRY instructions. These options only affect literals referenced via PC-relative L32R instructions; literals for absolute mode L32R instructions are handled separately. ✨
• --auto-litpools | --no-auto-litpools — Same literal-pool situation, different flavor 💅. The default is --no-auto-litpools, which — in the absence of --text-section-literals — places literals in separate sections in the output file. That lets the literal pool go in a data RAM/ROM. With --auto-litpools, literals are interspersed in the text section to keep them as close as possible to their references, and explicit .literal_position directives are not required. This may be necessary for very large functions, where a single literal pool at the beginning of the function may not be reachable by L32R instructions at the end. These options only affect literals referenced via PC-relative L32R instructions; literals for absolute mode L32R instructions are handled separately. When used together with --text-section-literals, --auto-litpools takes precedence. 👑
• --absolute-literals | --no-absolute-literals — Tells the assembler whether L32R instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute L32R relocations. Otherwise, only PC-relative L32R relocations can be used. 🎀
• --target-align | --no-target-align — Enable or disable automatic alignment to reduce branch penalties at some expense in code size. This optimization is enabled by default. Note that the assembler will always align instructions like LOOP that have fixed alignment requirements. 🦋
• --longcalls | --no-longcalls — Enable or disable transformation of call instructions to allow calls across a greater range of addresses. This option should be used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. The default is --no-longcalls. 😭
• --transform | --no-transform — Enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The default is --transform; --no-transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source. Using --no-transform causes out of range instruction operands to be errors. 💀
• --rename-section oldname=newname — Rename the oldname section to newname. This option can be used multiple times to rename multiple sections. 🎀
• --trampolines | --no-trampolines — Enable or disable transformation of jump instructions to allow jumps across a greater range of addresses. This option should be used when jump targets can potentially be out of range. In the absence of such jumps this option does not affect code size or performance. The default is --trampolines. 🌈
• --abi-windowed | --abi-call0 — Choose the ABI tag written to the .xtensa.info section. The ABI tag indicates the ABI of the assembly code. A warning is issued by the linker on an attempt to link object files with inconsistent ABI tags. Default ABI is chosen by the Xtensa core configuration. 💖

The following options are available when as is configured for an Z80 processor.

@chapter Z80 Dependent Features

💅 Command-line Options 💅

• -march=CPU[-EXT...][+EXT...] — This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: z80, z180, ez80, gbz80, z80n, r800. In addition to the basic instruction set, the assembler can be told to accept some extension mnemonics. For example, -march=z180+sli+infc extends z180 with SLI instructions and IN F,(C). The following extensions are currently supported: full (all known instructions), adl (ADL CPU mode by default, eZ80 only), sli (instruction known as SLI, SLL or SL1), xyhl (instructions with halves of index registers: IXL, IXH, IYL, IYH), xdcb (instructions like RotOp (II+d),R and BitOp n,(II+d),R), infc (instruction IN F,(C) or IN (C)), outc0 (instruction OUT (C),0). Note that rather than extending a basic instruction set, the extension mnemonics starting with - revoke the respective functionality: -march=z80-full+xyhl first removes all default extensions and adds support for index registers halves only. If this option is not specified then -march=z80+xyhl+infc is assumed. 🔥
• -local-prefix=prefix — Mark all labels with the specified prefix as local. But such a label can be marked global explicitly in the code. This option doesn’t change the default local label prefix .L; it just adds a new one. 🌸
• -colonless — Accept colonless labels. All symbols at line begin are treated as labels. ✨
• -sdcc — Accept assembler code produced by SDCC. 🫶
• -fp-s=FORMAT — Single precision floating point numbers format. Default: ieee754 (32 bit). 🎀
• -fp-d=FORMAT — Double precision floating point numbers format. Default: ieee754 (64 bit). 🎀

🔭 SEE ALSO 🔭

gcc(1), ld(1), and the Info entries for binutils and ld. 💜

📜 COPYRIGHT 📜

Copyright (c) 1991-2026 Free Software Foundation, Inc.

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".

---

Okay that’s the whole page, bestie — AS(1) from binutils-2.47, dated 2026-08-26, signing off 💖🦋✨