LLVM-RTDYLD(1)
💖 NAME 💖
bestie, this is llvm-rtdyld — the manual page for llvm-rtdyld 12. It's giving LLVM-RTDYLD(1) energy, and it lives in User Commands, naturally. 💅
🌈 DESCRIPTION 🌈
okay so first up, the vibe:
OVERVIEW: llvm MC-JIT tool
USAGE: llvm-rtdyld [options] <input files> --args <program arguments>...and then we get into the options, which are a whole menu. buckle up, bestie. 🎀
🎀 OPTIONS 🎀
💅 Color Options 💅
--color— Use colors in output (default=autodetect) 🌈
✨ General options ✨
--aarch64-neon-syntax=<value>— Choose style of NEON code to emit from AArch64 backend:=generic— Emit generic NEON assembly=apple— Emit Apple-style NEON assembly
--abort-on-max-devirt-iterations-reached— Abort when the max iterations for devirtualization CGSCC repeat pass is reached 💀--amdgpu-bypass-slow-div— Skip 64-bit divide for dynamic 32-bit values--amdgpu-disable-loop-alignment— Do not align and prefetch loops--amdgpu-disable-power-sched— Disable scheduling to minimize mAI power bursts--amdgpu-dpp-combine— Enable DPP combiner--amdgpu-dump-hsa-metadata— Dump AMDGPU HSA Metadata--amdgpu-enable-flat-scratch— Use flat scratch instructions--amdgpu-enable-merge-m0— Merge and hoist M0 initializations--amdgpu-promote-alloca-to-vector-limit=<uint>— Maximum byte size to consider promote alloca to vector--amdgpu-reserve-vgpr-for-sgpr-spill— Allocates one VGPR for future SGPR Spill--amdgpu-sdwa-peephole— Enable SDWA peepholer--amdgpu-use-aa-in-codegen— Enable the use of AA during codegen.--amdgpu-verify-hsa-metadata— Verify AMDGPU HSA Metadata--amdgpu-vgpr-index-mode— Use GPR indexing mode instead of movrel for vector indexing--args <string>...—<program arguments>...— literally the program arguments, bestie. 🫶--arm-add-build-attributes— (no description in the original — a mystery, but iconic) 🙈--arm-implicit-it=<value>— Allow conditional instructions outdside of an IT block=always— Accept in both ISAs, emit implicit ITs in Thumb=never— Warn in ARM, reject in Thumb=arm— Accept in ARM, reject in Thumb=thumb— Warn in ARM, emit implicit ITs in Thumb
--atomic-counter-update-promoted— Do counter update using atomic fetch add for promoted counters only--atomic-first-counter— Use atomic fetch add for first counter in a function (usually the entry counter)--bounds-checking-single-trap— Use one trap block per function--cfg-hide-deoptimize-paths— (no description in the original — spooky) 💀--cfg-hide-unreachable-paths— (no description in the original — also spooky) 👻--check=<string>— File containing RuntimeDyld verifier checks.--cost-kind=<value>— Target cost kind=throughput— Reciprocal throughput=latency— Instruction latency=code-size— Code size=size-latency— Code size and latency
--cvp-dont-add-nowrap-flags— (no description in the original — mysterious) ✨--debugify-level=<value>— Kind of debug info to add=locations— Locations only=location+variables— Locations and Variables
--debugify-quiet— Suppress verbose debugify output--disable-promote-alloca-to-lds— Disable promote alloca to LDS--disable-promote-alloca-to-vector— Disable promote alloca to vector--do-counter-promotion— Do counter register promotion--dot-cfg-mssa=<file name for generated dot file>— file name for generated dot file--dylib=<string>— Add library.--emscripten-cxx-exceptions-allowed=<string>— The list of function names in which Emscripten-style exception handling is enabled (see emscripten EMSCRIPTEN_CATCHING_ALLOWED options)--enable-cse-in-irtranslator— Should enable CSE in irtranslator--enable-cse-in-legalizer— Should enable CSE in Legalizer--enable-emscripten-cxx-exceptions— WebAssembly Emscripten-style exception handling--enable-emscripten-sjlj— WebAssembly Emscripten-style setjmp/longjmp handling--enable-gvn-hoist— Enable the GVN hoisting pass (default = off)--enable-gvn-memdep— (no description in the original — it's giving mystery) 🙈--enable-gvn-sink— Enable the GVN sinking pass (default = off)--enable-load-in-loop-pre— (no description in the original) 🕵️♀️--enable-load-pre— (no description in the original) 🕵️♀️--enable-loop-simplifycfg-term-folding— (no description in the original) 🕵️♀️--enable-name-compression— Enable name/filename string compression--enable-split-backedge-in-load-pre— (no description in the original) 🕵️♀️--entry=<string>— Function to call as entry point.--gpsize=<uint>— Global Pointer Addressing Size. The default size is 8.--hash-based-counter-split— Rename counter variable of a comdat function based on cfg hash--hot-cold-split— Enable hot-cold splitting pass--import-all-index— Import all external functions in index.--instcombine-code-sinking— Enable code sinking--instcombine-guard-widening-window=<uint>— How wide an instruction window to bypass looking for another guard--instcombine-max-iterations=<uint>— Limit the maximum number of instruction combining iterations--instcombine-max-num-phis=<uint>— Maximum number phis to handle in intptr/ptrint folding--instcombine-maxarray-size=<uint>— Maximum array size considered when doing a combine--instcombine-negator-enabled— Should we attempt to sink negations?--instcombine-negator-max-depth=<uint>— What is the maximal lookup depth when trying to check for viability of negation sinking.--instcombine-unsafe-select-transform— Enable poison-unsafe select to and/or transform--instrprof-atomic-counter-update-all— Make all profile counter updates atomic (for testing only) 💀--internalize-public-api-file=<filename>— A file containing list of symbol names to preserve--internalize-public-api-list=<list>— A list of symbol names to preserve--iterative-counter-promotion— Allow counter promotion across the whole loop nest.--lto-embed-bitcode=<value>— Embed LLVM bitcode in object files produced by LTO=none— Do not embed=optimized— Embed after all optimization passes=post-merge-pre-opt— Embed post merge, but before optimizations
--lto-pass-remarks-filter=<regex>— Only record optimization remarks from passes whose names match the given regular expression--lto-pass-remarks-format=<format>— The format used for serializing remarks (default: YAML)--lto-pass-remarks-output=<filename>— Output filename for pass remarks--matrix-default-layout=<value>— Sets the default matrix layout=column-major— Use column-major layout=row-major— Use row-major layout
--max-counter-promotions=<int>— Max number of allowed counter promotions--max-counter-promotions-per-loop=<uint>— Max number counter promotions per loop to avoid increasing register pressure too much--mcpu=<cpu-name>— Target a specific cpu type (-mcpu=helpfor details)--merror-missing-parenthesis— Error for missing parenthesis around predicate registers--merror-noncontigious-register— Error for register names that aren't contigious--mhvx— Enable Hexagon Vector eXtensions--mhvx=<value>— Enable Hexagon Vector eXtensions=v60— Build for HVX v60=v62— Build for HVX v62=v65— Build for HVX v65=v66— Build for HVX v66=v67— Build for HVX v67
--mips-compact-branches=<value>— MIPS Specific: Compact branch policy.=never— Do not use compact branches if possible.=optimal— Use compact branches where appropriate (default).=always— Always use compact branches if possible.
--mips16-constant-islands— Enable mips16 constant islands.--mips16-hard-float— Enable mips16 hard float.--mir-strip-debugify-only— Should mir-strip-debug only strip debug info from debugified modules by default--mno-compound— Disable looking for compound instructions for Hexagon--mno-fixup— Disable fixing up resolved relocations for Hexagon--mno-ldc1-sdc1— Expand double precision loads and stores to their single precision counterparts--mno-pairing— Disable looking for duplex instructions for Hexagon--mwarn-missing-parenthesis— Warn for missing parenthesis around predicate registers--mwarn-noncontigious-register— Warn for register names that arent contigious--mwarn-sign-mismatch— Warn for mismatching a signed and unsigned value--no-discriminators— Disable generation of discriminator information.--nvptx-sched4reg— NVPTX Specific: schedule for register pressue (yes, that's how it's spelled, we don't make the rules 💅)--poison-checking-function-local— Check that returns are non-poison (for testing) — like a vibe check for your returns ✨--preallocate=<ulong>— Allocate memory upfront rather than on-demand — get it all out the way, no waiting bestie 💖--r600-ir-structurize— Use StructurizeCFG IR pass--rdf-dump— (no description, it's a mystery 🙈)--rdf-limit=<uint>— (no description, just vibes)--runtime-counter-relocation— Enable relocating counters at runtime.--safepoint-ir-verifier-print-only— (no description, iconic silence 💀)--sample-profile-check-record-coverage=<N>— Emit a warning if less than N% of records in the input profile are matched to the IR.--sample-profile-check-sample-coverage=<N>— Emit a warning if less than N% of samples in the input profile are matched to the IR.--sample-profile-max-propagate-iterations=<uint>— Maximum number of iterations to go through when propagating sample block/edge weights through the CFG.--show-times— Show times forllvm-rtdyldphases--skip-ret-exit-block— Suppress counter promotion if exit blocks containret.--speculative-counter-promotion-max-exiting=<uint>— The max number of exiting blocks of a loop to allow speculative counter promotion--speculative-counter-promotion-to-loop— When the option is false, if the target block is in a loop, the promotion will be disallowed unless the promoted counter update can be further/iteratively promoted into an acyclic region.--summary-file=<string>— The summary file to use for function importing.--tail-predication=<value>— MVE tail-predication pass options=disabled— Don't tail-predicate loops=enabled-no-reductions— Enable tail-predication, but not for reduction loops=enabled— Enable tail-predication, including reduction loops=force-enabled-no-reductions— Enable tail-predication, but not for reduction loops, and force this which might be unsafe=force-enabled— Enable tail-predication, including reduction loops, and force this which might be unsafe
--thinlto-assume-merged— Assume the input has already undergone ThinLTO function importing and the other pre-optimization pipeline changes.--threads=<int>— (no description, just a number bestie 🙈)--triple=<string>— Target triple for disassembler
🎬 Action to perform
--execute— Load, link, and execute the inputs.--printline— Load, link, and print line information for each function.--printdebugline— Load, link, and print line information for each function using the debug object--printobjline— Like-printlineinfobut does not load the object first--verify— Load, link and verify the resulting memory image.--verify-region-info— Verify region info (time consuming)
--vp-counters-per-site=<number>— The average number of profile counters allocated per value profiling site.--vp-static-alloc— Do static counter allocation for value profiler--x86-align-branch=<string>— Specify types of branches to align (plus separated list of types):jcc— indicates conditional jumpsfused— indicates fused conditional jumpsjmp— indicates direct unconditional jumpscall— indicates direct and indirect callsret— indicates retsindirect— indicates indirect unconditional jumps
--x86-align-branch-boundary=<uint>— Control how the assembler should align branches with NOP. If the boundary's size is not 0, it should be a power of 2 and no less than 32. Branches will be aligned to prevent from being across or against the boundary of specified size. The default value 0 does not align branches.--x86-branches-within-32B-boundaries— Align selected instructions to mitigate negative performance impact of Intel's micro code update for errata skx102. May break assumptions about labels corresponding to particular instructions, and should be used with caution.
⚠️ bestie this one is giving "handle with care" energy — it might break your label assumptions, so use with caution fr fr
--x86-pad-max-prefix-size=<uint>— Maximum number of prefixes to use for padding
✨ Generic Options ✨
--help— Display available options (--help-hiddenfor more)--help-list— Display list of available options (--help-list-hiddenfor more)--version— Display the version of this program
💖 Polly Options: Configure the polly loop optimizer 💖
--polly— Enable the polly optimizer (only at-O3)--polly-2nd-level-tiling— Enable a 2nd level loop of loop tiling--polly-ast-print-accesses— Print memory access functions--polly-context=<isl parameter set>— Provide additional constraints on the context parameters--polly-dce-precise-steps=<int>— The number of precise steps between two approximating iterations. (A value of -1 schedules another approximation stage before the actual dead code elimination.--polly-delicm-max-ops=<int>— Maximum number of isl operations to invest for lifetime analysis; 0=no limit--polly-detect-full-functions— Allow the detection of full functions--polly-dump-after— Dump module after Polly transformations into a file suffixed with "-after"--polly-dump-after-file=<string>— Dump module after Polly transformations to the given file--polly-dump-before— Dump module before Polly transformations into a file suffixed with "-before"--polly-dump-before-file=<string>— Dump module before Polly transformations to the given file--polly-enable-simplify— Simplify SCoP after optimizations--polly-ignore-func=<string>— Ignore functions that match a regex. Multiple regexes can be comma separated. Scop detection will ignore all functions that match ANY of the regexes provided.--polly-isl-arg=<argument>— Option passed to ISL--polly-on-isl-error-abort— Abort if an isl error is encountered--polly-only-func=<string>— Only run on functions that match a regex. Multiple regexes can be comma separated. Scop detection will run on all functions that match ANY of the regexes provided.--polly-only-region=<identifier>— Only run on certain regions (The provided identifier must appear in the name of the region's entry block--polly-only-scop-detection— Only run scop detection, but no other optimizations--polly-optimized-scops— Polly - Dump polyhedral description of Scops optimized with the isl scheduling optimizer and the set of post-scheduling transformations is applied on the schedule tree--polly-parallel— Generate thread parallel code (isl codegen only)--polly-parallel-force— Force generation of thread parallel code ignoring any cost model--polly-pattern-matching-based-opts— Perform optimizations based on pattern matching--polly-process-unprofitable— Process scops that are unlikely to benefit from Polly optimizations.--polly-register-tiling— Enable register tiling--polly-report— Print information about the activities of Polly--polly-show— Highlight the code regions that will be optimized in a (CFG BBs and LLVM-IR instructions)--polly-show-only— Highlight the code regions that will be optimized in a (CFG only BBs)--polly-stmt-granularity=<value>— Algorithm to use for splitting basic blocks into multiple statements=bb— One statement per basic block=scalar-indep— Scalar independence heuristic=store— Store-level granularity
--polly-target=<value>— The hardware to target=cpu— generate CPU code
--polly-tiling— Enable loop tiling--polly-vectorizer=<value>— Select the vectorization strategy=none— No Vectorization=polly— Polly internal vectorizer=stripmine— Strip-mine outer loops for the loop-vectorizer to trigger
And that's the whole vibe bestie! This page was served fresh from llvm-rtdyld 12, dated February 2022. Stay slaying, keep linking, and remember: when in doubt, read the manual 💅✨🦋
📦 where this page comes from
- ubuntu jammy: llvm-12 1:12.0.1-19ubuntu3 · APACHE-2-LLVM-EXCEPTIONS
- 💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms