LLVM-RTDYLD(1)
LLVM-RTDYLD(1) π manual page for llvm-rtdyld 11 π
NAME πΈ
llvm-rtdyld β manual page for llvm-rtdyld 11. That's the whole name section, bestie. π
DESCRIPTION π«
OVERVIEW: llvm MC-JIT tool β yeah, it's the LLVM MC-JIT tool, periodt.
USAGE: here's the exact vibe:
llvm-rtdyld [options] <input files> --args <program arguments>...
OPTIONS βοΈ
Color Options π¨
--colorβ use colors in output (default=autodetect). Yes, the default is autodetect, so it'll figure out the vibe check for your terminal. β¨
General options π§°
--aarch64-neon-syntax=<value>β choose the style of NEON code to emit from the AArch64 backend:=genericβ emit generic NEON assembly=appleβ emit Apple-style NEON assembly
--amdgpu-bypass-slow-divβ skip 64-bit divide for dynamic 32-bit values π--amdgpu-disable-loop-alignmentβ do not align and prefetch loops--amdgpu-disable-power-schedβ disable scheduling to minimizemAIpower bursts--amdgpu-dpp-combineβ enable DPP combiner--amdgpu-dump-hsa-metadataβ dump AMDGPU HSA Metadata--amdgpu-enable-global-sgpr-addrβ enable use of SGPR regs for GLOBAL LOAD/STORE instructions--amdgpu-enable-merge-m0β merge and hoist M0 initializations--amdgpu-promote-alloca-to-vector-limit=<uint>β maximum byte size to consider promote alloca to vector--amdgpu-reserve-vgpr-for-sgpr-spillβ allocates one VGPR for future SGPR Spill--amdgpu-sdwa-peepholeβ enable SDWA peepholer--amdgpu-verify-hsa-metadataβ verify AMDGPU HSA Metadata--amdgpu-vgpr-index-modeβ use GPR indexing mode instead of movrel for vector indexing--args <string>...β<program arguments>...β literally the program arguments, bestie.--arm-add-build-attributesβ the manpage gives this one no description at all, so we're leaving it blank. π--arm-implicit-it=<value>β allow conditional instructions outside of an IT block (the source says "outdside", but we know what it means π):=alwaysβ accept in both ISAs, emit implicit ITs in Thumb=neverβ warn in ARM, reject in Thumb=armβ accept in ARM, reject in Thumb=thumbβ warn in ARM, emit implicit ITs in Thumb
--atomic-counter-update-promotedβ do counter update using atomic fetch add for promoted counters only--atomic-first-counterβ use atomic fetch add for first counter in a function (usually the entry counter)--bounds-checking-single-trapβ use one trap block per function--cfg-hide-deoptimize-pathsβ no description in the source, just vibes π«Ά--cfg-hide-unreachable-pathsβ also no description, iconic blank era β¨--check=<string>β file containing RuntimeDyld verifier checks.--cost-kind=<value>β target cost kind:=throughputβ reciprocal throughput=latencyβ instruction latency=code-sizeβ code size
--cvp-dont-add-nowrap-flagsβ no description, blank as the day is long π--debugify-level=<value>β kind of debug info to add:=locationsβ locations only=location+variablesβ locations and Variables
--debugify-quietβ suppress verbose debugify output--disable-promote-alloca-to-ldsβ disable promote alloca to LDS--disable-promote-alloca-to-vectorβ disable promote alloca to vector--do-counter-promotionβ do counter register promotion--dylib=<string>β add library.--emscripten-cxx-exceptions-allowed=<string>β the list of function names in which Emscripten-style exception handling is enabled (see emscriptenEMSCRIPTEN_CATCHING_ALLOWEDoptions)--enable-cse-in-irtranslatorβ should enable CSE in irtranslator--enable-cse-in-legalizerβ should enable CSE in Legalizer--enable-emscripten-cxx-exceptionsβ WebAssembly Emscripten-style exception handling--enable-emscripten-sjljβ WebAssembly Emscripten-style setjmp/longjmp handling--enable-gvn-hoistβ enable the GVN hoisting pass (default = off)--enable-gvn-memdepβ no description, we move πββοΈ--enable-gvn-sinkβ enable the GVN sinking pass (default = off)--enable-load-in-loop-preβ blank description, but the option is here π--enable-load-preβ also blank, still valid β¨--enable-loop-simplifycfg-term-foldingβ no description, but it's real π¦--enable-name-compressionβ enable name/filename string compression--entry=<string>β function to call as entry point.--gpsize=<uint>β Global Pointer Addressing Size. The default size is8.--hash-based-counter-splitβ rename counter variable of a comdat function based on cfg hash--hot-cold-splitβ enable hot-cold splitting pass--import-all-indexβ import all external functions in index.--instcombine-code-sinkingβ enable code sinking--instcombine-guard-widening-window=<uint>β how wide an instruction window to bypass looking for another guard--instcombine-max-iterations=<uint>β limit the maximum number of instruction combining iterations--instcombine-max-num-phis=<uint>β maximum number phis to handle in intptr/ptrint folding--instcombine-maxarray-size=<uint>β maximum array size considered when doing a combine--instcombine-negator-enabledβ should we attempt to sink negations?--instcombine-negator-max-depth=<uint>β what is the maximal lookup depth when trying to check for viability of negation sinking.--instrprof-atomic-counter-update-allβ make all profile counter updates atomic (for testing only)--internalize-public-api-file=<filename>β a file containing list of symbol names to preserve--internalize-public-api-list=<list>β a list of symbol names to preserve--iterative-counter-promotionβ allow counter promotion across the whole loop nest.--lto-embed-bitcodeβ embed LLVM bitcode in object files produced by LTO--lto-pass-remarks-filter=<regex>β only record optimization remarks from passes whose names match the given regular expression--lto-pass-remarks-format=<format>β the format used for serializing remarks (default:YAML)--lto-pass-remarks-output=<filename>β output filename for pass remarks--matrix-default-layout=<value>β sets the default matrix layout:=column-majorβ use column-major layout=row-majorβ use row-major layout
--max-counter-promotions=<int>β max number of allowed counter promotions--max-counter-promotions-per-loop=<uint>β max number counter promotions per loop to avoid increasing register pressure too much--mcpu=<cpu-name>β target a specific cpu type (-mcpu=helpfor details)--memop-size-large=<uint>β set large value threshold in memory intrinsic size profiling. Value of0disables the large value profiling.--memop-size-range=<string>β set the range of size in memory intrinsic calls to be profiled precisely, in a format of<start_val>:<end_val>--merror-missing-parenthesisβ error for missing parenthesis around predicate registers--merror-noncontigious-registerβ error for register names that aren't contigious--mhvxβ enable Hexagon Vector eXtensions--mhvx=<value>β enable Hexagon Vector eXtensions:=v60β build for HVX v60=v62β build for HVX v62=v65β build for HVX v65=v66β build for HVX v66=v67β build for HVX v67
--mips-compact-branches=<value>β MIPS Specific: Compact branch policy.=neverβ do not use compact branches if possible.=optimalβ use compact branches where appropriate (default).=alwaysβ always use compact branches if possible.
--mips16-constant-islandsβ enable mips16 constant islands.--mips16-hard-floatβ enable mips16 hard float.--mir-strip-debugify-onlyβ shouldmir-strip-debugonly strip debug info from debugified modules by default--mno-compoundβ disable looking for compound instructions for Hexagon--mno-fixupβ disable fixing up resolved relocations for Hexagon--mno-ldc1-sdc1β expand double precision loads and stores to their single precision counterparts--mno-pairingβ disable looking for duplex instructions for Hexagon--mwarn-missing-parenthesisβ warn for missing parenthesis around predicate registers--mwarn-noncontigious-registerβ warn for register names that arent contigious--mwarn-sign-mismatchβ warn for mismatching a signed and unsigned value--no-discriminatorsβ disable generation of discriminator information.--nvptx-sched4regβ NVPTX Specific: schedule for register pressue--poison-checking-function-localβ check that returns are non-poison (for testing)--preallocate=<ulong>β allocate memory upfront rather than on-demand--r600-ir-structurizeβ bestie, this one says "Use StructurizeCFG IR pass" β¨--rdf-dumpβ ngl the source just has a dash here, no description, so it's giving mysterious icon energy π--rdf-limit=<uint>β also a dash in the source, so no extra tea, just the flag with a<uint>value π«Ά--runtime-counter-relocationβ Enable relocating counters at runtime. lowkey handy for moving counters around while things are running π--safepoint-ir-verifier-print-onlyβ another dash-only situation, the source gives no description, periodt π--sample-profile-check-record-coverage=<N>β Emit a warning if less than N% of records in the input profile are matched to the IR. so if your record coverage is slacking, it will literally warn you π--sample-profile-check-sample-coverage=<N>β Emit a warning if less than N% of samples in the input profile are matched to the IR. same vibe but for samples, not records π--sample-profile-max-propagate-iterations=<uint>β Maximum number of iterations to go through when propagating sample block/edge weights through the CFG. it caps how many times it loops through that propagation, no cap fr fr π--show-timesβ Show times for llvm-rtdyld phases. so you can see where the time went, iconic β±οΈ--speculative-counter-promotion-max-exiting=<uint>β The max number of exiting blocks of a loop to allow speculative counter promotion. basically a limit on exiting blocks for that promotion β¨--speculative-counter-promotion-to-loopβ When the option is false, if the target block is in a loop, the promotion will be disallowed unless the promoted counter update can be further/iteratively promoted into an acyclic region. so it's a whole conditional vibe, read it carefully bestie π--summary-file=<string>β The summary file to use for function importing. give it a string filename and it's the summary file for importing functions π«Ά--tail-predication=<value>β MVE tail-predication options. here are the values, each one matters:=disabledβ Don't tail-predicate loops=enabled-no-reductionsβ Enable tail-predication, but not for reduction loops=enabledβ Enable tail-predication, including reduction loops=force-enabled-no-reductionsβ Enable tail-predication, but not for reduction loops, and force this which might be unsafe=force-enabledβ Enable tail-predication, including reduction loops, and force this which might be unsafe
the force- ones literally say "might be unsafe", so don't be reckless, bestie π
--threads=<int>β the source gives no description, just a dash, so it's a mystery number of threads π§--triple=<string>β Target triple for disassembler. you pass a string triple and it's for the disassembler β¨
π¬ Action to perform:
--executeβ Load, link, and execute the inputs. it's giving full send energy π₯--printlineβ Load, link, and print line information for each function. line info for every function, slay π--printdebuglineβ Load, link, and print line information for each function using the debug object. same but with the debug object, no cap π--printobjlineβ Like -printlineinfo but does not load the object first. note it says-printlineinfoin the original, keep that exact spelling even though it's different from--printlineabove, bestie don't @ me π--verifyβ Load, link and verify the resulting memory image. verification era β--verify-region-infoβ Verify region info (time consuming). it's literally marked time consuming, so budget your patience π--vp-counters-per-site=<number>β The average number of profile counters allocated per value profiling site. average number, per site, periodt π--vp-static-allocβ Do static counter allocation for value profiler. static allocation for value profiler, iconic β¨--x86-align-branch=<string>β Specify types of branches to align (plus separated list of types): here's the type list:jccindicates conditional jumpsfusedindicates fused conditional jumpsjmpindicates direct unconditional jumpscallindicates direct and indirect callsretindicates retsindirectindicates indirect unconditional jumps
--x86-align-branch-boundary=<uint>β Control how the assembler should align branches with NOP. If the boundary's size is not 0, it should be a power of 2 and no less than 32. Branches will be aligned to prevent from being across or against the boundary of specified size. The default value 0 does not align branches. so default is0, no alignment, and if you set it, power of 2 and>= 32, fr fr π₯--x86-branches-within-32B-boundariesβ Align selected instructions to mitigate negative performance impact of Intel's micro code update for errata skx102. May break assumptions about labels corresponding to particular instructions, and should be used with caution. this one literally warns about breaking assumptions, so be careful bestie π--x86-pad-max-prefix-size=<uint>β Maximum number of prefixes to use for padding. caps the prefixes for padding π
β¨ Generic Options:
--helpβ Display available options (--help-hidden for more). the classic help, and--help-hiddenfor the extra hidden ones π«Ά--help-listβ Display list of available options (--help-list-hidden for more). a list version, with--help-list-hiddenfor more β¨--versionβ Display the version of this program. version check, iconic π
πΈ Polly Options: Configure the polly loop optimizer πΈ
--pollyβ Enable the polly optimizer (only at -O3). only at-O3, bestie, don't forget that part π--polly-2nd-level-tilingβ Enable a 2nd level loop of loop tiling. a second level of loop tiling, slay π--polly-ast-print-accessesβ Print memory access functions. prints memory access functions β¨--polly-context=<isl parameter set>β Provide additional constraints on the context parameters. the placeholder is an isl parameter set, keep it exact π«Ά--polly-dce-precise-steps=<int>β The number of precise steps between two approximating iterations. (A value of -1 schedules another approximation stage before the actual dead code elimination. note the original has an open parenthesis and no closing one, so we keep that exact, bestie π--polly-delicm-max-ops=<int>β Maximum number of isl operations to invest for lifetime analysis; 0=no limit. so0means no limit, periodt π--polly-detect-full-functionsβ Allow the detection of full functions. full function detection enabled β--polly-dump-afterβ Dump module after Polly transformations into a file suffixed with "-after". suffix is-after, exact π--polly-dump-after-file=<string>β Dump module after Polly transformations to the given file. give it a string file name, it dumps there β¨--polly-dump-beforeβ Dump module before Polly transformations into a file suffixed with "-before". suffix is-before, exact π--polly-dump-before-file=<string>β Dump module before Polly transformations to the given file. string file name, dumps before π--polly-enable-simplifyβ Simplify SCoP after optimizations. SCoP simplify after optimizations, iconic π«Ά--polly-ignore-func=<string>β Ignore functions that match a regex. Multiple regexes can be comma separated. Scop detection will ignore all functions that match ANY of the regexes provided. so regex matching, comma separated, ANY match means ignore, fr fr π₯--polly-isl-arg=<argument>β Option passed to ISL. passes an argument to ISL π--polly-on-isl-error-abortβ Abort if an isl error is encountered. abort on isl error, no cap π--polly-only-func=<string>β Only run on functions that match a regex. Multiple regexes can be comma separated. Scop detection will run on all functions that match ANY of the regexes provided. only these functions, regex, comma separated, ANY match runs, periodt β¨--polly-only-region=<identifier>β Only run on certain regions (The provided identifier must appear in the name of the region's entry block. note the original has an open parenthesis and no closing one again, keep it exact, bestie π--polly-only-scop-detectionβ Only run scop detection, but no other optimizations. just detection, no other optimizations, that's it π--polly-optimized-scopsβ Polly - Dump polyhedral description of Scops optimized with the isl scheduling optimizer and the set of post-scheduling transformations is applied on the schedule tree. long description, keep every word, it's giving detailed π--polly-parallelβ Generate thread parallel code (isl codegen only). isl codegen only, don't forget π«Ά--polly-parallel-forceβ Force generation of thread parallel code ignoring any cost model. force it, ignore cost model, lowkey intense π₯--polly-pattern-matching-based-optsβ Perform optimizations based on pattern matching. pattern matching based opts, slay β¨--polly-process-unprofitableβ Process scops that are unlikely to benefit from Polly optimizations. process the unprofitable ones, iconic π--polly-register-tilingβ Enable register tiling. register tiling enabled π--polly-reportβ Print information about the activities of Polly. report on Polly activities, periodt π--polly-showβ Highlight the code regions that will be optimized in a (CFG BBs and LLVM-IR instructions). note open parenthesis and no closing, keep exact, bestie π--polly-show-onlyβ Highlight the code regions that will be optimized in a (CFG only BBs). again open parenthesis, no closing, exact π--polly-stmt-granularity=<value>β Algorithm to use for splitting basic blocks into multiple statements. values:=bbβ One statement per basic block=scalar-indepβ Scalar independence heuristic=storeβ Store-level granularity
--polly-target=<value>β The hardware to target. values:=cpuβ generate CPU code
--polly-tilingβ Enable loop tiling. loop tiling enabled β¨--polly-vectorizer=<value>β Select the vectorization strategy. values:=noneβ No Vectorization=pollyβ Polly internal vectorizer=stripmineβ Strip-mine outer loops for the loop-vectorizer to trigger
llvm-rtdyld 11 β’ January 2022 β’ LLVM-RTDYLD(1) π that's the whole page, bestie β go forth and optimize, you absolute icon π«Άβ¨
π¦ where this page comes from
- ubuntu jammy: llvm-11 1:11.1.0-6 Β· APACHE-2-LLVM-EXCEPTIONS
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms