LLVM-MC(1)
๐ LLVM-MC(1) ๐
okay bestie, welcome to the manual page for llvm-mc 12 โ yes it says "User Commands" up top, that's the section, we move ๐
โจ NAME โจ
llvm-mc โ the manual page for llvm-mc 12 ๐
๐ DESCRIPTION ๐
OVERVIEW: the LLVM machine code playground ๐โจ
USAGE:
llvm-mc [options] <input file>
OPTIONS: (there are a LOT, buckle up bestie, this is the whole menu) ๐
๐จ Color Options ๐จ
--colorโ use colors in the output, obviously, we're not animals ๐ (default isautodetect, so it figures out the vibe itself)
โ๏ธ General options โ๏ธ
-I=<directory>โ directory where include files live ๐--aarch64-neon-syntax=<value>โ pick which style of NEON code the AArch64 backend should emit:=genericโ emit generic NEON assembly=appleโ emit Apple-style NEON assembly ๐
--abort-on-max-devirt-iterations-reachedโ bail out (abort) once the max iterations for the devirtualization CGSCC repeat pass has been hit ๐--amdgpu-bypass-slow-divโ skip the 64-bit divide for dynamic 32-bit values--amdgpu-disable-loop-alignmentโ don't align and prefetch loops, just leave them be ๐--amdgpu-disable-power-schedโ turn off scheduling that exists to minimize mAI power bursts--amdgpu-dpp-combineโ turn on the DPP combiner--amdgpu-dump-hsa-metadataโ dump the AMDGPU HSA metadata--amdgpu-enable-flat-scratchโ use flat scratch instructions--amdgpu-enable-merge-m0โ merge and hoist M0 initializations--amdgpu-promote-alloca-to-vector-limit=<uint>โ the maximum byte size to even consider for promote alloca to vector--amdgpu-reserve-vgpr-for-sgpr-spillโ allocates one VGPR for a future SGPR spill--amdgpu-sdwa-peepholeโ turn on the SDWA peepholer ๐--amdgpu-use-aa-in-codegenโ enable using AA during codegen--amdgpu-verify-hsa-metadataโ verify the AMDGPU HSA metadata--amdgpu-vgpr-index-modeโ use GPR indexing mode instead ofmovrelfor vector indexing--arch=<string>โ the target arch to assemble for, and yes you can check-versionto see which targets are actually available ๐ฏ--arm-add-build-attributesโ (no description in the source at all, it's giving mystery ๐ต๏ธโ๏ธ)--arm-implicit-it=<value>โ allow conditional instructions outside of an IT block:=alwaysโ accept in both ISAs, emit implicit ITs in Thumb=neverโ warn in ARM, reject in Thumb=armโ accept in ARM, reject in Thumb=thumbโ warn in ARM, emit implicit ITs in Thumb
--asm-show-instโ emit the internal instruction representation into the assembly file ๐ซถ
๐ฌ Action to perform:
--as-lexโ lex tokens from a.sfile--assembleโ assemble a.sfile (this is the default, bestie, the main character ๐)--disassembleโ disassemble strings of hex bytes--mdisโ marked-up disassembly of strings of hex bytes โจ--atomic-counter-update-promotedโ do the counter update with atomic fetch add, but only for promoted counters--atomic-first-counterโ use atomic fetch add for the first counter in a function (which is usually the entry counter)--bounds-checking-single-trapโ use one trap block per function--cfg-hide-deoptimize-pathsโ (again, no description given, just vibes ๐ฆ)--cfg-hide-unreachable-pathsโ (also undescribed, we simply don't know ๐)--compress-debug-sections=<value>โ choose how DWARF debug sections get compressed:=noneโ no compression=zlibโ use zlib compression=zlib-gnuโ use zlib-gnu compression (deprecated, so likeโฆ she's retired ๐)
--cost-kind=<value>โ which target cost kind you want:=throughputโ reciprocal throughput=latencyโ instruction latency=code-sizeโ code size=size-latencyโ code size and latency
--cvp-dont-add-nowrap-flagsโ (no description provided, it's mysterious and that's fine ๐)--debugify-level=<value>โ what kind of debug info to add:=locationsโ locations only=location+variablesโ locations and variables
--debugify-quietโ suppress the verbose debugify output, shhh ๐คซ--defsym=<string>โ defines a symbol to be an integer constant--disable-promote-alloca-to-ldsโ disable promote alloca to LDS--disable-promote-alloca-to-vectorโ disable promote alloca to vector--do-counter-promotionโ do counter register promotion--dot-cfg-mssa=<file name for generated dot file>โ the file name for the generated dot file--dwarf-version=<int>โ the Dwarf version--dwarf64โ generate debugging info in the 64-bit DWARF format--emscripten-cxx-exceptions-allowed=<string>โ the list of function names where Emscripten-style exception handling is enabled (peep the emscriptenEMSCRIPTEN_CATCHING_ALLOWEDoptions)--enable-cse-in-irtranslatorโ should enable CSE in irtranslator--enable-cse-in-legalizerโ should enable CSE in Legalizer--enable-emscripten-cxx-exceptionsโ WebAssembly Emscripten-style exception handling--enable-emscripten-sjljโ WebAssembly Emscripten-stylesetjmp/longjmphandling--enable-gvn-hoistโ enable the GVN hoisting pass (default = off)--enable-gvn-memdepโ (no description, it's a secret ๐ค)--enable-gvn-sinkโ enable the GVN sinking pass (default = off)--enable-load-in-loop-preโ (undescribed, love that for us ๐ฆ)--enable-load-preโ (also undescribed ๐)--enable-loop-simplifycfg-term-foldingโ (no description here either, the mystery continues โจ)--enable-name-compressionโ enable name/filename string compression--enable-split-backedge-in-load-preโ (no description, just a name and a dream ๐)--fatal-warningsโ treat warnings as errors, no mercy periodt ๐ฅ--fdebug-compilation-dir=<string>โ specifies the debug info's compilation dir--fdebug-prefix-map=<= separated key-value pairs>โ map file source paths in debug info--filetype=<value>โ choose an output file type:=asmโ emit an assembly (.s) file=nullโ don't emit anything at all (it's for timing purposes, bestie)=objโ emit a native object (.o) file
-gโ generate dwarf debugging info for assembly source files ๐--gpsize=<uint>โ Global Pointer Addressing Size. The default size is 8.--hash-based-counter-splitโ rename the counter variable of a comdat function based on cfg hash--hot-cold-splitโ enable the hot-cold splitting pass--import-all-indexโ import all external functions in index--incremental-linker-compatibleโ when used withfiletype=obj, emit an object file that can be used with an incremental linker--instcombine-code-sinkingโ enable code sinking--instcombine-guard-widening-window=<uint>โ how wide an instruction window to bypass while looking for another guard--instcombine-max-iterations=<uint>โ limit the maximum number of instruction combining iterations--instcombine-max-num-phis=<uint>โ the maximum number of phis to handle in intptr/ptrint folding--instcombine-maxarray-size=<uint>โ the maximum array size considered when doing a combine--instcombine-negator-enabledโ should we attempt to sink negations? ๐ค--instcombine-negator-max-depth=<uint>โ the maximal lookup depth when trying to check whether negation sinking is viable--instcombine-unsafe-select-transformโ enable the poison-unsafe select to and/or transform--instrprof-atomic-counter-update-allโ make all profile counter updates atomic (for testing only, so don't go shipping that ๐จ)--internalize-public-api-file=<filename>โ a file containing a list of symbol names to preserve--internalize-public-api-list=<list>โ a list of symbol names to preserve--iterative-counter-promotionโ allow counter promotion across the whole loop nest--large-code-modelโ create cfi directives that assume the code might be more than 2gb away--lto-embed-bitcode=<value>โ embed LLVM bitcode in object files produced by LTO:=noneโ do not embed=optimizedโ embed after all optimization passes=post-merge-pre-optโ embed post merge, but before optimizations
--lto-pass-remarks-filter=<regex>โ only record optimization remarks from passes whose names match the given regular expression--lto-pass-remarks-format=<format>โ the format used for serializing remarks (default: YAML)--lto-pass-remarks-output=<filename>โ output filename for pass remarks--main-file-name=<string>โ specifies the name we should consider the input file--masm-hexfloatsโ enable MASM-style hex float initializers (3F800000r)--masm-integersโ enable binary and hex masm integers (0b110and0ABCh)--matrix-default-layout=<value>โ sets the default matrix layout:=column-majorโ use column-major layout=row-majorโ use row-major layout
--mattr=<a1,+a2,-a3,...>โ target specific attributes (run-mattr=helpfor the details ๐ซถ)--max-counter-promotions=<int>โ the max number of allowed counter promotions--max-counter-promotions-per-loop=<uint>โ the max number of counter promotions per loop, so you don't blow up register pressure too much
โฆand that's only part 1, bestie, there is MORE coming, stay with me ๐
--mc-relax-allโ when you're using it together withfiletype=obj, it relaxes all the fixups in the emitted object file. all of them. every last one โจ--mcpu=<cpu-name>โ target a specific cpu type, like, be intentional about it. and if you're nosy about the options,-mcpu=helpgives you the details ๐ซ--merror-missing-parenthesisโ errors out when there's a missing parenthesis around predicate registers. no more freestyling, we're checking ๐ค--merror-noncontigious-registerโ errors out for register names that aren't contigious. yes, that's the spelling, we're leaving it exactly as it is ๐--mhvxโ enable Hexagon Vector eXtensions ๐ฅ--mhvx=<value>โ also enables Hexagon Vector eXtensions, but now you get to choose, main-character style:=v60โ build for HVX v60=v62โ build for HVX v62=v65โ build for HVX v65=v66โ build for HVX v66=v67โ build for HVX v67
--mips-compact-branches=<value>โ MIPS specific: compact branch policy. pick your era:=neverโ do not use compact branches if possible.=optimalโ use compact branches where appropriate. this is the default, she's the moment ๐=alwaysโ always use compact branches if possible.
--mips16-constant-islandsโ enable mips16 constant islands ๐ธ--mips16-hard-floatโ enable mips16 hard float ๐ธ--mir-strip-debugify-onlyโ shouldmir-strip-debugonly strip debug info from debugified modules by default? that's the question bestie--mno-compoundโ disable looking for compound instructions for Hexagon--mno-fixupโ disable fixing up resolved relocations for Hexagon--mno-ldc1-sdc1โ expand double precision loads and stores into their single precision counterparts--mno-pairingโ disable looking for duplex instructions for Hexagon--mwarn-missing-parenthesisโ warns (doesn't error, she's gentle) for missing parenthesis around predicate registers--mwarn-noncontigious-registerโ warns for register names that arent contigious (again: their spelling, not mine, love that for them)--mwarn-sign-mismatchโ warns when a signed and unsigned value are mismatched-nโ don't assume the assembly file starts in the text section. assumptions? not today--no-deprecated-warnโ suppress all deprecated warnings--no-discriminatorsโ disable generation of discriminator information.--no-exec-stackโ the file doesn't need an exec stack--no-warnโ suppress all warnings. silence, iconic, sometimes a little scary ๐ซฃ--nvptx-sched4regโ NVPTX specific: schedule for register pressue (their typo, we're keeping it, it's part of the lore)-o=<filename>โ output filename ๐--output-asm-variant=<uint>โ which syntax variant to use for output printing--poison-checking-function-localโ check that returns are non-poison. for testing purposes only, bestie, don't get any ideas--position-independentโ position independent โจ--preserve-commentsโ preserve comments in the outputted assembly. your notes stay, periodt--print-imm-hexโ prefer hex format for immediate values--r600-ir-structurizeโ use theStructurizeCFGIR pass--rdf-dumpโ no description in the original. mysterious queen behaviour, she says nothing and we respect it ๐--rdf-limit=<uint>โ also no description. same energy--relax-relocationsโ emitR_X86_64_GOTPCRELXinstead ofR_X86_64_GOTPCREL--runtime-counter-relocationโ enable relocating counters at runtime.--safepoint-ir-verifier-print-onlyโ again, no description. silent, powerful, unbothered--sample-profile-check-record-coverage=<N>โ emit a warning if less than N% of records in the input profile are matched to the IR.--sample-profile-check-sample-coverage=<N>โ emit a warning if less than N% of samples in the input profile are matched to the IR.--sample-profile-max-propagate-iterations=<uint>โ maximum number of iterations to go through when propagating sample block/edge weights through the CFG.--save-temp-labelsโ don't discard temporary labels ๐--show-encodingโ show instruction encodings--show-instโ show the internal instruction representation--show-inst-operandsโ show instruction operands as parsed--skip-ret-exit-blockโ suppress counter promotion if exit blocks containret.--speculative-counter-promotion-max-exiting=<uint>โ the max number of exiting blocks of a loop to allow speculative counter promotion--speculative-counter-promotion-to-loopโ when this option is false, if the target block is in a loop, the promotion will be disallowed unless the promoted counter update can be further/iteratively promoted into an acyclic region.--split-dwarf-file=<filename>โ DWO output filename--summary-file=<string>โ the summary file to use for function importing.--tail-predication=<value>โ MVE tail-predication pass options. the menu:=disabledโ don't tail-predicate loops=enabled-no-reductionsโ enable tail-predication, but not for reduction loops=enabledโ enable tail-predication, including reduction loops=force-enabled-no-reductionsโ enable tail-predication, but not for reduction loops, and force this which might be unsafe โ ๏ธ=force-enabledโ enable tail-predication, including reduction loops, and force this which might be unsafe โ ๏ธ
--thinlto-assume-mergedโ assume the input has already undergone ThinLTO function importing and the other pre-optimization pipeline changes.--threads=<int>โ no description given. she's booked and busy, no time to explain ๐--triple=<string>โ target triple to assemble for; peep-versionfor the available targets--verify-region-infoโ verify region info. heads up: it's time consuming โณ--vp-counters-per-site=<number>โ the average number of profile counters allocated per value profiling site.--vp-static-allocโ do static counter allocation for the value profiler--x86-align-branch=<string>โ specify which types of branches to align. it's a plus-separated list of types, and the types are:jccโ indicates conditional jumpsfusedโ indicates fused conditional jumpsjmpโ indicates direct unconditional jumpscallโ indicates direct and indirect callsretโ indicates retsindirectโ indicates indirect unconditional jumps
--x86-align-branch-boundary=<uint>โ controls how the assembler should align branches with NOP. if the boundary's size is not0, it should be a power of 2 and no less than32. branches get aligned so they don't end up across or against the boundary of that specified size. the default value0does not align branches.--x86-branches-within-32B-boundariesโ align selected instructions to mitigate the negative performance impact of Intel's micro code update for errataskx102.
โ ๏ธ this one may break assumptions about labels corresponding to particular instructions, and it should be used with caution. bestie, read that twice.
--x86-pad-max-prefix-size=<uint>โ maximum number of prefixes to use for padding
โจ Generic Options โจ
--helpโ display the available options (--help-hiddenfor more) ๐--help-listโ display the list of available options (--help-list-hiddenfor more) ๐--versionโ display the version of this program
๐ฆ Polly Options ๐ฆ โ Configure the polly loop optimizer
--pollyโ enable the polly optimizer. note that it only kicks in at-O3โจ--polly-2nd-level-tilingโ enable a 2nd level loop of loop tiling--polly-ast-print-accessesโ print memory access functions--polly-context=<isl parameter set>โ provide additional constraints on the context parameters--polly-dce-precise-steps=<int>โ the number of precise steps between two approximating iterations. (a value of-1schedules another approximation stage before the actual dead code elimination. โ yes, that parenthesis never closes in the original, we're leaving it exactly as shipped ๐--polly-delicm-max-ops=<int>โ maximum number of isl operations to invest for lifetime analysis;0=no limit--polly-detect-full-functionsโ allow the detection of full functions--polly-dump-afterโ dump the module after Polly transformations into a file suffixed with"-after"--polly-dump-after-file=<string>โ dump the module after Polly transformations to the given file--polly-dump-beforeโ dump the module before Polly transformations into a file suffixed with"-before"--polly-dump-before-file=<string>โ dump the module before Polly transformations to the given file--polly-enable-simplifyโ simplify SCoP after optimizations--polly-ignore-func=<string>โ ignore functions that match a regex. multiple regexes can be comma separated. Scop detection will ignore all functions that match ANY of the regexes provided.--polly-isl-arg=<argument>โ option passed to ISL--polly-on-isl-error-abortโ abort if an isl error is encountered ๐--polly-only-func=<string>โ only run on functions that match a regex. multiple regexes can be comma separated. Scop detection will run on all functions that match ANY of the regexes provided.--polly-only-region=<identifier>โ only run on certain regions, bestie. Heads up tho: that identifier you pass must appear in the name of the region's entry block, or it's simply not gonna find its people. ๐ซถ--polly-only-scop-detectionโ run scop detection and that's it. No other optimizations, none, zero, nada. Just the detection era. ๐--polly-optimized-scopsโ Polly dumps the polyhedral description of Scops that got optimized with the isl scheduling optimizer, and the set of post-scheduling transformations is applied on the schedule tree. It's giving very "show me the receipts". ๐--polly-parallelโ generate thread parallel code. (isl codegen only, so keep that in mind ๐)--polly-parallel-forceโ force generation of thread parallel code, ignoring any cost model whatsoever. No thoughts, no cost model, just parallel. ๐ค--polly-pattern-matching-based-optsโ perform optimizations based on pattern matching. โจ--polly-process-unprofitableโ process scops that are unlikely to benefit from Polly optimizations. Yes, even the ones that probably won't slay. Equal opportunity optimization. ๐--polly-register-tilingโ enable register tiling. ๐--polly-reportโ print information about the activities of Polly. It's basically Polly's storytime. ๐ข--polly-showโ highlight the code regions that will be optimized in a (CFG BBs and LLVM-IR instructions). ๐--polly-show-onlyโ highlight the code regions that will be optimized in a (CFG only BBs). ๐ธ--polly-stmt-granularity=<value>โ the algorithm to use for splitting basic blocks into multiple statements. Pick your fighter:=bbโ one statement per basic block. ๐งฑ=scalar-indepโ the scalar independence heuristic. ๐งฎ=storeโ store-level granularity. ๐
--polly-target=<value>โ the hardware to target. Your pick:=cpuโ generate CPU code. ๐ป
--polly-tilingโ enable loop tiling. ๐ฒ--polly-vectorizer=<value>โ select the vectorization strategy. The lineup:=noneโ no Vectorization. Rest era. ๐ด=pollyโ Polly internal vectorizer. ๐=stripmineโ strip-mine outer loops so the loop-vectorizer triggers. โ๏ธ
And that's the whole page, fr fr. This masterpiece is fromllvm-mc 12, dated February 2022, and it lives on theLLVM-MC(1)man page. Periodt. ๐ โจ
๐ฆ where this page comes from
- ubuntu jammy: llvm-12 1:12.0.1-19ubuntu3 ยท APACHE-2-LLVM-EXCEPTIONS
- ๐ girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms