AS(1)

📦 version 12.2.0, in nixpkgs unstable

okay so you opened AS(1) from GNU Development Tools, and bestie, this is the portable GNU assembler — yes, the whole architecture buffet, no cap. 💅

🌸 NAME 🌸

AS — the portable GNU assembler. That's the name. Short, iconic, does exactly what it says on the tin. ✨

🦋 SYNOPSIS 🦋

okay so here's how you call it. This is the full shape of the command, and I'm keeping every bracket exactly where it belongs, fr fr:

as [-a[cdghlns][=file]] [--alternate] [-D]
 [--compress-debug-sections]  [--nocompress-debug-sections]
 [--debug-prefix-map old=new]
 [--defsym sym=val] [-f] [-g] [--gstabs]
 [--gstabs+] [--gdwarf-2] [--gdwarf-sections]
 [--help] [-I dir] [-J]
 [-K] [-L] [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM] [--keep-locals]
 [--no-pad-sections]
 [-o objfile] [-R]
 [--hash-size=NUM] [--reduce-memory-overheads]
 [--statistics]
 [-v] [-version] [--version]
 [-W] [--warn] [--fatal-warnings] [-w] [-x]
 [-Z] [@FILE]
 [--sectname-subst] [--size-check=[error|warning]]
 [--elf-stt-common=[no|yes]]
 [--target-help] [target-options]
 [--|files ...]

🔥 TARGET 🔥

this section is giving “every architecture wants a turn on the aux” energy. It's the complete target-option menu, and I'm preserving it exactly — every weird bracket, every slash, every ..., every duplicated-looking thing. No edits, no merges, no “fixing” the lore. 🫶

and yes, the Target MICROBLAZE options: bit is literally inline after the Meta options in the original, so I'm leaving that exactly as-is. we respect the chaos. 💀

       Target AArch64 options:
          [-EB|-EL]
          [-mabi=ABI]

       Target Alpha options:
          [-mcpu]
          [-mdebug | -no-mdebug]
          [-replace | -noreplace]
          [-relax] [-g] [-Gsize]
          [-F] [-32addr]

       Target ARC options:
          [-mcpu=cpu]
          [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
          [-mcode-density]
          [-mrelax]
          [-EB|-EL]

       Target ARM options:
          [-mcpu=processor[+extension...]]
          [-march=architecture[+extension...]]
          [-mfpu=floating-point-format]
          [-mfloat-abi=abi]
          [-meabi=ver]
          [-mthumb]
          [-EB|-EL]
          [-mapcs-32|-mapcs-26|-mapcs-float|
           -mapcs-reentrant]
          [-mthumb-interwork] [-k]

       Target Blackfin options:
          [-mcpu=processor[-sirevision]]
          [-mfdpic]
          [-mno-fdpic]
          [-mnopic]

       Target CRIS options:
          [--underscore | --no-underscore]
          [--pic] [-N]
          [--emulation=criself | --emulation=crisaout]
          [--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]

       Target D10V options:
          [-O]

       Target D30V options:
          [-O|-n|-N]

       Target EPIPHANY options:
          [-mepiphany|-mepiphany16]

       Target H8/300 options:
          [-h-tick-hex]

       Target i386 options:
          [--32|--x32|--64] [-n]
          [-march=CPU[+EXTENSION...]] [-mtune=CPU]

       Target i960 options:
          [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
           -AKC|-AMC]
          [-b] [-no-relax]

       Target IA-64 options:
          [-mconstant-gp|-mauto-pic]
          [-milp32|-milp64|-mlp64|-mp64]
          [-mle|mbe]
          [-mtune=itanium1|-mtune=itanium2]
          [-munwind-check=warning|-munwind-check=error]
          [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
          [-x|-xexplicit] [-xauto] [-xdebug]

       Target IP2K options:
          [-mip2022|-mip2022ext]

       Target M32C options:
          [-m32c|-m16c] [-relax] [-h-tick-hex]

       Target M32R options:
          [--m32rx|--[no-]warn-explicit-parallel-conflicts|
          --W[n]p]

       Target M680X0 options:
          [-l] [-m68000|-m68010|-m68020|...]

       Target M68HC11 options:
          [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
          [-mshort|-mlong]
          [-mshort-double|-mlong-double]
          [--force-long-branches] [--short-branches]
          [--strict-direct-mode] [--print-insn-syntax]
          [--print-opcodes] [--generate-example]

       Target MCORE options:
          [-jsri2bsr] [-sifilter] [-relax]
          [-mcpu=[210|340]]

       Target Meta options:
          [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:

       Target MIPS options:
          [-nocpp] [-EL] [-EB] [-O[optimization level]]
          [-g[debug level]] [-G num] [-KPIC] [-call_shared]
          [-non_shared] [-xgot [-mvxworks-pic]
          [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
          [-mfp64] [-mgp64] [-mfpxx]
          [-modd-spreg] [-mno-odd-spreg]
          [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
          [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
          [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
          [-mips64r3] [-mips64r5] [-mips64r6]
          [-construct-floats] [-no-construct-floats]
          [-mignore-branch-isa] [-mno-ignore-branch-isa]
          [-mnan=encoding]
          [-trap] [-no-break] [-break] [-no-trap]
          [-mips16] [-no-mips16]
          [-mmips16e2] [-mno-mips16e2]
          [-mmicromips] [-mno-micromips]
          [-msmartmips] [-mno-smartmips]
          [-mips3d] [-no-mips3d]
          [-mdmx] [-no-mdmx]
          [-mdsp] [-mno-dsp]
          [-mdspr2] [-mno-dspr2]
          [-mdspr3] [-mno-dspr3]
          [-mmsa] [-mno-msa]
          [-mxpa] [-mno-xpa]
          [-mmt] [-mno-mt]
          [-mmcu] [-mno-mcu]
          [-minsn32] [-mno-insn32]
          [-mfix7000] [-mno-fix7000]
          [-mfix-rm7000] [-mno-fix-rm7000]
          [-mfix-vr4120] [-mno-fix-vr4120]
          [-mfix-vr4130] [-mno-fix-vr4130]
          [-mdebug] [-no-mdebug]
          [-mpdr] [-mno-pdr]

       Target MMIX options:
          [--fixed-special-register-names] [--globalize-symbols]
          [--gnu-syntax] [--relax] [--no-predefined-symbols]
          [--no-expand] [--no-merge-gregs] [-x]
          [--linker-allocated-gregs]

       Target Nios II options:
          [-relax-all] [-relax-section] [-no-relax]
          [-EB] [-EL]

       Target NDS32 options:
           [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
           [-misa=isa] [-mabi=abi] [-mall-ext]
           [-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
           [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
           [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
           [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
           [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
           [-mb2bb]

       Target PDP11 options:
          [-mpic|-mno-pic] [-mall] [-mno-extensions]
          [-mextension|-mno-extension]
          [-mcpu] [-mmachine]

       Target picoJava options:
          [-mb|-me]

       Target PowerPC options:
          [-a32|-a64]
          [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
           -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
           -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
           -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
           -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
           -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
          [-many] [-maltivec|-mvsx|-mhtm|-mvle]
          [-mregnames|-mno-regnames]
          [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
          [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
          [-msolaris|-mno-solaris]
          [-nops=count]

       Target PRU options:
          [-link-relax]
          [-mnolink-relax]
          [-mno-warn-regname-label]

       Target RISC-V options:
          [-fpic|-fPIC|-fno-pic]
          [-march=ISA]
          [-mabi=ABI]

       Target RL78 options:
          [-mg10]
          [-m32bit-doubles|-m64bit-doubles]

       Target RX options:
          [-mlittle-endian|-mbig-endian]
          [-m32bit-doubles|-m64bit-doubles]
          [-muse-conventional-section-names]
          [-msmall-data-limit]
          [-mpid]
          [-mrelax]
          [-mint-register=number]
          [-mgcc-abi|-mrx-abi]

       Target s390 options:
          [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
          [-mregnames|-mno-regnames]
          [-mwarn-areg-zero]

       Target SCORE options:
          [-EB][-EL][-FIXDD][-NWARN]
          [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
          [-march=score7][-march=score3]
          [-USE_R1][-KPIC][-O0][-G num][-V]

       Target SPARC options:
          [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
           -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
           -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
           -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
           -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
           -Asparcvisr|-Asparc5]
          [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
           -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
           -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
           -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
           -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
           -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
           -bump]
          [-32|-64]
          [--enforce-aligned-data][--dcti-couples-detect]

       Target TIC54X options:
        [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
        [-merrors-to-file <filename>|-me <filename>]

       Target TIC6X options:
          [-march=arch] [-mbig-endian|-mlittle-endian]
          [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
          [-mpic|-mno-pic]

       Target TILE-Gx options:
          [-m32|-m64][-EB][-EL]

       Target Visium options:
          [-mtune=arch]

       Target Xtensa options:
        [--[no-]text-section-literals] [--[no-]auto-litpools]
        [--[no-]absolute-literals]
        [--[no-]target-align] [--[no-]longcalls]
        [--[no-]transform]
        [--rename-section oldname=newname]
        [--[no-]trampolines]

       Target Z80 options:
         [-z80] [-r800]
         [ -ignore-undocumented-instructions] [-Wnud]
         [ -ignore-unportable-instructions] [-Wnup]
         [ -warn-undocumented-instructions] [-Wud]
         [ -warn-unportable-instructions] [-Wup]
         [ -forbid-undocumented-instructions] [-Fud]
         [ -forbid-unportable-instructions] [-Fup]

💖 DESCRIPTION 💖

okay so picture this: GNU as is literally not just one assembler, it’s a whole family of assemblers. If you use (or have used) the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called pseudo-ops) and assembler syntax. slay.

as is primarily intended to assemble the output of the GNU C compiler gcc for use by the linker ld. Nevertheless, we’ve tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly. This doesn’t mean as always uses the same syntax as another assembler for the same architecture; for example, we know of several incompatible versions of 680x0 assembly language syntax. 😭 iconic chaos, honestly.

Each time you run as it assembles exactly one source program. The source program is made up of one or more files. (The standard input is also a file.) 🫶

You give as a command line that has zero or more input file names. The input files are read (from left file name to right). A command line argument (in any position) that has no special meaning is taken to be an input file name. simple as that.

If you give as no file names it attempts to read one input file from the as standard input, which is normally your terminal. You may have to type ctl-D to tell as there is no more program to assemble. 💅

Use -- if you need to explicitly name the standard input file in your command line.

If the source is empty, as produces a small, empty object file. tiny king behavior.

as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly. ⚠️ no cap, pay attention to those.

If you are invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the -Wa) by commas. For example:

gcc -c -g -O -Wa,-alh,-L file.c

This passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table). ✨

Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.) iykyk.

✨ OPTIONS ✨

  • @file — read command-line options from file. The options read are inserted in place of the original @file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed.
    • Options in file are separated by whitespace.
    • A whitespace character may be included in an option by surrounding the entire option in either single or double quotes.
    • Any character (including a backslash) may be included by prefixing the character to be included with a backslash.
    • The file may itself contain additional @file options; any such options will be processed recursively. 🌀
  • -a[cdghlmns] — turn on listings, in any of a variety of ways:
    • -ac — omit false conditionals
    • -ad — omit debugging directives
    • -ag — include general information, like as version and options passed
    • -ah — include high-level source
    • -al — include assembly
    • -am — include macro expansions
    • -an — omit forms processing
    • -as — include symbols
    • =file — set the name of the listing file

You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls. 🎀

  • --alternate — begin in alternate macro mode.
  • --compress-debug-sections — compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities. Note: if compression would make a given section larger, then it is not compressed. ⚠️
  • --compress-debug-sections=none, --compress-debug-sections=zlib, --compress-debug-sections=zlib-gnu, --compress-debug-sections=zlib-gabi — these options control how DWARF debug sections are compressed. --compress-debug-sections=none is equivalent to --nocompress-debug-sections. --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to --compress-debug-sections. --compress-debug-sections=zlib-gnu compresses DWARF debug sections using zlib. The debug sections are renamed to begin with .zdebug. Note: if compression would make a given section larger, then it is not compressed nor renamed. 💅
  • --nocompress-debug-sections — do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.
  • -D — ignored. This option is accepted for script compatibility with calls to other assemblers.
  • --debug-prefix-map old=new — when assembling files in directory old, record debugging information describing them as in new instead.
  • --defsym sym=value — define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a .set pseudo-op. 🧚
  • -f — “fast” — skip whitespace and comment preprocessing (assume source is compiler output).
  • -g, --gen-debug — generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2.
  • --gstabs — generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
  • --gstabs+ — generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time. 😭 read the warning, bestie.
  • --gdwarf-2 — generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note: this option is only supported by some targets, not all of them.
  • --gdwarf-sections — instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. For example a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. If the code section is just called .text then debug line section will still be called just .debug_line without any suffix. 🌸
  • --size-check=error, --size-check=warning — issue an error or warning for invalid ELF .size directive.
  • --elf-stt-common=no, --elf-stt-common=yes — these options control whether the ELF assembler should generate common symbols with the "STT_COMMON" type. The default can be controlled by a configure option --enable-elf-stt-common.
  • --help — print a summary of the command line options and exit.
  • --target-help — print a summary of all target specific options and exit.
  • -I dir — add directory dir to the search list for .include directives.
  • -J — don’t warn about signed overflow.
  • -K — issue warnings when difference tables altered for long displacements.
  • -L, --keep-locals — keep (in the symbol table) local symbols. These symbols start with system-specific local label prefixes, typically .L for ELF systems or L for traditional a.out systems.
  • --listing-lhs-width=number — set the maximum width, in words, of the output data column for an assembler listing to number.
  • --listing-lhs-width2=number — set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number.
  • --listing-rhs-width=number — set the maximum width of an input source line, as displayed in a listing, to number bytes.
  • --listing-cont-lines=number — set the maximum number of lines printed in a listing for a single line of input to number + 1.
  • --no-pad-sections — stop the assembler from padding the ends of output sections to the alignment of that section. The default is to pad the sections, but this can waste space which might be needed on targets which have tight memory constraints. 👑
  • -o objfile — name the object-file output from as objfile.
  • -R — fold the data section into the text section.
  • --hash-size=number — set the default size of GAS’s hash tables to a prime number close to number. Increasing this value can reduce the length of time it takes the assembler to perform its tasks, at the expense of increasing the assembler’s memory requirements. Similarly reducing this value can reduce the memory requirements at the expense of speed. 🦋
  • --reduce-memory-overheads — this option reduces GAS’s memory requirements, at the expense of making the assembly processes slower. Currently this switch is a synonym for --hash-size=4051, but in the future it may have other effects as well.
  • --sectname-subst — honor substitution sequences in section names.
  • --statistics — print the maximum space (in bytes) and total time (in seconds) used by assembly.
  • --strip-local-absolute — remove local absolute symbols from the outgoing symbol table.
  • -v, -version — print the as version.
  • --version — print the as version and exit.
  • -W, --no-warn — suppress warning messages.
  • --fatal-warnings — treat warnings as errors. 🔥
  • --warn — don’t suppress warning messages or treat them as errors.
  • -w — ignored.
  • -x — ignored.
  • -Z — generate an object file even after errors. 💀 bold.
  • -- | files ... — standard input, or source files to assemble.

The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). 🌈

  • -EB — this option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.
  • -EL — marks the output the assembler makes as being encoded for a little-endian processor 🧚
  • -mabi=abi — tells it which ABI the source code is using. Recognized args are "ilp32" and "lp64", which decide whether the generated object file comes out in ELF32 or ELF64 format respectively. The default is "lp64" ✨
  • -mcpu=processor[+extension...] — picks the target processor. Try to assemble an instruction that won't run on that processor and the assembler will hit you with an error message, no cap. Recognized processor names: "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a72", "cortex-a73", "cortex-a75", "exynos-m1", "falkor", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1" and "xgene2". There's also a special name "all" — use that and the assembler accepts instructions valid for any supported processor, including all optional extensions 💅

Beyond the basic instruction set, you can tell the assembler to accept, or restrict, various extension mnemonics that extend the processor.

If some implementations of a particular processor can have an extension, then those extensions are automatically enabled — so normally you won't have to specify any extra extensions at all. Iconic behaviour tbh 🎀

  • -march=architecture[+extension...] — specifies the target architecture. Same deal: assemble an instruction that won't execute on the target architecture and you get an error message. Recognized architecture names: "armv8-a", "armv8.1-a", "armv8.2-a", "armv8.3-a" and "armv8.4-a".

If both -mcpu and -march are specified, the assembler uses the setting for -mcpu. If neither is specified, the assembler defaults to -mcpu=all.

The architecture option can be extended with the same instruction set extension options as the -mcpu option. But unlike -mcpu, extensions are not always enabled by default 👀

  • -mverbose-error — turns on verbose error messages for AArch64 gas. This one is enabled by default, so it's already slaying for you 🫶
  • -mno-verbose-error — turns verbose error messages off in AArch64 gas.

🌸 The following options are available when as is configured for an Alpha processor 🌸

  • -mcpu — specifies the target processor. If you try to assemble an instruction that won't execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the .arch directive.

Recognized processor names: 21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6", "ev67", "ev68". (yep, "ev5" shows up twice in there — not me, that's the list 💀) The special name "all" lets the assembler accept instructions valid for any Alpha processor.

To support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. "ev4") do not 💅

  • -mdebug
  • -no-mdebug — enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. The default is to automatically enable .mdebug when the first stabs directive is seen ✨
  • -relax — forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Heads up: this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. That said, it can still be useful in specific applications 🦋
  • -replace
  • -noreplace — enables or disables the optimization of procedure calls, both at assemblage and at link time. These are only available for VMS targets, and -replace is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual 📚
  • -g — used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect, literally nothing 🌈
  • -Gsize — a local common symbol larger than size gets placed in .bss, while smaller symbols go in .sbss.
  • -F
  • -32addr — these options are ignored for backward compatibility 🙈

🦋 The following options are available when as is configured for an ARC processor 🦋

  • -mcpu=cpu — selects the core processor variant.
  • -EB | -EL — select either big-endian (-EB) or little-endian (-EL) output.
  • -mcode-density — enable Code Density extension instructions 🎀

💜 The following options are available when as is configured for the ARM processor family 💜

  • -mcpu=processor[+extension...] — specify which ARM processor variant is the target.
  • -march=architecture[+extension...] — specify which ARM architecture variant is used by the target.
  • -mfpu=floating-point-format — select which Floating Point architecture is the target.
  • -mfloat-abi=abi — select which floating point ABI is in use.
  • -mthumb — enable Thumb only instruction decoding.
  • -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant — select which procedure calling convention is in use.
  • -EB | -EL — select either big-endian (-EB) or little-endian (-EL) output.
  • -mthumb-interwork — specify that the code has been generated with interworking between Thumb and ARM code in mind.
  • -mccs — turns on CodeComposer Studio assembly syntax compatibility mode.
  • -k — specify that PIC code has been generated.

🍓 The following options are available when as is configured for the Blackfin processor family 🍓

  • -mcpu=processor[-sirevision] — specifies the target processor. The optional sirevision is not used in the assembler; it's here so GCC can easily pass down its -mcpu= option. The assembler will issue an error message if you attempt to assemble an instruction which will not execute on the target processor. Recognized processor names: "bf504", "bf506", "bf512", "bf514", "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526", "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542", "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m", "bf549", "bf549m", "bf561", and "bf592" 💅
  • -mfdpic — assemble for the FDPIC ABI.
  • -mno-fdpic
  • -mnopic — disable -mfdpic.

See the info pages for documentation of the CRIS-specific options — yeah, they live over there, go look 👑 (Wait, you need CRIS docs? Info pages. That's the vibe.)

⭐ The following options are available when as is configured for a D10V processor ⭐

  • -O — optimize output by parallelizing instructions.

🔥 The following options are available when as is configured for a D30V processor 🔥

  • -O — optimize output by parallelizing instructions.
  • -n — warn when nops are generated.
  • -N — warn when a nop after a 32-bit multiply instruction is generated.

🧚 The following options are available when as is configured for an Epiphany processor 🧚

  • -mepiphany — specifies that both 32 and 16 bit instructions are allowed. This is the default behavior, so it's just doing its thing already 💖
  • -mepiphany16 — restricts the permitted instructions to just the 16 bit set.

💠 The following options are available when as is configured for an H8/300 processor 💠

@chapter H8/300 Dependent Features

(no babe I didn't mistype, that line is literally in there — we keep the lore 🫶)

Options

The Renesas H8/300 version of as has one machine-dependent option:

  • -h-tick-hex — support H'00 style hex constants in addition to 0x00 style.
  • -mach=name — sets the H8300 machine variant. Recognized machine names: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and "h8300sxn" ✨

🌈 The following options are available when as is configured for an i386 processor 🌈

  • --32 | --x32 | --64 — select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.

These options are only available with the ELF object file format, and they require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure to enable 64-bit usage and use x86-64 as target platform). So like, check your build first bestie 😭

  • -n — by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables that optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment 👑
  • --divide — on SVR4-derived platforms, the character / is treated as a comment character, which means it can't be used in expressions. The --divide option turns / into a normal character. This does not disable / at the beginning of a line starting a comment, and it doesn't affect using # for starting a comment 💅
  • -march=CPU[+EXTENSION...] — specifies the target processor. Assemble an instruction that won't execute on the target processor and the assembler issues an error message. Recognized processor names: "i8086", "i186", "i286", "i386", "i486", "i586", "i686", "pentium", "pentiumpro", "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona", "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2", "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2", "bdver3", "bdver4", "znver1", "btver1", "btver2", "generic32" and "generic64" 🦋

so like — beyond the basic instruction set, you can also tell the assembler to accept a whole buffet of extension mnemonics. for example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. the currently supported extensions are 8087, 287, 387, 687, no87, no287, no387, no687, mmx, nommx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4, nosse, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4, avx, avx2, noavx, noavx2, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, noavx512f, noavx512cd, noavx512er, noavx512pf, noavx512vl, noavx512bw, noavx512dq, noavx512ifma, noavx512vbmi, noavx512_4fmaps, noavx512_4vnniw, noavx512_vpopcntdq, noavx512_vbmi2, noavx512_vnni, noavx512_bitalg, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, hle, rtm, invpcid, clflush, mwaitx, clzero, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, svme, abm and padlock 💅

real talk though — the mnemonics that start with no don't extend the instruction set, they revoke that functionality. like, taking it back. 🙈

also important: when the .arch directive is used together with -march, the .arch directive takes precedent. periodt. 👑

  • -mtune=CPU — tells the assembler which processor to optimize for. when you also pass -march, only instructions belonging to the processor named by -march will actually get generated. the valid CPU values are literally the same list as -march=CPU. same list, no extra credit. ✨
  • -msse2avx — tells the assembler it should encode SSE instructions with a VEX prefix. that's it, that's the whole vibe. 🦋
  • -msse-check=none, -msse-check=warning, -msse-check=error — these three control whether the assembler checks SSE instructions at all:
    • -msse-check=none → don't check SSE instructions. this is the default, bestie.
    • -msse-check=warning → issue a warning for any SSE instruction.
    • -msse-check=error → issue an error for any SSE instruction. no chill mode.
  • -mavxscalar=128, -mavxscalar=256 — control how scalar AVX instructions get encoded.
    • -mavxscalar=128 → encode them with 128bit vector length. default ✨
    • -mavxscalar=256 → encode them with 256bit vector length.
  • -mevexlig=128, -mevexlig=256, -mevexlig=512 — control how length-ignored (LIG) EVEX instructions get encoded.
    • -mevexlig=128 → 128bit vector length. default, iconic 🎀
    • -mevexlig=256 → 256bit vector length.
    • -mevexlig=512 → 512bit vector length.
  • -mevexwig=0, -mevexwig=1 — control how w-ignored (WIG) EVEX instructions get encoded.
    • -mevexwig=0 → encodes WIG EVEX instructions with evex.w = 0. default 💜
    • -mevexwig=1 → encodes them with evex.w = 1.
  • -mmnemonic=att, -mmnemonic=intel — picks which instruction mnemonic to match instructions by. heads up: the .att_mnemonic and .intel_mnemonic directives will take precedent 👑
  • -msyntax=att, -msyntax=intel — picks the instruction syntax used when processing instructions. again: the .att_syntax and .intel_syntax directives will take precedent.
  • -mnaked-reg — says registers don't need a % prefix. (naked registers, scandalous 💀) the .att_syntax and .intel_syntax directives will take precedent.
  • -madd-bnd-prefix — forces the assembler to slap a BND prefix on all branches, even when the source code never explicitly asked for one. generous of it ngl.
  • -mno-shared — on ELF targets the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. the -mshared option tells it to instead generate code that could go into a shared library, where all non-weak global branch targets with default visibility can be preempted. resulting code is slightly bigger. this only affects how branch instructions are handled, fyi.
  • -mbig-obj — on x86-64 PE/COFF targets this forces the big object file format, which allows more than 32768 sections. that's a lot of sections bestie 😭
  • -momit-lock-prefix=no, -momit-lock-prefix=yes — control how the assembler encodes the lock prefix. this one is a workaround for processors that fail on lock prefix.
    • -momit-lock-prefix=yes → omits all lock prefixes.
    • -momit-lock-prefix=no → encodes lock prefix as usual. default
⚠️ seriously though: this option can only be safely used on single-core, single-thread computers. like, read that twice. 🙈
  • -mfence-as-lock-add=no, -mfence-as-lock-add=yes — control how lfence, mfence and sfence get encoded.
    • -mfence-as-lock-add=yes → encodes lfence, mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode, and lock addl $0x0, (%esp) in 32-bit mode.
    • -mfence-as-lock-add=no → encodes them as usual. default ✨
  • -mrelax-relocations=no, -mrelax-relocations=yes — control whether the assembler generates relax relocations: R_386_GOT32X in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX in 64-bit mode.
    • -mrelax-relocations=yes → generate relax relocations.
    • -mrelax-relocations=no → don't.

the default can be controlled by a configure option: --enable-x86-relax-relocations 🛠️

  • -mevexrcig=rne, -mevexrcig=rd, -mevexrcig=ru, -mevexrcig=rz — control how SAE-only EVEX instructions get encoded.
    • -mevexrcig=rne → encodes the RC bits of the EVEX instruction with 00. default 💖
    • -mevexrcig=rd → 01 RC bits.
    • -mevexrcig=ru → 10 RC bits.
    • -mevexrcig=rz → 11 RC bits.
  • -mamd64, -mintel64 — says the assembler should accept only AMD64 or only Intel64 ISA in 64-bit mode. the default is to accept both, because why choose 🌈

🕹️ when as is configured for the Intel 80960 processor

the following options are available:

  • -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC — pick which variant of the 960 architecture is the target.
  • -b — add code to collect statistics about branches taken. data girlie behavior 📊
  • -no-relax — do not alter compare-and-branch instructions for long displacements; error if necessary. it will simply ✨refuse✨

🍓 when as is configured for the Ubicom IP2K series

  • -mip2022ext — says the extended IP2022 instructions are allowed.
  • -mip2022 — restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. back to basics, no extras 💅

🌸 when as is configured for the Renesas M32C and M16C processors

  • -m32c — assemble M32C instructions.
  • -m16c — assemble M16C instructions. this one's the default.
  • -relax — enable support for link-time relaxations.
  • -h-tick-hex — support H'00 style hex constants in addition to 0x00 style. two hex flavors, both valid 🍓

🦋 when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series

  • --m32rx — specify which processor in the M32R family is the target. the default is normally the M32R, but this option changes it to the M32RX.
  • --warn-explicit-parallel-conflicts or --Wp — produce warning messages when questionable parallel constructs are encountered. questionable!! 👀
  • --no-warn-explicit-parallel-conflicts or --Wnp — do not produce warning messages when questionable parallel constructs are encountered.

🧚 when as is configured for the Motorola 68000 series

  • -l — shorten references to undefined symbols, to one word instead of two. little savings, big icon energy ✨
  • -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 — specify what processor in the 68000 family is the target. the default is normally the 68020, but this can be changed at configuration time.
  • -m68881 | -m68882 | -mno-68881 | -mno-68882 — the target machine does (or does not) have a floating-point coprocessor. default is to assume a coprocessor for 68020, 68030, and cpu32. and like, even though the basic 68000 isn't compatible with the 68881, you can specify a combination of the two, because it's possible to emulate the coprocessor instructions with the main processor. loophole slay 💅
  • -m68851 | -mno-68851 — the target machine does (or does not) have a memory-management unit coprocessor. default is to assume an MMU for 68020 and up.

🎀 when as is configured for an Altera Nios II processor

  • -relax-section — replace identified out-of-range branches with PC-relative jmp sequences when possible. the generated code sequences are suitable for position-independent code, but there's a practical limit on the extended branch range because of the length of the sequences. this option is the default ✨
  • -relax-all — replace branch instructions that can't be determined to be in range, plus all call instructions, with jmp and callr sequences respectively. this generates absolute relocations against the target symbols and is not appropriate for position-independent code. 🚨
  • -no-relax — do not replace any branches or calls.
  • -EB — generate big-endian output.
  • -EL — generate little-endian output. this is the default 💖
  • -march=architecture — specifies the target architecture. the assembler issues an error message if you try to assemble an instruction which will not execute on the target architecture. recognized architecture names are r1 and r2. the default is r1. (yes, another -march, different context, don't @ me 😭)

🧵 when as is configured for a PRU processor

okay so—

  • -mlink-relax — tells as to assume LD is gonna do that cute LDI32 glow-up: LD peeks at the upper 16 bits of the expression, and if they're all zeros it shortens LDI32 down to a single LDI. In that scenario as outputs DIFF relocations for diff expressions. slay for LD 💅
  • -mno-link-relax — opposite vibe: assume LD will not optimize LDI32 instructions. consequence? DIFF relocations don't get emitted at all. ✨
  • -mno-warn-regname-label — turns off the warning you'd normally get when a label name matches a register name. ngl, assembler programmers usually want that warning, but C compilers may wanna turn it off. 🫶

🌸 MIPS time!! 🌸

The following options are available when as is configured for a MIPS processor. buckle up bestie, there's a lot 💖

  • -G num — sets the largest size of an object that can be referenced implicitly with the gp register. only accepted for targets that use ECOFF format, like a DECstation running Ultrix. default value is 8. 📏
  • -EB — generate "big endian" format output.
  • -EL — generate "little endian" format output. (the endian girlies stay winning 💅)
  • -mips1, -mips2, -mips3, -mips4, -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, -mips64r6 — generate code for a particular MIPS Instruction Set Architecture level. the tea ☕:
    • -mips1 is an alias for -march=r3000
    • -mips2 is an alias for -march=r6000
    • -mips3 is an alias for -march=r4000
    • -mips4 is an alias for -march=r8000
    • -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. periodt ✨
  • -march=cpu — generate code for a particular MIPS CPU. 🎀
  • -mtune=cpu — schedule and tune for a particular MIPS CPU.
  • -mfix7000, -mno-fix7000 — cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
  • -mfix-rm7000, -mno-fix-rm7000 — cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.
  • -mdebug, -no-mdebug — cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections. 🐛
  • -mpdr, -mno-pdr — control generation of .pdr sections.
  • -mgp32, -mfp32 — register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.
  • -mgp64, -mfp64 — same deal but 64 bits, always. -mgp64 controls the size of general-purpose registers and -mfp64 controls the size of floating-point registers.
  • -mfpxx — register sizes are normally inferred from the ISA and ABI, but using this flag in combination with -mabi=32 enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide. flexible queen 🌈
  • -modd-spreg, -mno-odd-spreg — enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA. -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg.
  • -mips16, -no-mips16 — generate code for the MIPS 16 processor. equivalent to putting .module mips16 at the start of the assembly file. -no-mips16 turns off this option.
  • -mmips16e2, -mno-mips16e2 — enable the use of MIPS16e2 instructions in MIPS16 mode. equivalent to putting .module mips16e2 at the start of the assembly file. -mno-mips16e2 turns off this option.
  • -mmicromips, -mno-micromips — generate code for the microMIPS processor. equivalent to putting .module micromips at the start of the assembly file. -mno-micromips turns off this option. that one is equivalent to putting .module nomicromips at the start of the assembly file. little lowercase era 💅
  • -msmartmips, -mno-smartmips — enables the SmartMIPS extension to the MIPS32 instruction set. equivalent to putting .module smartmips at the start of the assembly file. -mno-smartmips turns off this option.
  • -mips3d, -no-mips3d — generate code for the MIPS-3D Application Specific Extension. tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option.
  • -mdmx, -no-mdmx — generate code for the MDMX Application Specific Extension. tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.
  • -mdsp, -mno-dsp — generate code for the DSP Release 1 Application Specific Extension. tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option.
  • -mdspr2, -mno-dspr2 — generate code for the DSP Release 2 Application Specific Extension. this option implies -mdsp. tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option.
  • -mdspr3, -mno-dspr3 — generate code for the DSP Release 3 Application Specific Extension. this option implies -mdsp and -mdspr2. tells the assembler to accept DSP Release 3 instructions. -mno-dspr3 turns off this option.
  • -mmsa, -mno-msa — generate code for the MIPS SIMD Architecture Extension. tells the assembler to accept MSA instructions. -mno-msa turns off this option.
  • -mxpa, -mno-xpa — generate code for the MIPS eXtended Physical Address (XPA) Extension. tells the assembler to accept XPA instructions. -mno-xpa turns off this option.
  • -mmt, -mno-mt — generate code for the MT Application Specific Extension. tells the assembler to accept MT instructions. -mno-mt turns off this option.
  • -mmcu, -mno-mcu — generate code for the MCU Application Specific Extension. tells the assembler to accept MCU instructions. -mno-mcu turns off this option.
  • -minsn32, -mno-insn32 — only use 32-bit instruction encodings when generating code for the microMIPS processor. this option inhibits the use of any 16-bit instructions. equivalent to putting .set insn32 at the start of the assembly file. -mno-insn32 turns off this option, and it's equivalent to putting .set noinsn32 at the start of the assembly file. by default -mno-insn32 is selected, allowing all instructions to be used. 🫶
  • --construct-floats, --no-construct-floats — the --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. by default --construct-floats is selected, allowing construction of these floating point constants. ✨
  • --relax-branch, --no-relax-branch — the --relax-branch option enables the relaxation of out-of-range branches. by default --no-relax-branch is selected, causing any out-of-range branches to produce an error. no chill, just error 💀
  • -mignore-branch-isa, -mno-ignore-branch-isa — ignore branch checks for invalid transitions between ISA modes. here's the lore: the semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. so GAS has checks implemented that verify in branch assembly that the two ISA modes match. -mignore-branch-isa disables these checks. by default -mno-ignore-branch-isa is selected, causing any invalid branch requiring a transition between ISA modes to produce an error. 🚨
  • -mnan=encoding — pick between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format. the latter is the default. ngl, legacy is giving vintage 🎀
  • --emulation=name — ok so this one used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. it's retained for backwards compatibility only. the available configuration names are: mipself, mipslelf and mipsbelf. choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferred options instead. 🦋
  • -nocpp — as ignores this option. it's accepted for compatibility with the native tools. the "seen but not heard" icon 💅
  • --trap, --no-trap, --break, --no-break — control how to deal with multiplication overflow and division by zero. --trap or --no-break (which are synonyms) take a trap exception, and those only work for Instruction Set Architecture level 2 and higher. --break or --no-trap (also synonyms, and the default) take a break exception. 😭
  • -n — when this option is used, as will issue a warning every time it generates a nop instruction from a macro. lil nop watchdog, honestly iconic 🐕

🧚 Meta processor zone 🧚

The following options are available when as is configured for a Meta processor.

  • -mcpu=metac11 — generate code for Meta 1.1.
  • -mcpu=metac12 — generate code for Meta 1.2.
  • -mcpu=metac21 — generate code for Meta 2.1.
  • -mfpu=metac21 — allow code to use FPU hardware of Meta 2.1. 🔥
lowkey important aside: see the info pages for documentation of the MMIX-specific options. not here bestie, different page 📖

🌺 NDS32 processor section 🌺

The following options are available when as is configured for a NDS32 processor.

  • -O1 — optimize for performance.
  • -Os — optimize for space.
  • -EL — produce little endian data output.
  • -EB — produce little endian data output.
  • -mpic — generate PIC.
  • -mno-fp-as-gp-relax — suppress fp-as-gp relaxation for this file.
  • -mb2bb-relax — back-to-back branch optimization.
  • -mno-all-relax — suppress all relaxation for this file.
  • -march=<arch name> — assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.
  • -mbaseline=<baseline> — assemble for baseline <baseline> which could be v2, v3, v3m.
  • -mfpu-freg=FREG — specify a FPU configuration.
ok do not come for me about -EB up there saying "little endian" 💀 that is word-for-word what the page says, I am simply the messenger, copy-paste accuracy is my whole brand 🫶
  • "0" — 8 SP / 4 DP registers
  • "1" — 16 SP / 8 DP registers
  • "2" — 32 SP / 16 DP registers
  • "3" — 32 SP / 32 DP registers
  • -mabi=abi — pick an abi version, bestie. abi can be v1, v2, v2fp, or v2fpp.
  • -m[no-]mac — turn Multiply instructions support on/off.
  • -m[no-]div — turn Divide instructions support on/off.
  • -m[no-]16bit-ext — turn the 16-bit extension on/off.
  • -m[no-]dx-regs — turn the d0/d1 registers on/off.
  • -m[no-]perf-ext — turn Performance extension on/off.
  • -m[no-]perf2-ext — turn Performance extension 2 on/off.
  • -m[no-]string-ext — turn String extension on/off.
  • -m[no-]reduced-regs — turn the Reduced Register configuration (GPR16) option on/off.
  • -m[no-]audio-isa-ext — turn the AUDIO ISA extension on/off.
  • -m[no-]fpu-sp-ext — turn the FPU SP extension on/off.
  • -m[no-]fpu-dp-ext — turn the FPU DP extension on/off.
  • -m[no-]fpu-fma — turn FPU fused-multiply-add instructions on/off.
  • -mall-ext — turn on all extensions and instructions support. literally the "select all" checkbox of assembler flags 👑

🦋 when as is configured for a PowerPC processor

these are the options you get, and there are… a lot of them. buckle up bestie 💅

  • -a32 — generate ELF32 or XCOFF32.
  • -a64 — generate ELF64 or XCOFF64.
  • -K PIC — set EF_PPC_RELOCATABLE_LIB in ELF flags.
  • -mpwrx | -mpwr2 — generate code for POWER/2 (RIOS2).
  • -mpwr — generate code for POWER (RIOS1).
  • -m601 — generate code for PowerPC 601.
  • -mppc, -mppc32, -m603, -m604 — generate code for PowerPC 603/604.
  • -m403, -m405 — generate code for PowerPC 403/405.
  • -m440 — generate code for PowerPC 440. BookE and some 405 instructions.
  • -m464 — generate code for PowerPC 464.
  • -m476 — generate code for PowerPC 476.
  • -m7400, -m7410, -m7450, -m7455 — generate code for PowerPC 7400/7410/7450/7455.
  • -m750cl — generate code for PowerPC 750CL.
  • -m821, -m850, -m860 — generate code for PowerPC 821/850/860.
  • -mppc64, -m620 — generate code for PowerPC 620/625/630.
  • -me500, -me500x2 — generate code for Motorola e500 core complex.
  • -me500mc — generate code for Freescale e500mc core complex.
  • -me500mc64 — generate code for Freescale e500mc64 core complex.
  • -me5500 — generate code for Freescale e5500 core complex.
  • -me6500 — generate code for Freescale e6500 core complex.
  • -mspe — generate code for Motorola SPE instructions.
  • -mspe2 — generate code for Freescale SPE2 instructions.
  • -mtitan — generate code for AppliedMicro Titan core complex.
  • -mppc64bridge — generate code for PowerPC 64, including bridge insns.
  • -mbooke — generate code for 32-bit BookE.
  • -ma2 — generate code for A2 architecture.
  • -me300 — generate code for PowerPC e300 family.
  • -maltivec — generate code for processors with AltiVec instructions.
  • -mvle — generate code for Freescale PowerPC VLE instructions.
  • -mvsx — generate code for processors with Vector-Scalar (VSX) instructions.
  • -mhtm — generate code for processors with Hardware Transactional Memory instructions.
  • -mpower4, -mpwr4 — generate code for Power4 architecture.
  • -mpower5, -mpwr5, -mpwr5x — generate code for Power5 architecture.
  • -mpower6, -mpwr6 — generate code for Power6 architecture.
  • -mpower7, -mpwr7 — generate code for Power7 architecture.
  • -mpower8, -mpwr8 — generate code for Power8 architecture.
  • -mpower9, -mpwr9 — generate code for Power9 architecture.
  • -mcell — generate code for Cell Broadband Engine architecture. (it's listed twice in the original — she contains multitudes 💀)
  • -mcom — generate code Power/PowerPC common instructions.
  • -many — generate code for any architecture (PWR/PWRX/PPC).
  • -mregnames — allow symbolic names for registers.
  • -mno-regnames — do not allow symbolic names for registers.
  • -mrelocatable — support for GCC's -mrelocatable option.
  • -mrelocatable-lib — support for GCC's -mrelocatable-lib option.
  • -memb — set PPC_EMB bit in ELF flags.
  • -mlittle, -mlittle-endian, -le — generate code for a little endian machine.
  • -mbig, -mbig-endian, -be — generate code for a big endian machine.
  • -msolaris — generate code for Solaris.
  • -mno-solaris — do not generate code for Solaris.
  • -nops=count — if an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops. lowkey genius ✨

🌸 when as is configured for a RISC-V processor

  • -fpic
  • -fPIC — generate position-independent code. (same energy, two spellings 🫶)
  • -fno-pic — don't generate position-independent code (default).
  • -march=ISA — select the base isa, as specified by ISA. for example -march=rv32ima.
  • -mabi=ABI — selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none to indicate the soft-float calling convention.

🎀 RX-specific options

see the info pages for documentation of the RX-specific options. that's the whole vibe check, go read the info pages bestie 💖

⭐ when as is configured for the s390 processor family

  • -m31
  • -m64 — select the word size, either 31/32 bits or 64 bits.
  • -mesa
  • -mzarch — select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).
  • -march=processor — specify which s390 processor variant is the target: g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), or z14 (or arch12). pick your fighter 😤
  • -mregnames
  • -mno-regnames — allow or disallow symbolic names for registers.
  • -mwarn-areg-zero — warn whenever the operand for a base or index register has been specified but evaluates to zero. honestly? it's just looking out for you 🫶

🔥 when as is configured for a TMS320C6000 processor

  • -march=arch — enable (only) instructions from architecture arch. by default, all instructions are permitted.

the following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x".

  • -mdsbt
  • -mno-dsbt — the -mdsbt option causes the assembler to generate the "Tag_ABI_DSBT" attribute with a value of 1, indicating that the code is using DSBT addressing. the -mno-dsbt option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. the linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. ⚠️
  • -mpid=no
  • -mpid=near
  • -mpid=far — the -mpid= option causes the assembler to generate the "Tag_ABI_PID" attribute with a value indicating the form of data addressing used by the code. -mpid=no, the default, indicates position-dependent data addressing, -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing, and -mpid=far indicates position-independent addressing with GOT accesses using far DP addressing. the linker will emit a warning if objects built with different settings of this option are linked together. ⚠️
  • -mpic
  • -mno-pic — the -mpic option causes the assembler to generate the "Tag_ABI_PIC" attribute with a value of 1, indicating that the code is using position-independent code addressing. the -mno-pic option, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. the linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together. ⚠️
  • -mbig-endian
  • -mlittle-endian — generate code for the specified endianness. the default is little-endian.

💜 when as is configured for a TILE-Gx processor

  • -m32 | -m64 — select the word size, either 32 bits or 64 bits.
  • -EB | -EL — select the endianness, either big-endian (-EB) or little-endian (-EL).

🧚 when as is configured for a Visium processor

  • -mtune=arch — this option specifies the target architecture. if an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. 😭

the following names are recognized: "mcm24" "mcm" "gr5" "gr6"

🌈 when as is configured for an Xtensa processor

  • --text-section-literals | --no-text-section-literals — control the treatment of literal pools. the default is --no-text-section-literals, which places literals in separate sections in the output file. this allows the literal pool to be placed in a data RAM/ROM. with --text-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. this may be necessary for large assembly files, where the literals would otherwise be out of range of the "L32R" instructions in the text section. literals are grouped into pools following .literal_position directives or preceding ENTRY instructions. these options only affect literals referenced via PC-relative "L32R" instructions; literals for absolute mode "L32R" instructions are handled separately.
  • --auto-litpools | --no-auto-litpools — control the treatment of literal pools (yes, again, they're siblings 👯). the default is --no-auto-litpools, which in the absence of --text-section-literals places literals in separate sections in the output file. this allows the literal pool to be placed in a data RAM/ROM. with --auto-litpools, the literals are interspersed in the text section in order to keep them as close as possible to their references, explicit .literal_position directives are not required. this may be necessary for very large functions, where single literal pool at the beginning of the function may not be reachable by "L32R" instructions at the end. these options only affect literals referenced via PC-relative "L32R" instructions; literals for absolute mode "L32R" instructions are handled separately. when used together with --text-section-literals, --auto-litpools takes precedence. 👑
  • --absolute-literals | --no-absolute-literals — okay so this tells the assembler whether L32R instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute L32R relocations. Otherwise, only the PC-relative L32R relocations can be used. 💅
  • --target-align | --no-target-align — enable or disable automatic alignment to reduce branch penalties, at some expense in code size. This optimization is enabled by default. Note that the assembler will always align instructions like LOOP that have fixed alignment requirements. ✨
  • --longcalls | --no-longcalls — enable or disable transformation of call instructions so calls can reach a greater range of addresses. Use this when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. The default is --no-longcalls. 👑
  • --transform | --no-transform — enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The default is --transform; --no-transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source. Using --no-transform causes out of range instruction operands to be errors. ⚠️
  • --rename-section oldname=newname — rename the oldname section to newname. This option can be used multiple times to rename multiple sections. 🎀
  • --trampolines | --no-trampolines — enable or disable transformation of jump instructions so jumps can reach a greater range of addresses. Use this when jump targets can potentially be out of range. In the absence of such jumps this option does not affect code size or performance. The default is --trampolines. 🦋

The following options are available when as is configured for a Z80 family processor. 🕹️

  • -z80 — assemble for Z80 processor. 💾
  • -r800 — assemble for R800 processor. 🎮
  • -ignore-undocumented-instructions, -Wnud — assemble undocumented Z80 instructions that also work on R800 without warning. 🙈
  • -ignore-unportable-instructions, -Wnup — assemble all undocumented Z80 instructions without warning. 🌈
  • -warn-undocumented-instructions, -Wud — issue a warning for undocumented Z80 instructions that also work on R800. ⚠️
  • -warn-unportable-instructions, -Wup — issue a warning for undocumented Z80 instructions that do not work on R800. 🚨
  • -forbid-undocumented-instructions, -Fud — treat all undocumented instructions as errors. ❌
  • -forbid-unportable-instructions, -Fup — treat undocumented Z80 instructions that do not work on R800 as errors. 🛑

🫶 SEE ALSO 🫶

gcc(1), ld(1), and the Info entries for binutils and ld. iykyk, those are the next besties to check. 💖

Copyright (c) 1991-2018 Free Software Foundation, Inc. 💜

Okay, legal moment, no skipping: Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". periodt. 🌈

Source/version: binutils-2.30 — dated 2018-01-27 — page: AS(1). That's the whole iconic footer vibe, bestie: go assemble something legendary. 💅✨

📦 where this page comes from