CXL-RESERVE-DPA(1)
β¨ cxl-reserve-dpa β¨
okay so real talk, this one lives in the cxl Manual, section 1, and it's genuinely one of my faves because it's like the little reservation desk for device memory π
π NAME π
cxl-reserve-dpa β allocate device-physical address space π«Ά
πΈ SYNOPSIS πΈ
cxl reserve-dpa <mem0> [<mem1>..<memN>] [<options>]
okay so the CXL region provisioning process is a whole multi-step thing, right? it doesn't just happen in one go. one of those steps is figuring out and reserving the DPA span that each member of the interleave-set (that's the region, bestie) contributes β and you gotta do that in advance of attaching that allocation to a region. so for development, test, and debug purposes, this command is your little helper buddy: it finds the next available decoder on the endpoint (memdev) and marks a span of DPA as busy. slay π₯
β¨ OPTIONS β¨
<memory device(s)>β amemXdevice name, or a memdev id number. use it to restrict the operation to the specified memdev(s). and if you sayall, that means no restriction at all β go wild, no cap π-S,--serialβ instead of a memdev id number, read the<memdev>argument(s) as a list of serial numbers. iykyk π¦-b,--bus=β restrict the operation to the specified bus.-d,--decoderβ pick which decoder to attempt the allocation on. here's the tea β: the CXL specification mandates that allocations must be ordered by DPA and decoder instance β meaning the lowest DPA allocation on the device is covered bydecoder0, and the last / highest DPA allocation is covered by the last decoder. the kernel enforces this ordering, fr fr. by default, the tool just picks the next available decoder for you π-t,--typeβ select the partition for the allocation. CXL devices implement a partition that dividesramandpmemcapacity, wherepmemcapacity consumes the higher DPA capacity above the partition boundary. the type defaults topmem. β οΈ note that given CXL DPA allocation constraints, once any pmem allocation is established, then all remaining ram capacity becomes reserved (skipped). like, gone. skipped. sorry bestie π-f,--forceβ so the kernel enforces those CXL DPA allocation ordering constraints, and the tool anticipates them and fails operations that are expected to fail without even sending them to the kernel. for test purposes though, this flag says "no, actually, send it anyway" β it continues to attempt "expected to fail" operations to exercise the driver. chaos mode, but make it intentional π-s,--sizeβ specify the size of the allocation. this option supports the suffixeskorKfor KiB,morMfor MiB,gorGfor GiB andtorTfor TiB. this defaults to "all available capacity of the specified type" β like, the whole thing π₯-vβ turn on verbose debug messages in the library (iflibcxlwas built with logging and debug enabled). basically the "tell me everything" button π
π COPYRIGHT π
Copyright Β© 2016 - 2022, Intel Corporation. License GPLv2: GNU GPL version 2 http://gnu.org/licenses/gpl.html. This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. (yes, all caps NO WARRANTY β they mean it, bestie π)
π SEE ALSO π
cxl-free-dpa(1)β the other half of the story, go give it a read π§
and that's the whole vibe check, bestie π this page came to you from the cxl manual, dated 2026-06-30 β stay caffeinated, keep your DPA ordered, and go reserve some space, periodt ππβ¨
π¦ where this page comes from
- arch rolling: ndctl 85-1 Β· LGPL-2.1-only AND GPL-2.0-only AND CC0-1.0 AND MIT
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms