CLANG-REPL(1)
π NAME π
clang-repl β okay so this is the manual page for clang-repl 14, and bestie, it's a lot, but we're gonna get through it together π
π¦ DESCRIPTION π¦
So here's the whole entire usage vibe:
USAGE: clang-repl [options] [code to run]
That's it. That's the shape of it. Options, and optionally some code you want to actually run, and she'll handle the rest β¨
π OPTIONS π
π Color Options π
--colorβ bestie, this one just uses colors in the output. And yeah, it'sdefault=autodetect, so she checks the vibe for herself before committing to a palette π¨
π General options π
--Xcc=<string>β an argument you're passing straight through to theCompilerInvocation. She'll take it from there π«‘--aarch64-neon-syntax=<value>β pick which style of NEON code the AArch64 backend emits:=genericβ emit generic NEON assembly=appleβ emit Apple-style NEON assembly
--aarch64-use-aaβ turn on the use of AA during codegen--abort-on-max-devirt-iterations-reachedβ abort the whole thing when we hit the max iterations for the devirtualization CGSCC repeat pass π--addrsigβ emit an address-significance table--align-loops=<uint>β the default alignment for loops--allow-ginsert-as-artifactβ allowG_INSERTto be considered an artifact. It's a hack to work around AMDGPU test infinite loops, no cap π--amdgpu-bypass-slow-divβ skip the 64-bit divide for dynamic 32-bit values--amdgpu-disable-loop-alignmentβ don't align and prefetch loops--amdgpu-disable-power-schedβ disable scheduling to minimize mAI power bursts--amdgpu-dpp-combineβ enable the DPP combiner--amdgpu-dump-hsa-metadataβ dump AMDGPU HSA Metadata--amdgpu-enable-flat-scratchβ use flat scratch instructions--amdgpu-enable-merge-m0β merge and hoist M0 initializations--amdgpu-promote-alloca-to-vector-limit=<uint>β the maximum byte size to consider when promoting alloca to vector--amdgpu-sdwa-peepholeβ enable the SDWA peepholer--amdgpu-use-aa-in-codegenβ enable the use of AA during codegen--amdgpu-verify-hsa-metadataβ verify AMDGPU HSA Metadata--amdgpu-vgpr-index-modeβ use GPR indexing mode instead of movrel for vector indexing--arm-add-build-attributesβ (no description given, she's just there, existing, mysterious)--arm-implicit-it=<value>β allow conditional instructions outside of an IT block:=alwaysβ accept in both ISAs, emit implicit ITs in Thumb=neverβ warn in ARM, reject in Thumb=armβ accept in ARM, reject in Thumb=thumbβ warn in ARM, emit implicit ITs in Thumb
--asm-show-instβ emit the internal instruction representation into the assembly file--atomic-counter-update-promotedβ do counter update using atomic fetch add for promoted counters only--atomic-first-counterβ use atomic fetch add for the first counter in a function (which is usually the entry counter)--basic-block-sections=<all | <function list (file)> | labels | none>β emit basic blocks into separate sections--bounds-checking-single-trapβ use one trap block per function--cfg-hide-cold-paths=<number>β hide blocks whose relative frequency falls below the given value--cfg-hide-deoptimize-pathsβ (no description, iconic silent type energy)--cfg-hide-unreachable-pathsβ (also no description, matching her sister's vibe)--code-model=<value>β choose the code model:=tinyβ Tiny code model=smallβ Small code model=kernelβ Kernel code model=mediumβ Medium code model=largeβ Large code model
--cost-kind=<value>β target cost kind:=throughputβ Reciprocal throughput=latencyβ Instruction latency=code-sizeβ Code size=size-latencyβ Code size and latency
--data-sectionsβ emit data into separate sections--debug-entry-valuesβ enable debug info for the debug entry values--debug-info-correlateβ use debug info to correlate profiles--debugger-tune=<value>β tune debug info for a particular debugger:=gdbβ gdb=lldbβ lldb=dbxβ dbx=sceβ SCE targets (e.g. PS4)
--debugify-level=<value>β the kind of debug info to add:=locationsβ Locations only=location+variablesβ Locations and Variables
--debugify-quietβ suppress the verbose debugify output π€«--denormal-fp-math=<value>β select which denormal numbers the code is permitted to require:=ieeeβ IEEE 754 denormal numbers=preserve-signβ the sign of a flushed-to-zero number is preserved in the sign of 0=positive-zeroβ denormals are flushed to positive zero
--denormal-fp-math-f32=<value>β same deal but forfloat: select which denormal numbers the code is permitted to require:=ieeeβ IEEE 754 denormal numbers=preserve-signβ the sign of a flushed-to-zero number is preserved in the sign of 0=positive-zeroβ denormals are flushed to positive zero
--disable-i2p-p2i-optβ disables the inttoptr/ptrtoint roundtrip optimization--disable-promote-alloca-to-ldsβ disable promote alloca to LDS--disable-promote-alloca-to-vectorβ disable promote alloca to vector--disable-tail-callsβ never emit tail calls. Never ever. Periodt β--do-counter-promotionβ do counter register promotion--dot-cfg-mssa=<file name for generated dot file>β file name for generated dot file--dwarf-version=<int>β Dwarf version--dwarf64β generate debugging info in the 64-bit DWARF format--emit-call-site-infoβ emit call site debug information, if debug information is enabled--emscripten-cxx-exceptions-allowed=<string>β the list of function names in which Emscripten-style exception handling is enabled (see the emscriptenEMSCRIPTEN_CATCHING_ALLOWEDoptions)--emulated-tlsβ use the emulated TLS model--enable-cse-in-irtranslatorβ should enable CSE in irtranslator--enable-cse-in-legalizerβ should enable CSE in Legalizer--enable-emscripten-cxx-exceptionsβ WebAssembly Emscripten-style exception handling--enable-emscripten-sjljβ WebAssembly Emscripten-style setjmp/longjmp handling--enable-gvn-hoistβ enable the GVN hoisting pass (default = off)--enable-gvn-memdepβ (no description given, she's keeping it to herself π)--enable-gvn-sinkβ enable the GVN sinking pass (default = off)--enable-load-in-loop-preβ (no description, mysterious as ever)--enable-load-preβ (also no description)--enable-loop-simplifycfg-term-foldingβ (no description here either, we love a cryptic queen)--enable-name-compressionβ enable name/filename string compression--enable-no-infs-fp-mathβ enable FP math optimizations that assume no Β±Infs--enable-no-nans-fp-mathβ enable FP math optimizations that assume no NaNs--enable-no-signed-zeros-fp-mathβ enable FP math optimizations that assume the sign of 0 is insignificant--enable-no-trapping-fp-mathβ enable setting the FP exceptions build attribute not to use exceptions--enable-split-backedge-in-load-preβ (no description, staying mysterious π )--enable-unsafe-fp-mathβ enable optimizations that may decrease FP precision β οΈ she is literally telling you the precision can drop, so listen--exception-model=<value>β exception model:=defaultβ default exception handling model=dwarfβ DWARF-like CFI based exception handling=sjljβ SjLj exception handling=armβ ARM EHABI exceptions=winehβ Windows exception model=wasmβ WebAssembly exception handling
--execute-concurrency=<uint>β the number of threads used to process all files in parallel. Set it to0for hardware concurrency. Heads up bestie: this flag only applies to all-TUs.--executor=<string>β the name of the executor to use--experimental-debug-variable-locationsβ use experimental new value-tracking variable locations π§ͺ--fatal-warningsβ treat warnings as errors. No more "it's just a warning" delulu, every warning is now a whole error π₯
...and that's not even all of it, bestie β there's more where this came from π
--filetype=<value>β bestie, pick your file type π (and lowkey, not every target supports every single type, so check before you commit):=asmβ emit an assembly file, aka the.sone=objβ emit a native object file, aka the.oone=nullβ emit literally nothing at all β this one's purely for performance testing, no cap
--filter=<string>β only process the files that match this filter. heads up tho: this flag only applies to all-TUs, so don't come for me if it does nothing elsewhere π--float-abi=<value>β choose your float ABI type:=defaultβ the target's default float ABI type=softβ soft float ABI (this one gets implied by-soft-float)=hardβ hard float ABI, it uses FP registers
--force-dwarf-frame-sectionβ always emit a debug frame section. every time. periodt.--fp-contract=<value>β enables aggressive formation of fused FP ops, which is giving optimizer main character energy:=fastβ fuse FP ops whenever it's profitable=onβ only fuse the 'blessed' FP ops=offβ only fuse FP ops when the result won't be affected
--frame-pointer=<value>β specify frame pointer elimination optimization:=allβ disable frame pointer elimination=non-leafβ disable frame pointer elimination for non-leaf frames=noneβ enable frame pointer elimination
--fs-profile-debug-bw-threshold=<uint>β only show the debug message if the source branch weight is greater than this value.--fs-profile-debug-prob-diff-threshold=<uint>β only show the debug message if the branch probility is greater than this value (in percentage).--function-sectionsβ emit functions into separate sections β¨--generate-merged-base-profilesβ when you're generating nested context-sensitive profiles, this always generates an extra base profile for a function with all of its context profiles merged into it.--gpsize=<uint>β Global Pointer Addressing Size. the default size is8.--hash-based-counter-splitβ rename the counter variable of a comdat function based on cfg hash.--hot-cold-splitβ enable the hot-cold splitting pass π₯π§--ignore-xcoff-visibilityβ don't emit the visibility attribute for asm in AIX OS, or give all symbols 'unspecified' visibility in a XCOFF object file.--import-all-indexβ import all external functions in index.--incremental-linker-compatibleβ when used withfiletype=obj, emit an object file that can be used with an incremental linker.--instcombine-code-sinkingβ enable code sinking.--instcombine-guard-widening-window=<uint>β how wide an instruction window to bypass while looking for another guard.--instcombine-max-iterations=<uint>β cap the maximum number of instruction combining iterations.--instcombine-max-num-phis=<uint>β maximum number of phis to handle in intptr/ptrint folding.--instcombine-maxarray-size=<uint>β the maximum array size considered when doing a combine.--instcombine-negator-enabledβ should we even attempt to sink negations? asking for a friend.--instcombine-negator-max-depth=<uint>β what's the maximal lookup depth when trying to check for viability of negation sinking.--instrprof-atomic-counter-update-allβ make all profile counter updates atomic (for testing only π).--internalize-public-api-file=<filename>β a file containing a list of symbol names to preserve.--internalize-public-api-list=<list>β a list of symbol names to preserve.--iterative-counter-promotionβ allow counter promotion across the whole loop nest.--lto-embed-bitcode=<value>β embed LLVM bitcode in object files produced by LTO:=noneβ do not embed=optimizedβ embed after all optimization passes=post-merge-pre-optβ embed post merge, but before optimizations
--lto-pass-remarks-filter=<regex>β only record optimization remarks from passes whose names match the given regular expression.--lto-pass-remarks-format=<format>β the format used for serializing remarks (default:YAML).--lto-pass-remarks-output=<filename>β output filename for pass remarks.--march=<string>β the architecture to generate code for (peep--version).--matrix-default-layout=<value>β sets the default matrix layout:=column-majorβ use column-major layout=row-majorβ use row-major layout
--mattr=<a1,+a2,-a3,...>β target specific attributes (-mattr=helpfor the details, bestie).--max-counter-promotions=<int>β max number of allowed counter promotions.--max-counter-promotions-per-loop=<uint>β max number of counter promotions per loop, so we don't crank the register pressure up too much π--mc-relax-allβ when used withfiletype=obj, relax all fixups in the emitted object file.--mcabacβ tbd π«Ά (no fr, that's what it says)--mcpu=<cpu-name>β target a specific cpu type (-mcpu=helpfor the details).--meabi=<value>β set the EABI type (the default depends on the triple):=defaultβ triple default EABI version=4β EABI version 4=5β EABI version 5=gnuβ EABI GNU
--merror-missing-parenthesisβ error for a missing parenthesis around predicate registers.--merror-noncontigious-registerβ error for register names that aren't contigious.--mhvxβ enable Hexagon Vector eXtensions β¨--mhvx=<value>β enable Hexagon Vector eXtensions:=v60β build for HVX v60=v62β build for HVX v62=v65β build for HVX v65=v66β build for HVX v66=v67β build for HVX v67=v68β build for HVX v68=v69β build for HVX v69
--mips-compact-branches=<value>β MIPS Specific: compact branch policy.=neverβ do not use compact branches if possible.=optimalβ use compact branches where appropriate (this one's the default).=alwaysβ always use compact branches if possible.
--mips16-constant-islandsβ enable mips16 constant islands.--mips16-hard-floatβ enable mips16 hard float.--mir-strip-debugify-onlyβ shouldmir-strip-debugonly strip debug info from debugified modules by default?--mno-compoundβ disable looking for compound instructions for Hexagon.--mno-fixupβ disable fixing up resolved relocations for Hexagon.--mno-ldc1-sdc1β expand double precision loads and stores into their single precision counterparts.--mno-pairingβ disable looking for duplex instructions for Hexagon.--mwarn-missing-parenthesisβ warn for a missing parenthesis around predicate registers.--mwarn-noncontigious-registerβ warn for register names that arent contigious.--mwarn-sign-mismatchβ warn for mismatching a signed and an unsigned value.--no-deprecated-warnβ suppress all deprecated warnings.--no-discriminatorsβ disable generation of discriminator information.--no-type-checkβ suppress type errors (Wasm).--no-warnβ suppress all warnings π€«--no-xray-indexβ don't emit thexray_fn_idxsection.--nozero-initialized-in-bssβ don't place zero-initialized symbols into the bss section.--nvptx-sched4regβ NVPTX Specific: schedule for register pressue.--opaque-pointersβ use opaque pointers.--poison-checking-function-localβ check that returns are non-poison (for testing).--print-pipeline-passesβ print a-passescompatible string describing the pipeline (best-effort only, so don't hold me to it π).--r600-ir-structurizeβ use the StructurizeCFG IR pass.--rdf-dumpβ no description given, it's just vibes π--rdf-limit=<uint>β also no description, we love a mystery π¦--relax-elf-relocationsβ emitGOTPCRELX/REX_GOTPCRELXinstead ofGOTPCRELon x86-64 ELF.--relocation-model=<value>β choose relocation model.=staticβ non-relocatable code π=picβ fully relocatable, position independent code β¨=dynamic-no-picβ relocatable external references, non-relocatable code π=ropiβ code and read-only data relocatable, accessed PC-relative=rwpiβ read-write data relocatable, accessed relative to static base=ropi-rwpiβ the combination ofropiandrwpi, bestie, both at once π«Ά
--runtime-counter-relocationβ enable relocating counters at runtime. moving them around, live, no biggie β¨--safepoint-ir-verifier-print-onlyβ that's literally all the manpage says, no description given, we move--sample-profile-check-record-coverage=<N>β emit a warning if less than N% of records in the input profile are matched to the IR. so if your profile is slacking, you get a lil heads up π--sample-profile-check-sample-coverage=<N>β emit a warning if less than N% of samples in the input profile are matched to the IR.--sample-profile-max-propagate-iterations=<uint>β maximum number of iterations to go through when propagating sample block/edge weights through the CFG. yes, the CFG. we love a control flow graph moment β--skip-ret-exit-blockβ suppress counter promotion if exit blocks containret.--speculative-counter-promotion-max-exiting=<uint>β the max number of exiting blocks of a loop to allow speculative counter promotion.--speculative-counter-promotion-to-loopβ when the option is false, if the target block is in a loop, the promotion will be disallowed unless the promoted counter update can be further/iteratively promoted into an acyclic region.--split-machine-functionsβ split out cold basic blocks from machine functions based on profile information. the cold ones get their own lil corner βοΈ--stack-size-sectionβ emit a section containing stack size metadata.--stack-symbol-orderingβ order local stack symbols.--stackrealignβ force align the stack to the minimum alignment.--strict-dwarfβ use strict dwarf. no cap, strict π--summary-file=<string>β the summary file to use for function importing.--swift-async-fp=<value>β determine when the Swift async frame pointer should be set.=autoβ determine based on deployment target=alwaysβ always set the bit=neverβ never set the bit
--tail-predication=<value>β MVE tail-predication pass options.=disabledβ don't tail-predicate loops=enabled-no-reductionsβ enable tail-predication, but not for reduction loops=enabledβ enable tail-predication, including reduction loops=force-enabled-no-reductionsβ enable tail-predication, but not for reduction loops, and force this which might be unsafe=force-enabledβ enable tail-predication, including reduction loops, and force this which might be unsafe
bestie the force- ones say "might be unsafe" right there in the text. i'm just the messenger π¨
--tailcalloptβ turnfastcccalls into tail calls by (potentially) changing ABI. potentially changing the ABI. nbd. iconic actually--thinlto-assume-mergedβ assume the input has already undergone ThinLTO function importing and the other pre-optimization pipeline changes.--thread-model=<value>β choose threading model.=posixβ POSIX thread model=singleβ Single thread model
--threads=<int>β the manpage gives no description here. just vibes. she's mysterious π--tls-size=<uint>β bit size of immediate TLS offsets.--unique-basic-block-section-namesβ give unique names to every basic block section. every single one gets her own name, main character treatment π--unique-section-namesβ give unique names to every section.--use-ctorsβ use.ctorsinstead of.init_array.--vec-extabiβ enable the AIX Extended Altivec ABI.--verify-region-infoβ verify region info (time consuming). she's thorough. she's also slow. pick a lane bestie β³--vp-counters-per-site=<number>β the average number of profile counters allocated per value profiling site.--vp-static-allocβ do static counter allocation for value profiler.--wasm-enable-ehβ WebAssembly exception handling.--wasm-enable-sjljβ WebAssemblysetjmp/longjmphandling.--x86-align-branch=<string>β specify types of branches to align (plus separated list of types):jccβ indicates conditional jumpsfusedβ indicates fused conditional jumpsjmpβ indicates direct unconditional jumpscallβ indicates direct and indirect callsretβ indicates retsindirectβ indicates indirect unconditional jumps
--x86-align-branch-boundary=<uint>β control how the assembler should align branches withNOP. If the boundary's size is not 0, it should be a power of 2 and no less than 32. Branches will be aligned to prevent from being across or against the boundary of specified size. The default value0does not align branches. so like, 0 means no aligning, got it π«‘--x86-branches-within-32B-boundariesβ align selected instructions to mitigate negative performance impact of Intel's micro code update for errataskx102. May break assumptions about labels corresponding to particular instructions, and should be used with caution.
caution!! it can break your assumptions about labels β instructions. read that twice, bestie π
--x86-pad-max-prefix-size=<uint>β maximum number of prefixes to use for padding.--xcoff-traceback-tableβ emit the XCOFF traceback table.
π Generic Options π
--helpβ display available options (--help-hiddenfor more). the classic. the blueprint. use it, fr fr π--help-listβ display list of available options (--help-list-hiddenfor more).--versionβ display the version of this program. slay, now you know what you're running β¨
πΈ Polly Options πΈ β Configure the polly loop optimizer
--pollyβ enable the polly optimizer (with-O1,-O2or-O3). only those three optimization levels, periodt--polly-2nd-level-tilingβ enable a 2nd level loop of loop tiling. tiling on tiling. inception energy π--polly-ast-print-accessesβ print memory access functions.--polly-context=<isl parameter set>β provide additional constraints on the context parameters.--polly-dce-precise-steps=<int>β the number of precise steps between two approximating iterations. (A value of-1schedules another approximation stage before the actual dead code elimination.--polly-delicm-max-ops=<int>β maximum number of isl operations to invest for lifetime analysis;0=no limit. zero means go feral, unlimited ops π--polly-detect-full-functionsβ allow the detection of full functions.--polly-dump-afterβ dump module after Polly transformations into a file suffixed with"-after".--polly-dump-after-file=<string>β dump module after Polly transformations to the given file.--polly-dump-beforeβ dump module before Polly transformations into a file suffixed with"-before".--polly-dump-before-file=<string>β dump module before Polly transformations to the given file.--polly-enable-simplifyβ simplify SCoP after optimizations.--polly-ignore-func=<string>β ignore functions that match a regex. Multiple regexes can be comma separated. Scop detection will ignore all functions that match ANY of the regexes provided. ANY of them. not all. ANY π«Ά--polly-isl-arg=<argument>β option passed to ISL.--polly-on-isl-error-abortβ abort if an isl error is encountered.--polly-only-func=<string>β only run on functions that match a regex. Multiple regexes can be comma separated. Scop detection will run on all functions that match ANY of the regexes provided.--polly-only-region=<identifier>β only run on certain regions (The provided identifier must appear in the name of the region's entry block.--polly-only-scop-detectionβ only run scop detection, but no other optimizations. just looking, not touching π--polly-optimized-scopsβ Polly - Dump polyhedral description of Scops optimized with the isl scheduling optimizer and the set of post-scheduling transformations is applied on the schedule tree.--polly-parallelβ generate thread parallel code (isl codegen only).--polly-parallel-forceβ force generation of thread parallel code ignoring any cost model. ignoring the cost model entirely?? bold. we love a reckless queen π--polly-pattern-matching-based-optsβ perform optimizations based on pattern matching.--polly-postoptsβ apply post-rescheduling optimizations such as tiling (requires-polly-reschedule). note the requirement, bestie, she needs-polly-rescheduleπ₯--polly-pragma-based-optsβ apply user-directed transformation from metadata.--polly-pragma-ignore-depcheckβ skips the dependency check for pragma-based transformations. no dep check, no problem, we move π«Ά--polly-process-unprofitableβ processes scops that are unlikely to benefit from Polly optimizations. it's giving "let me try anyway" energy ngl π--polly-register-tilingβ enables register tiling β¨--polly-reportβ prints information about the activities of Polly. she's telling you what she's been up to π--polly-rescheduleβ optimizes SCoPs using ISL πΈ--polly-showβ highlights the code regions that will be optimized in a (CFG BBs and LLVM-IR instructions). yes bestie, show us the glow-up spots π--polly-show-onlyβ highlights the code regions that will be optimized in a (CFG only BBs). same vibe, but CFG only β no LLVM-IR instructions on this one.--polly-stmt-granularity=<value>β the algorithm to use for splitting basic blocks into multiple statements. pick your fighter:=bbβ one statement per basic block=scalar-indepβ scalar independence heuristic=storeβ store-level granularity
--polly-target=<value>β the hardware to target π―=cpuβ generate CPU code
--polly-tilingβ enable loop tiling π§±--polly-vectorizer=<value>β select the vectorization strategy. choose wisely:=noneβ no vectorization=pollyβ Polly internal vectorizer=stripmineβ strip-mine outer loops for the loop-vectorizer to trigger
and that's the whole page, bestie!! π that was clang-repl version 14, dated May 2025 β you've officially read the entire CLANG-REPL(1) manual top to bottom and honestly? iconic behavior πβ go compile something slay ππ¦
π¦ where this page comes from
- ubuntu questing: clang-tools-14 1:14.0.6-20ubuntu3
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms