AS(1)
👑 AS(1) — GNU Development Tools 👑
okay so bestie, welcome to AS(1). this is the manual page for the portable GNU assembler from the GNU Development Tools, and bestie she is THAT girl. she takes your assembly and turns it into object files across basically every CPU that has ever existed. no cap. the target list alone is like 40 architectures long, it's giving "collect them all" energy. 🫶 let's get into it.
🌸 NAME 🌸
AS — the portable GNU assembler. that's the whole name. short, sweet, iconic, periodt. 💅
🦋 SYNOPSIS 🦋
so here's how you summon her, literally all the flags, none skipped, none merged, exactly as written:
as [-a[cdghilns][=file]]
[--alternate]
[--compress-debug-sections] [--nocompress-debug-sections]
[-D]
[--dump-config]
[--debug-prefix-map old=new]
[--defsym sym=val]
[--elf-stt-common=[no|yes]]
[--emulation=name]
[-f]
[-g] [--gstabs] [--gstabs+]
[--gdwarf-<N>] [--gdwarf-sections]
[--gdwarf-cie-version=VERSION]
[--generate-missing-build-notes=[no|yes]]
[--gsframe] [--gsframe=[no|yes]]
[--gsframe-3]
[--hash-size=N]
[--help] [--target-help]
[--info] [--no-info]
[-I dir]
[-J]
[-K]
[--keep-locals]
[-L]
[--listing-lhs-width=NUM]
[--listing-lhs-width2=NUM]
[--listing-rhs-width=NUM]
[--listing-cont-lines=NUM]
[--multibyte-handling=[allow|warn|warn-sym-only]]
[--no-pad-sections]
[-o objfile] [-R]
[--reloc-section-sym=[all|internal|none]]
[--scfi=experimental]
[--sectname-subst]
[--size-check=[error|warning]]
[--statistics]
[-v] [--verbose]
[-version] [--version]
[-W] [--no-warn] [--warn] [--fatal-warnings]
[-w] [-x]
[-Z] [@FILE]
[target-options]
[--|files ...]and then there's [target-options] which is its own whole universe. keep reading. 🌈
🔥 TARGET 🔥
okay so this is the part where she shows off. every architecture she can assemble for, and their special little flags. i'm not skipping a single one, bestie, i love you too much. 💜
⭐ Target AArch64 options
for the ARM64 girlies:
[-EB|-EL]
[-mabi=ABI]⭐ Target Alpha options
[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]⭐ Target ARC options
[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]⭐ Target ARM options
[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
-mapcs-reentrant]
[-mthumb-interwork] [-k]⭐ Target Blackfin options
[-mcpu=processor[-sirevision]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]⭐ Target BPF options
[-EL] [-EB]⭐ Target CRIS options
[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
[--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]⭐ Target C-SKY options
[-march=arch] [-mcpu=cpu]
[-EL] [-mlittle-endian] [-EB] [-mbig-endian]
[-fpic] [-pic]
[-mljump] [-mno-ljump]
[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
[-mnolrw ] [-mno-lrw]
[-melrw] [-mno-elrw]
[-mlaf ] [-mliterals-after-func]
[-mno-laf] [-mno-literals-after-func]
[-mlabr] [-mliterals-after-br]
[-mno-labr] [-mnoliterals-after-br]
[-mistack] [-mno-istack]
[-mhard-float] [-mmp] [-mcp] [-mcache]
[-msecurity] [-mtrust]
[-mdsp] [-medsp] [-mvdsp]⭐ Target D10V options
[-O]⭐ Target D30V options
[-O|-n|-N]⭐ Target EPIPHANY options
[-mepiphany|-mepiphany16]⭐ Target H8/300 options
[-h-tick-hex]⭐ Target i386 options
[--32|--x32|--64] [-n]
[-march=CPU[+EXTENSION...]] [-mtune=CPU]⭐ Target IA-64 options
[-mconstant-gp|-mauto-pic]
[-milp32|-milp64|-mlp64|-mp64]
[-mle|mbe]
[-mtune=itanium1|-mtune=itanium2]
[-munwind-check=warning|-munwind-check=error]
[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
[-x|-xexplicit] [-xauto] [-xdebug]⭐ Target IP2K options
[-mip2022|-mip2022ext]⭐ Target M32C options
[-m32c|-m16c] [-relax] [-h-tick-hex]⭐ Target M32R options
[--m32rx|--[no-]warn-explicit-parallel-conflicts|
--W[n]p]⭐ Target M680X0 options
[-l] [-m68000|-m68010|-m68020|...]⭐ Target M68HC11 options
[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branches] [--short-branches]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]⭐ Target MCORE options
[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]⭐ Target Meta options
also sneaking in MICROBLAZE on the same line, she's efficient like that:
[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
[-mlittle-endian] [-mbig-endian]⭐ Target MIPS options
okay this one is a LOT, she really said "let me cook":
[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot [-mvxworks-pic]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-mfp64] [-mgp64] [-mfpxx]
[-modd-spreg] [-mno-odd-spreg]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
[-mips64r3] [-mips64r5] [-mips64r6]
[-construct-floats] [-no-construct-floats]
[-mignore-branch-isa] [-mno-ignore-branch-isa]
[-mnan=encoding]
[-trap] [-no-break] [-break] [-no-trap]
[-mips16] [-no-mips16]
[-mmips16e2] [-mno-mips16e2]
[-mmicromips] [-mno-micromips]
[-msmartmips] [-mno-smartmips]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdsp] [-mno-dsp]
[-mdspr2] [-mno-dspr2]
[-mdspr3] [-mno-dspr3]
[-mmsa] [-mno-msa]
[-mxpa] [-mno-xpa]
[-mmt] [-mno-mt]
[-mmcu] [-mno-mcu]
[-mcrc] [-mno-crc]
[-mginv] [-mno-ginv]
[-mloongson-mmi] [-mno-loongson-mmi]
[-mloongson-cam] [-mno-loongson-cam]
[-mloongson-ext] [-mno-loongson-ext]
[-mloongson-ext2] [-mno-loongson-ext2]
[-minsn32] [-mno-insn32]
[-mfix7000] [-mno-fix7000]
[-mfix-rm7000] [-mno-fix-rm7000]
[-mfix-vr4120] [-mno-fix-vr4120]
[-mfix-vr4130] [-mno-fix-vr4130]
[-mfix-r5900] [-mno-fix-r5900]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]⭐ Target MMIX options
[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]⭐ Target NDS32 options
[-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
[-misa=isa] [-mabi=abi] [-mall-ext]
[-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
[-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
[-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
[-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
[-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
[-mb2bb]⭐ Target PDP11 options
[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]⭐ Target picoJava options
[-mb|-me]⭐ Target PowerPC options
look at this roster, she said "why not all of them":
[-a32|-a64]
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
-m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
-mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
-me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
-mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
-mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
[-many] [-maltivec|-mvsx|-mhtm|-mvle]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
[-nops=count]⭐ Target PRU options
[-link-relax]
[-mnolink-relax]
[-mno-warn-regname-label]⭐ Target RISC-V options
[-fpic|-fPIC|-fno-pic]
[-march=ISA|Profiles|Profiles_ISA]
[-mabi=ABI]
[-mlittle-endian|-mbig-endian]⭐ Target RL78 options
[-mg10]
[-m32bit-doubles|-m64bit-doubles]⭐ Target RX options
[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]⭐ Target s390 options
[-m31|-m64] [-mesa|-mzarch] [-march=CPU]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]
[-mwarn-regtype-mismatch=strict
-mwarn-regtype-mismatch=relaxed
-mwarn-regtype-mismatch=no
-mno-warn-regtype-mismatch]⭐ Target SCORE options
[-EB][-EL][-FIXDD][-NWARN]
[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
[-march=score7][-march=score3]
[-USE_R1][-KPIC][-O0][-G num][-V]⭐ Target SPARC options
[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
-Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
-Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
-Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
-Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
-Asparcvisr|-Asparc5]
[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
-xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
-xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
-xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
-xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
-xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
-bump]
[-32|-64]
[--enforce-aligned-data][--dcti-couples-detect]⭐ Target TIC54X options
[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]⭐ Target TIC6X options
[-march=arch] [-mbig-endian|-mlittle-endian]
[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
[-mpic|-mno-pic]⭐ Target TILE-Gx options
[-m32|-m64][-EB][-EL]⭐ Target Visium options
[-mtune=arch]⭐ Target Xtensa options
[--[no-]text-section-literals] [--[no-]auto-litpools]
[--[no-]absolute-literals]
[--[no-]target-align] [--[no-]longcalls]
[--[no-]transform]
[--rename-section oldname=newname]
[--[no-]trampolines]
[--abi-windowed|--abi-call0]⭐ Target Z80 options
[-march=CPU[-EXT][+EXT]]
[-local-prefix=PREFIX]
[-colonless]
[-sdcc]
[-fp-s=FORMAT]
[-fp-d=FORMAT]✨ DESCRIPTION ✨
okay bestie so here's the tea ☕ — GNU as is not just one assembler, it's literally a whole family of assemblers, like a girl group 👑. If you've ever used (or even just breathed near) the GNU assembler on one architecture, the next architecture is gonna feel super familiar, iykyk. Every version has sooo much in common with the others: object file formats, most assembler directives (we call those pseudo-ops, cute right?), and the assembler syntax itself. Consistency slay 💅
as is primarily intended to assemble the output of the GNU C compiler gcc so the linker ld can do its thing with it. That's its main character job. That said, we've genuinely tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly (no hidden lore here). That does not mean as always uses the same syntax as another assembler for the same architecture — for example, we know of several incompatible versions of 680x0 assembly language syntax. Chaos, honestly 😭
Every single time you run as, it assembles exactly one source program. One. Periodt. That source program is made up of one or more files. (And yes, standard input totally counts as a file, bestie.)
You give as a command line with zero or more input file names. Input files get read from left file name to right, like reading a group chat in order 🫶. A command-line argument (in any position) that has no special meaning is just taken to be an input file name.
If you give as no file names at all, it attempts to read one input file from standard input, which is normally your terminal. You may have to type ctl-D to tell as there's no more program to assemble. It's like saying "that's all, bestie, go off" 💖
Use -- if you need to explicitly name the standard input file in your command line. Noted, iconic behavior.
If the source is empty, as produces a small, empty object file. Tiny. Minimal. Cozy. A little empty shell 🐚
as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Here's the distinction that matters:
- Warnings report an assumption made so that
ascould keep assembling a flawed program 🌈 - Errors report a grave problem that stops the assembly 💀 (serious business, she's done)
If you're invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the -Wa) by commas. For example:
gcc -c -g -O -Wa,-alh,-L file.cThis passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain internal symbols in the symbol table). See? Communication. We love to see it 💅
Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.) nosy but make it ✨educational✨
🎀 OPTIONS 🎀
okay this is the big one, grab a snack 🍓
@file— Read command-line options from file. The options read are inserted in place of the original@fileoption. If file does not exist, or cannot be read, then the option will be treated literally, and not removed.
Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively. it's giving inception 🌀
-a[cdghilmns]— Turn on listings, in any of a variety of ways:-acomit false conditionals-adomit debugging directives-aginclude general information, likeasversion and options passed-ahinclude high-level source-alinclude assembly-aliinclude assembly with ginsn-aminclude macro expansions-anomit forms processing-asinclude symbols=fileset the name of the listing file
You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls. Combo moves, bestie 💅
--alternate— Begin in alternate macro mode. switching it up 😌--compress-debug-sections— Compress DWARF debug sections using zlib withSHF_COMPRESSEDfrom the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities 😭. Note: if compression would make a given section larger, then it is not compressed.--compress-debug-sections=none,--compress-debug-sections=zlib,--compress-debug-sections=zlib-gnu,--compress-debug-sections=zlib-gabi,--compress-debug-sections=zstd— These options control how DWARF debug sections are compressed.--compress-debug-sections=noneis equivalent to--nocompress-debug-sections.--compress-debug-sections=zliband--compress-debug-sections=zlib-gabiare equivalent to--compress-debug-sections.--compress-debug-sections=zlib-gnucompresses DWARF debug sections using the obsoleted zlib-gnu format. The debug sections are renamed to begin with.zdebug.--compress-debug-sections=zstdcompresses DWARF debug sections using zstd. Note: if compression would actually make a section larger, then it is not compressed nor renamed.--nocompress-debug-sections— Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.-D— Enable debugging in target specific backends, if supported. Otherwise ignored. Even if ignored, this option is accepted for script compatibility with calls to other assemblers. polite queen, accepts it anyway 🫶--debug-prefix-map old=new— When assembling files in directory old, record debugging information describing them as in new instead.--defsym sym=value— Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading0xindicates a hexadecimal value, and a leading0indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a.setpseudo-op.--dump-config— Displays how the assembler is configured and then exits. just a lil peek at her settings 👀--elf-stt-common=no,--elf-stt-common=yes— These options control whether the ELF assembler should generate common symbols with theSTT_COMMONtype. The default can be controlled by a configure option--enable-elf-stt-common.--emit-local-absolute— Emit even pre-defined (local) absolute symbols to the outgoing symbol table. Note that this isn't the exact opposite of--strip-local-absolute. not a perfect mirror, just vibes 🪞--emulation=name— If the assembler is configured to support multiple different target configurations then this option can be used to select the desired form.-f— "fast"---skip whitespace and comment preprocessing (assume source is compiler output). zoom zoom 🏎️-g,--gen-debug— Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a.debug_infoand.debug_linesection is only emitted when the assembly file doesn't generate one itself.--gstabs— Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.--gstabs+— Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program 💀. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time.--gdwarf-2— Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note---this option is only supported by some targets, not all of them.--gdwarf-3— This option is the same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.--gdwarf-4— This option is the same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.--gdwarf-5— This option is the same as the--gdwarf-2option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note: enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.--gdwarf-sections— Instead of creating a.debug_linesection, create a series of.debug_line.foosections where foo is the name of the corresponding code section. For example a code section called.text.funcwill have its dwarf line number information placed into a section called.debug_line.text.func. If the code section is just called.textthen debug line section will still be called just.debug_linewithout any suffix. suffix-free, minimal, iconic 🌸--gdwarf-cie-version=version— Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specified the default is version1, though some targets can modify this default. Other possible values for version are3or4.--generate-missing-build-notes=yes,--generate-missing-build-notes=no— These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the--enable-generate-build-notesconfigure option.--gsframe,--gsframe,--gsframe=no,--gsframe=yes— Create.sframesection from CFI directives. The explicit--gsframe=yesoption behaves the same as--gsframe. Generation can be suppressed with--gsframe=no. The default can be controlled by a configure option--enable-default-sframe. The current version of the emitted SFrame stack trace data isSFRAME_VERSION_3. (yes she listed--gsframetwice, she contains multitudes ✨)--gsframe-3— Generate SFrame stack trace information as per Version 3 of the specification.--hash-size N— Ignored. Supported for command line compatibility with other assemblers. she's just being nice okay 😭--help— Print a summary of the command-line options and exit. always here to help, bestie 🫶--target-help— spills ALL the tea on every target-specific option there is, then dips. That's it, that's the whole job. ✨--info— bestie, do NOT hold back the informational messages. Let them speak. 🗣️--no-info— okay actually, hush. Suppress the informational messages. 🤫-Idir — adds the directory dir to the search list for.includedirectives. So when your.includegoes looking for its little files, it knows where to peek. 🫶-J— not me ignoring signed overflow. Don't warn about it. 💅-K— issue warnings when difference tables get altered for long displacements. It's giving "heads up, things shifted." ⚠️-L,--keep-locals— keeps internal symbols in the symbol table. These little guys start with system-specific local label prefixes — typically.Lon ELF systems, orLon traditionala.outsystems. Precious. We keep them. 🥺- *
--listing-lhs-width=number* — sets the max width, in words, of the output data column for an assembler listing to number. Yes, words, not bytes, don't come for me. - *
--listing-lhs-width2=number* — same idea but for the continuation lines in an assembler listing. Max width of the output data column, in words, set to number. The sequel. 🎬 - *
--listing-rhs-width=number* — sets the max width of an input source line, as shown in a listing, to number bytes. This one IS bytes. Slay, units. 📏 - *
--listing-cont-lines=number* — sets the max number of lines printed in a listing for a single line of input to number + 1. Note the lil +1, it's iconic of them. ✨ --multibyte-handling=allow/--multibyte-handling=warn/--multibyte-handling=warn-sym-only/--multibyte-handling=warn_sym_only— this whole squad controls how the assembler deals with multibyte characters in the input. The default — which you can restore by passing theallowargument — is to allow those characters with zero complaints, live and let live. Passingwarnmakes the assembler generate a warning message every single time any multibyte character shows up. Passingwarn-sym-onlyonly generates a warning when a symbol gets DEFINED with a name containing multibyte characters. (And heads up: references to undefined symbols will not generate a warning.) 🙈--no-pad-sections— stops the assembler from padding the ends of output sections to the alignment of that section. The default is to pad the sections, but bestie… that can waste space, and some targets have tight memory constraints where that space is genuinely needed. Do with that what you will. 💀- *
-o*objfile — names the object-file output fromasobjfile. The ✨name✨ of the thing. -R— folds the data section into the text section. Merging era. 🫂--reduce-memory-overheads— Ignored. It's supported for compatibility with tools that pass the same option to both the assembler and the linker. It's just there to be polite. 🙃--reloc-section-sym=all/--reloc-section-sym=internal/--reloc-section-sym=none— these control whether relocations referencing local binding symbols get adjusted to use section symbols instead. With"all"(the default), relocations against ALL eligible local binding symbols are converted. With"internal", only relocations against internal labels — symbols matching the".L"prefix — get converted. With"none", no such conversions happen at all. Pick your fighter. 👑--scfi=experimental— this one controls whether the assembler should synthesize CFI for hand-written input. If the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning. Note that--scfi=experimentalis not intended to be used for compiler-generated code, including inline assembly. This experimental support is work in progress. Only System V AMD64 ABI is supported.
Each input function in assembly must begin with the .type directive, and should ideally be closed off using a .size directive. When using SCFI, each .type directive prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry). This implies that with each .type directive, a previous block of instructions, if any, is finalised as a distinct FDE.
bestie it literally says "experimental" in the name, tread carefully 🧪
--sectname-subst— honors substitution sequences in section names. Respect the substitutions. 💅--size-check=error/--size-check=warning— issue an error or a warning for an invalid ELF.sizedirective. You choose the energy: 🔥 or ⚠️.--statistics— prints the maximum space (in bytes) and total time (in seconds) used by assembly. Receipts. 🧾--strip-local-absolute— removes local absolute symbols from the outgoing symbol table. Gone, blocked, deleted. 🚫-v,--verbose— prints theasversion. Hi, hello, who are you. 👋--version,-version— prints theasversion and exits. Same info, but it leaves the chat immediately. 🚪-W,--no-warn— suppress warning messages. Silence is golden. 🤐--warn— don't suppress warning messages, and don't treat them as errors either. Let them be heard, but let them be free. 🌈--fatal-warnings— treat warnings as errors. Yikes, suddenly everything matters. 💀-w— Ignored.-x— Ignored.-Z— generate an object file even after errors. Bold. Living dangerously. 🔥- *
--*files ... — standard input, or source files to assemble. The classics. The main characters. 👑
The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). ✨
-EB— this option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.-EL— this option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.- *
-mabi=abi* — specify which ABI the source code uses. The recognized arguments are:"ilp32"and"lp64", which decide the generated object file in ELF32 and ELF64 format respectively. The default is"lp64". -mcpu=processor[+extension...]— this option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized:"cortex-a34","cortex-a35","cortex-a53","cortex-a55","cortex-a57","cortex-a65","cortex-a65ae","cortex-a72","cortex-a73","cortex-a75","cortex-a76","cortex-a76ae","cortex-a77","cortex-a78","cortex-a78ae","cortex-a78c","cortex-a510","cortex-a520","cortex-a710","cortex-a720","ares","exynos-m1","falkor","neoverse-n1","neoverse-n2","neoverse-e1","neoverse-v1","qdf24xx","saphira","thunderx","vulcan","xgene1""xgene2","cortex-r82","cortex-x1","cortex-x2","cortex-x3", and"cortex-x4". The special name"all"may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions.
In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.
If some implementations of a particular processor can have an extension, then then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions.
-march=architecture[+extension...]— this option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized:"armv8-a","armv8.1-a","armv8.2-a","armv8.3-a","armv8.4-a""armv8.5-a","armv8.6-a","armv8.7-a","armv8.8-a","armv8.9-a","armv8-r","armv9-a","armv9.1-a","armv9.2-a","armv9.3-a","armv9.4-a"and"armv9.5-a".
If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assembler will default to -mcpu=all.
The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu, extensions are not always enabled by default.
-mbig-obj— on PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. Big object energy. 🐘-mverbose-error— this option enables verbose error messages for AArch64 gas. This option is enabled by default.-mno-verbose-error— this option disables verbose error messages in AArch64 gas.-menable-sysreg-checking— this option enables error messages that are issued if an attempt is made to assemble a system register access which will not execute on the target architecture.
The following options are available when as is configured for an Alpha processor. 🦋
-mcpu— this option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the.archdirective.
The following processor names are recognized: 21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6", "ev67", "ev68". The special name "all" may be used to allow the assembler to accept instructions valid for any Alpha processor.
In order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. "ev4") do not.
-mdebug/-no-mdebug— enables or disables the generation of.mdebugencapsulation for stabs directives and procedure descriptors. The default is to automatically enable.mdebugwhen the first stabs directive is seen.-relax— this option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications.-replace/-noreplace— enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets and-replaceis the default. See section 1.4.1 of the OpenVMS Linker Utility Manual.-g— this option is used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect.-Gsize — a local common symbol larger than size is placed in.bss, while smaller symbols are placed in.sbss. Size-based sorting, we love to see it. 📊-F/-32addr— these options are ignored for backward compatibility. Ancient artifacts. 🏺
The following options are available when as is configured for an ARC processor.
- *
-mcpu=cpu* — this option selects the core processor variant. Simple as that. 💅 -EB|-EL— select either big-endian (-EB) or little-endian (-EL) output.-mcode-density— enable Code Density extension instructions. Compact queen. 👑
💖 ARM, bestie 💖
The following options are available when as is configured for the ARM processor family. ARM girlies, this one's for you ✨
-mcpu=processor[+extension...]— tells the assembler which ARM processor variant is the target. that's the whole job 🫶-march=architecture[+extension...]— picks which ARM architecture variant the target is using.-mfpu=floating-point-format— selects which Floating Point architecture is the target. yes, floats have architecture now 💅-mfloat-abi=abi— selects which floating point ABI is in use.-mthumb— enables Thumb only instruction decoding. curiosity: no ARM mixed in, just Thumb, periodt.-mapcs-32|-mapcs-26|-mapcs-float|-mapcs-reentrant— selects which procedure calling convention is in use. pick your fighter 🎀-EB|-EL— select either big-endian (-EB) or little-endian (-EL) output. endian girlies stay winning.-mthumb-interwork— specifies that the code has been generated with interworking between Thumb and ARM code in mind. it's giving bilingual 👑-mccs— turns on CodeComposer Studio assembly syntax compatibility mode.-k— specifies that PIC code has been generated.
🖤 Blackfin 🖤
The following options are available when as is configured for the Blackfin processor family.
-mcpu=processor[-sirevision]— this option specifies the target processor. the optional sirevision is not used in assembler. it's literally just vibing there so that GCC can easily pass down its-mcpu=option. lowkey iconic. the assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor — so no cap, don't try it 🙈
The following processor names are recognized: bf504, bf506, bf512, bf514, bf516, bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf535 (not implemented yet), bf536, bf537, bf538, bf539, bf542, bf542m, bf544, bf544m, bf547, bf547m, bf548, bf548m, bf549, bf549m, bf561, and bf592. 💀 that's a lot of bfs, and yes bf535 is not implemented yet, we said what we said.
-mfdpic— assemble for the FDPIC ABI.-mno-fdpic,-mnopic— disable-mfdpic. bye felicia 👋
🦋 Linux kernel BPF 🦋
The following options are available when as is configured for the Linux kernel BPF processor family.
@chapter BPF Dependent Features
okay bestie yes that's a raw texinfo artifact just sitting in the source. we don't question it, we just treasure it 🎀
BPF Options
-EB— this option specifies that the assembler should emit big-endian eBPF.-EL— this option specifies that the assembler should emit little-endian eBPF.-mdialect=dialect— this option specifies the assembly language dialect to recognize while assembling. the assembler supportsnormalandpseudoc. 💅-misa-spec=spec— this option specifies the version of the BPF instruction set to use when assembling. the BPF ISA versions supported arev1v2,v3andv4.
the value xbpf can be specified to recognize extra instructions that are used by GCC for testing purposes. but beware, bestie — this is not valid BPF. it's giving "for science only" 🔥
-mno-relax— this option tells the assembler to not relax instructions.
Note that if no endianness option is specified in the command line, the host endianness is used. also: see the info pages for documentation of the CRIS-specific options. ✨
🌸 C-SKY 🌸
The following options are available when as is configured for the C-SKY processor family.
-march=archname— assemble for architecture archname. the--helpoption lists valid values for archname.-mcpu=cpuname— assemble for architecture cpuname. the--helpoption lists valid values for cpuname. (yes, both of them point you at--help, go look 👀)-EL,-mlittle-endian— generate little-endian output.-EB,-mbig-endian— generate big-endian output.-fpic,-pic— generate position-independent code.-mljump,-mno-ljump— enable/disable transformation of the short branch instructionsjbf,jbt, andjbrtojmpi. this option is for V2 processors only. it is ignored on CK801 and CK802 targets, which do not support thejmpiinstruction, and is enabled by default for other processors.-mbranch-stub,-mno-branch-stub— pass throughR_CKCORE_PCREL_IMM26BY2relocations forbsrinstructions to the linker.
this option is only available for bare-metal C-SKY V2 ELF targets, where it is enabled by default. it cannot be used in code that will be dynamically linked against shared libraries. ⚠️
-force2bsr,-mforce2bsr,-no-force2bsr,-mno-force2bsr— enable/disable transformation ofjbsrinstructions tobsr. this option is always enabled (and-mno-force2bsris ignored) for CK801/CK802 targets. it is also always enabled when-mbranch-stubis in effect. no takesies-backsies 🫶-jsri2bsr,-mjsri2bsr,-no-jsri2bsr,-mno-jsri2bsr— enable/disable transformation ofjsriinstructions tobsr. this option is enabled by default.-mnolrw,-mno-lrw— enable/disable transformation oflrwinstructions into amovih/oripair.-melrw,-mno-elrw— enable/disable extendedlrwinstructions. this option is enabled by default for CK800-series processors.-mlaf,-mliterals-after-func,-mno-laf,-mno-literals-after-func— enable/disable placement of literal pools after each function.-mlabr,-mliterals-after-br,-mno-labr,-mnoliterals-after-br— enable/disable placement of literal pools after unconditional branches. this option is enabled by default.-mistack,-mno-istack— enable/disable interrupt stack instructions. this option is enabled by default on CK801, CK802, and CK802 processors.
The following options explicitly enable certain optional instructions. These features are also enabled implicitly by using -mcpu= to specify a processor that supports it. ✨
-mhard-float— enable hard float instructions.-mmp— enable multiprocessor instructions.-mcp— enable coprocessor instructions.-mcache— enable cache prefetch instruction.-msecurity— enable C-SKY security instructions.-mtrust— enable C-SKY trust instructions.-mdsp— enable DSP instructions.-medsp— enable enhanced DSP instructions.-mvdsp— enable vector DSP instructions.
🧚 Epiphany 🧚
The following options are available when as is configured for an Epiphany processor.
-mepiphany— specifies that the both 32 and 16 bit instructions are allowed. this is the default behavior. main character energy, honestly 👑-mepiphany16— restricts the permitted instructions to just the 16 bit set. minimalist queen 🎀
🍓 H8/300 🍓
The following options are available when as is configured for an H8/300 processor.
@chapter H8/300 Dependent Features
Options
The Renesas H8/300 version of as has one machine-dependent option:
-h-tick-hex— supportH'00style hex constants in addition to0x00style. (and then two more showed up, we love a surprise ✨)-mach=name— sets the H8300 machine variant. The following machine names are recognised:h8300h,h8300hn,h8300s,h8300sn,h8300sxandh8300sxn.
🔥 i386 🔥
The following options are available when as is configured for an i386 processor.
--32|--x32|--64— select the word size, either 32 bits or 64 bits.--32implies Intel i386 architecture, while--x32and--64imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.
These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform). ⚠️ read that twice bestie
-n— by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such asleal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.--divide— On SVR4-derived platforms, the character/is treated as a comment character, which means that it cannot be used in expressions. The--divideoption turns/into a normal character. This does not disable/at the beginning of a line starting a comment, or affect using#for starting a comment. 💅-march=CPU[+EXTENSION...]— This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized:i8086,i186,i286,i386,i486,i586,i686,pentium,pentiumpro,pentiumii,pentiumiii,pentium4,prescott,nocona,core,core2,corei7,iamcu,k6,k6_2,athlon,opteron,k8,amdfam10,bdver1,bdver2,bdver3,bdver4,znver1,znver2,znver3,znver4,znver5,znver6,btver1,btver2,generic32andgeneric64. 😭 an absolute wall of names and we included every single one, no cap
okay so on top of the basic instruction set, the assembler can be told to accept alllll kinds of extension mnemonics. like for example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. slay!! 🎀
the extensions currently supported are: 8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, avx512_bmm, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb, avx10.1, avx10.1/512, avx10.1/256, avx10.1/128, user_msr, msr_imm, apx_f, apx_nci, apx_ndd, apx_nf, apx_nci_ndd_nf, avx10.2, avx10.2/512, avx10.2/256, avx10.2/128, movrs, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8 amx_movrs, amx_avx512, amx_tile, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, snp, invlpgb, tlbsync, rmpquery, rmpread, svme, gmism2, gmiccs, padlockrng2, padlockphe2, padlockxmodx and padlock.
(ngl between amx_fp8 and amx_movrs there's no comma in the source and i am not the one fixing it 💀 not my job, i just report.)
Note that these extension mnemonics can be prefixed with no to revoke the respective (and any dependent) functionality. 🔥
Note further that the suffixes permitted on -march=avx10.<N> enforce a vector length restriction — i.e. despite these otherwise being "enabling" options, using these suffixes will disable all insns with wider vector or mask register operands. yeah bestie, they're doing the opposite of what the name says. it's giving chaos but okay. 😭
When the .arch directive is used with -march, the .arch directive will take precedent.
-mtune=CPU— picks a processor to optimize for. When you use it together with the-marchoption, only instructions of the processor specified by the-marchoption will be generated.
Valid CPU values are identical to the processor list of -march=CPU. same menu, different seat. 🪑
-moperand-check=none-moperand-check=warning-moperand-check=error— these control whether the assembler checks certain instruction operands or operand combinations. an example is instructions where the operand size can't be inferred from its operands and also hasn't been specified by way of an instruction suffix.-moperand-check=nonemakes the assembler not perform these checks.-moperand-check=warningmakes it throw a warning when the checks fail — this is the default.-moperand-check=errormakes it throw an error when the checks fail.
-msse2avx— tells the assembler it should encode SSE instructions with a VEX prefix, which requires AVX to be available. SSE instructions using extended GPRs will be encoded with EVEX prefix, which requires AVX512 or AVX10 to be available.-muse-unaligned-vector-move— tells the assembler to encode aligned vector move as unaligned vector move. living dangerously, love that for you 💅-msse-check=none-msse-check=warning-msse-check=error— these control whether the assembler checks SSE instructions.-msse-check=nonemakes it not check SSE instructions — this is the default.-msse-check=warningmakes it issue a warning for any SSE instruction.-msse-check=errormakes it issue an error for any SSE instruction.
-mavxscalar=128-mavxscalar=256— these control how the assembler encodes scalar AVX instructions.-mavxscalar=128encodes scalar AVX instructions with 128bit vector length, which is the default.-mavxscalar=256encodes them with 256bit vector length.
⚠️ WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. bestie i am BEGGING you, not in prod. 🙈
-mvexwig=0-mvexwig=1— these control how the assembler encodes VEX.W-ignored (WIG) VEX instructions.-mvexwig=0encodes WIG VEX instructions withvex.w = 0, which is the default.-mvexwig=1encodes WIG EVEX instructions withvex.w = 1.
⚠️ WARNING: Don't use this for production code — due to CPU errata the resulting code may not work on certain models. (again?? again. 😭)
-mevexlig=128-mevexlig=256-mevexlig=512— these control how the assembler encodes length-ignored (LIG) EVEX instructions.-mevexlig=128encodes LIG EVEX instructions with 128bit vector length, which is the default.-mevexlig=256and-mevexlig=512encode LIG EVEX instructions with 256bit and 512bit vector length, respectively.-mevexwig=0-mevexwig=1— these control how the assembler encodes w-ignored (WIG) EVEX instructions.-mevexwig=0encodes WIG EVEX instructions withevex.w = 0, which is the default.-mevexwig=1encodes WIG EVEX instructions withevex.w = 1.-mmnemonic=att-mmnemonic=intel— picks the instruction mnemonic used for matching instructions. The.att_mnemonicand.intel_mnemonicdirectives will take precedent. 👑-msyntax=att-msyntax=intel— picks the instruction syntax used when processing instructions. The.att_syntaxand.intel_syntaxdirectives will take precedent.-mnaked-reg— registers don't require a%prefix. nakey registers ✨. The.att_syntaxand.intel_syntaxdirectives will take precedent.-madd-bnd-prefix— forces the assembler to add BND prefix to all branches, even if the prefix wasn't explicitly specified in the source code. all of them. every single one. 💀-mno-shared— on ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The-msharedoption tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. the resulting code is slightly bigger. this option only affects the handling of branch instructions.-mbig-obj— on PE/COFF target this forces the use of big object file format, which allows more than 32768 sections. go big or go home. 👑-momit-lock-prefix=no-momit-lock-prefix=yes— these control how the assembler encodes the lock prefix. this one is a workaround for processors that fail on lock prefix.
⚠️ this option can only be safely used with single-core, single-thread computers. like, seriously.
-momit-lock-prefix=yes will omit all lock prefixes. -momit-lock-prefix=no will encode lock prefix as usual, which is the default.
-mfence-as-lock-add=no-mfence-as-lock-add=yes— these control how the assembler encodeslfence,mfenceandsfence.-mfence-as-lock-add=yeswill encodelfence,mfenceandsfenceaslock addl $0x0, (%rsp)in 64-bit mode andlock addl $0x0, (%esp)in 32-bit mode.-mfence-as-lock-add=nowill encode them as usual, which is the default.-mrelax-relocations=no-mrelax-relocations=yes— these control whether the assembler generates relax relocations:R_386_GOT32Xin 32-bit mode, orR_X86_64_GOTPCRELXandR_X86_64_REX_GOTPCRELXin 64-bit mode.-mrelax-relocations=yeswill generate relax relocations.-mrelax-relocations=nowill not generate relax relocations.-mtls-check=no-mtls-check=yes— these control whether the assembler checks tls relocation.-mtls-check=yeswill check tls relocation.-mtls-check=nowill not check tls relocation. the default can be controlled by a configure option--enable-x86-tls-check.-malign-branch-boundary=NUM— controls how the assembler aligns branches with segment prefixes or NOP.NUMmust be a power of 2. it should be0or no less than16. branches will be aligned withinNUMbyte boundary.-malign-branch-boundary=0, which is the default, doesn't align branches.-malign-branch=TYPE[+TYPE...]— specifies the types of branches to align.TYPEis a combination of:jcc, which aligns conditional jumpsfused, which aligns fused conditional jumpsjmp, which aligns unconditional jumpscall, which aligns callsret, which aligns retsindirect, which aligns indirect jumps and calls
The default is -malign-branch=jcc+fused+jmp. 🌸
-malign-branch-prefix-size=NUM— specifies the maximum number of prefixes on an instruction to align branches.NUMshould be between0and5. the defaultNUMis5.-mbranches-within-32B-boundaries— aligns conditional jumps, fused conditional jumps and unconditional jumps within 32 byte boundary with up to 5 segment prefixes on an instruction. it is equivalent to:
-malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5The default doesn't align branches.
-mlfence-after-load=no-mlfence-after-load=yes— these control whether the assembler generateslfenceafter load instructions.-mlfence-after-load=yeswill generatelfence.-mlfence-after-load=nowill not generatelfence, which is the default.
-mlfence-before-indirect-branch=none,-mlfence-before-indirect-branch=all,-mlfence-before-indirect-branch=register,-mlfence-before-indirect-branch=memory— bestie these four control whether the assembler drops an lfence before indirect near branch instructions, and each flavor hits different 🙈=all→ generateslfencebefore an indirect near branch via register, AND issues a warning before an indirect near branch via memory. Sneaky extra: it implicitly sets-mlfence-before-ret=shlwhen there's no explicit-mlfence-before-ret=hanging around.=register→ generateslfencebefore indirect near branch via register. That's it, that's the whole job 💅=memory→ issues a warning before indirect near branch via memory.=none→ nolfence, no warning. This is the default, and it's giving "do nothing, say nothing" energy.
⚠️ Important heads-up bestie:lfencewill not be generated before an indirect near branch via register when-mlfence-after-load=yesis set, because in that case thelfencegets generated after loading the branch target register. They can't both have main character energy 😭
-mlfence-before-ret=none,-mlfence-before-ret=shl,-mlfence-before-ret=or,-mlfence-before-ret=yes,-mlfence-before-ret=not— do we generatelfencebeforeretor not, that is literally the question 🌸=or→ generates anorinstruction withlfence.=shl/=yes→ generates ashlinstruction withlfence(yes bestie, those two do the Same Thing, iconic).=not→ generates anotinstruction withlfence.=none→ does not generatelfence. The default. Lowkey the chillest option 🧚
-mx86-used-note=no,-mx86-used-note=yes— should the assembler generate theGNU_PROPERTY_X86_ISA_1_USEDandGNU_PROPERTY_X86_FEATURE_2_USEDGNU property notes? That's the vibe check ✨ The default is controlled by the--enable-x86-used-noteconfigure option.-mevexrcig=rne,-mevexrcig=rd,-mevexrcig=ru,-mevexrcig=rz— how should the assembler encode SAE-only EVEX instructions? Let's discuss 🔥=rne→ encodes the RC bits of the EVEX instruction with00. This is the default.=rd,=ru,=rz→ encode SAE-only EVEX instructions with01,10, and11RC bits, respectively. They understood the assignment 💅
-mamd64,-mintel64— tells the assembler to accept only AMD64 or Intel64 ISA in 64-bit mode. The default is to accept common, Intel64-only AND AMD64 ISAs, so this is you narrowing the guest list 🎀-O0,-O,-O1,-O2,-Os— optimize instruction encoding for a smaller instruction size. Let's break it down because this part is a whole saga 👑
-O and -O1 encode:
- 64-bit register load instructions with 64-bit immediate → as 32-bit register load instructions with 31-bit or 32-bit immediates
- 64-bit register clearing instructions → as 32-bit register clearing instructions
- 256-bit/512-bit VEX/EVEX vector register clearing instructions → as 128-bit VEX vector register clearing instructions
- 128-bit/256-bit EVEX vector register load/store instructions → as VEX vector register load/store instructions
- 128-bit/256-bit EVEX packed integer logical instructions → as 128-bit/256-bit VEX packed integer logical
-O2 includes all the -O1 optimization plus it encodes 256-bit/512-bit EVEX vector register clearing instructions as 128-bit EVEX vector register clearing instructions. And in 64-bit mode, VEX encoded instructions with commutative source operands will also have their source operands swapped if that allows using the 2-byte VEX prefix form instead of the 3-byte one. Certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST. She's efficient, she's ruthless, she's -O2 💀
-Os includes all the -O2 optimization plus it encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate.
-O0 turns off this optimization. Sometimes the answer is just "no" 🫶
The following options are available when as is configured for the Ubicom IP2K series. 🦋
-mip2022ext— the extended IP2022 instructions are allowed. Go off ✨-mip2022— restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. Back to basics bestie.
The following options are available when as is configured for the Renesas M32C and M16C processors. 🌸
-m32c— assemble M32C instructions.-m16c— assemble M16C instructions (this one is the default).-relax— enable support for link-time relaxations. Chill vibes, let the linker handle it 🧚-h-tick-hex— supportH'00style hex constants in addition to0x00style. Two aesthetics, one assembler 💅
The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series. 🎀
--m32rx— specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.--warn-explicit-parallel-conflictsor--Wp— produce warning messages when questionable parallel constructs are encountered. Red flag detector: ON 🔥--no-warn-explicit-parallel-conflictsor--Wnp— do not produce warning messages when questionable parallel constructs are encountered. Ignorance is bliss, live your truth 🙈
The following options are available when as is configured for the Motorola 68000 series. ⭐
-l— shorten references to undefined symbols, to one word instead of two. Short and sweet, periodt.-m68000,-m68008,-m68010,-m68020,-m68030,-m68040,-m68060,-m68302,-m68331,-m68332,-m68333,-m68340,-mcpu32,-m5200— specify what processor in the 68000 family is the target. The default is normally the68020, but this can be changed at configuration time. Pick your fighter 🥊-m68881,-m68882,-mno-68881,-mno-68882— does the target machine have a floating-point coprocessor or not? The default is to assume a coprocessor for68020,68030, andcpu32. And bestie, plot twist: although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor. Iconic workaround energy ✨-m68851,-mno-68851— does the target machine have a memory-management unit coprocessor or not? The default is to assume an MMU for68020and up.
For details about the PDP-11 machine dependent features options, see PDP-11-Options. 🫶
-mpic,-mno-pic— generate position-independent (or position-dependent) code. The default is-mpic.-mall,-mall-extensions— enable all instruction set extensions. This is the default. All of them. Every single one. Slay 💅-mno-extensions— disable all instruction set extensions. None of them. Zero. 💀-mextension,-mno-extension— enable (or disable) a particular instruction set extension. Choose your fave.-mcpu— enable the instruction set extensions supported by a particular CPU, and disable all other extensions. Monogamy but for instruction sets 😭-mmachine— enable the instruction set extensions supported by a particular machine model, and disable all other extensions.
The following options are available when as is configured for a picoJava processor. 🌈
-mb— generate "big endian" format output.-ml— generate "little endian" format output.
The following options are available when as is configured for a PRU processor. 🍓
-mlink-relax— assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LD would shorten the LDI32 instruction to a single LDI. In such a case,aswill output DIFF relocations for diff expressions.-mno-link-relax— assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted. No optimizations, no relocations, no drama 🙈-mno-warn-regname-label— do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off. (C compilers stay doing the most.)- *
-mcore-revision=revision* — this option specifies the PRU core revision to assemble for. The following revisions are recognized:"V1","V2","V3"and"V4". The assembler defaults to"V3". Bestie we're going with V3 unless you say otherwise 💜
The following options are available when as is configured for a MIPS processor. 👑
-Gnum — sets the largest size of an object that can be referenced implicitly with the"gp"register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is8.-EB— generate "big endian" format output.-EL— generate "little endian" format output.-mips1,-mips2,-mips3,-mips4,-mips5,-mips32,-mips32r2,-mips32r3,-mips32r5,-mips32r6,-mips64,-mips64r2,-mips64r3,-mips64r5,-mips64r6— generate code for a particular MIPS Instruction Set Architecture level. The alias lore:-mips1is an alias for-march=r3000,-mips2is an alias for-march=r6000,-mips3is an alias for-march=r4000and-mips4is an alias for-march=r8000. Then-mips5,-mips32,-mips32r2,-mips32r3,-mips32r5,-mips32r6,-mips64,-mips64r2,-mips64r3,-mips64r5, and-mips64r6correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. So many releases, so much range 🌟-march=cpu — generate code for a particular MIPS CPU.-mtune=cpu — schedule and tune for a particular MIPS CPU.-mfix7000,-mno-fix7000— cause nops to be inserted if the read of the destination register of anmfhiormfloinstruction occurs in the following two instructions.-mfix-rm7000,-mno-fix-rm7000— cause nops to be inserted if admultordmultuinstruction is followed by a load instruction.-mfix-r5900,-mno-fix-r5900— do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer, and always schedule a"nop"instruction there instead. Why so dramatic? Because the short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. Hardware said "I'll do it my way" 💀-mdebug,-no-mdebug— cause stabs-style debugging output to go into an ECOFF-style.mdebugsection instead of the standard ELF.stabssections.-mpdr,-mno-pdr— control generation of".pdr"sections.-mgp32,-mfp32— the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times.-mgp32controls the size of general-purpose registers and-mfp32controls the size of floating-point registers. Locked in at 32 bits, no take-backs 💅-mgp64,-mfp64— so normally the register sizes get figured out from the ISA and ABI, right? But these two flags force a specific group of registers to just be 64 bits wide, always, no negotiating.-mgp64is the one that controls the size of the general-purpose registers, and-mfp64handles the size of the floating-point registers. Teamwork, honestly. ✨-mfpxx— same deal, register sizes normally come from the ISA and ABI, but if you pair this flag with-mabi=32it enables an ABI variant that'll operate correctly with floating-point registers that are either 32 or 64 bits wide. Flexible queen energy. 💅-modd-spreg,-mno-odd-spreg— turns on the use of floating-point operations on odd-numbered single-precision registers when the ISA supports it. Heads up tho:-mfpxximplies-mno-odd-spreg, and otherwise the default is-modd-spreg.-mips16,-no-mips16— generates code for the MIPS 16 processor. This is literally equivalent to putting.module mips16at the start of the assembly file.-no-mips16turns it back off.-mmips16e2,-mno-mips16e2— enables the use of MIPS16e2 instructions while you're in MIPS16 mode. Same vibe: equivalent to putting.module mips16e2at the start of the assembly file.-mno-mips16e2turns this option off.-mmicromips,-mno-micromips— generates code for the microMIPS processor. Equivalent to putting.module micromipsat the start of the assembly file.-mno-micromipsturns this option off, and that is equivalent to putting.module nomicromipsat the start of the assembly file.-msmartmips,-mno-smartmips— enables the SmartMIPS extension to the MIPS32 instruction set. Yes, it's also equivalent to putting.module smartmipsat the start of the assembly file.-mno-smartmipsturns it off.-mips3d,-no-mips3d— generates code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions.-no-mips3dturns it off.-mdmx,-no-mdmx— generates code for the MDMX Application Specific Extension, which means the assembler will accept MDMX instructions.-no-mdmxturns it off.-mdsp,-mno-dsp— generates code for the DSP Release 1 Application Specific Extension. Tells the assembler to accept DSP Release 1 instructions.-mno-dspturns it off.-mdspr2,-mno-dspr2— generates code for the DSP Release 2 Application Specific Extension. Sneaky detail: this option implies-mdsp. It tells the assembler to accept DSP Release 2 instructions.-mno-dspr2turns it off.-mdspr3,-mno-dspr3— generates code for the DSP Release 3 Application Specific Extension. And this one implies both-mdspand-mdspr2— it's stacking, bestie. Tells the assembler to accept DSP Release 3 instructions.-mno-dspr3turns it off.-mmsa,-mno-msa— generates code for the MIPS SIMD Architecture Extension. Tells the assembler to accept MSA instructions.-mno-msaturns it off.-mxpa,-mno-xpa— generates code for the MIPS eXtended Physical Address (XPA) Extension. Tells the assembler to accept XPA instructions.-mno-xpaturns it off.-mmt,-mno-mt— generates code for the MT Application Specific Extension. Tells the assembler to accept MT instructions.-mno-mtturns it off.-mmcu,-mno-mcu— generates code for the MCU Application Specific Extension. Tells the assembler to accept MCU instructions.-mno-mcuturns it off.-mcrc,-mno-crc— generates code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. Tells the assembler to accept CRC instructions.-mno-crcturns it off.-mginv,-mno-ginv— generates code for the Global INValidate (GINV) Application Specific Extension. Tells the assembler to accept GINV instructions.-mno-ginvturns it off.-mloongson-mmi,-mno-loongson-mmi— generates code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. Tells the assembler to accept MMI instructions.-mno-loongson-mmiturns it off.-mloongson-cam,-mno-loongson-cam— generates code for the Loongson Content Address Memory (CAM) instructions. Tells the assembler to accept Loongson CAM instructions.-mno-loongson-camturns it off.-mloongson-ext,-mno-loongson-ext— generates code for the Loongson EXTensions (EXT) instructions. Tells the assembler to accept Loongson EXT instructions.-mno-loongson-extturns it off.-mloongson-ext2,-mno-loongson-ext2— generates code for the Loongson EXTensions R2 (EXT2) instructions. This option implies-mloongson-ext. Tells the assembler to accept Loongson EXT2 instructions.-mno-loongson-ext2turns it off.-minsn32,-mno-insn32— only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions, periodt. Equivalent to putting.set insn32at the start of the assembly file.-mno-insn32turns this option off, and that's equivalent to putting.set noinsn32at the start of the assembly file. By default-mno-insn32is selected, which allows all instructions to be used. 🫶--construct-floats,--no-construct-floats— so--no-construct-floatsdisables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default--construct-floatsis selected, allowing construction of these floating point constants.--relax-branch,--no-relax-branch—--relax-branchenables the relaxation of out-of-range branches. By default--no-relax-branchis selected, which causes any out-of-range branches to produce an error. 🚨-mignore-branch-isa,-mno-ignore-branch-isa— ignore branch checks for invalid transitions between ISA modes. Okay so the semantics of branches doesn't provide for an ISA mode switch, which means in most cases the ISA mode a branch was encoded for has to be the same as the ISA mode of the branch's target label. Because of that, GAS has checks implemented that verify during branch assembly that the two ISA modes match.-mignore-branch-isadisables those checks. By default-mno-ignore-branch-isais selected, causing any invalid branch that requires a transition between ISA modes to produce an error.-mnan=encoding — picks between the IEEE 754-2008 NaN encoding format (-mnan=2008) or the legacy one (-mnan=legacy). The legacy one is the default.--emulation=name — okay so this option used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. But MIPS ECOFF support was removed in GAS 2.24 👋, so the option does basically nothing useful now. It's just being kept around for backwards compatibility.
The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are the preferred options now instead.
-nocpp—asliterally ignores this option. It's accepted for compatibility with the native tools. That's it, that's the whole story. 💀--trap,--no-trap,--break,--no-break— these control how to deal with multiplication overflow and division by zero.--trapor--no-break(they're synonyms) take a trap exception — and note that these only work for Instruction Set Architecture level 2 and higher.--breakor--no-trap(also synonyms, and also the default) take a break exception.-n— when this option is used,aswill issue a warning every time it generates a nop instruction from a macro.
The following options are available when as is configured for a LoongArch processor.
-fpic,-fPIC— generate position-independent code-fno-pic— don't generate position-independent code (default)
The following options are available when as is configured for a Meta processor.
-mcpu=metac11— generate code for Meta 1.1.-mcpu=metac12— generate code for Meta 1.2.-mcpu=metac21— generate code for Meta 2.1.-mfpu=metac21— allow code to use FPU hardware of Meta 2.1.
See the info pages for documentation of the MMIX-specific options.
The following options are available when as is configured for a NDS32 processor.
-O1— optimize for performance.-Os— optimize for space.-EL— produce little endian data output.-EB— produce little endian data output.-mpic— generate PIC.-mno-fp-as-gp-relax— suppress fp-as-gp relaxation for this file.-mb2bb-relax— back-to-back branch optimization.-mno-all-relax— suppress all relaxation for this file.-march=<arch name> — assemble for architecture <arch name> which could bev3,v3j,v3m,v3f,v3s,v2,v2j,v2f,v2s.-mbaseline=<baseline> — assemble for baseline <baseline> which could bev2,v3,v3m.-mfpu-freg=FREG— specify a FPU configuration.
0 8 SP / 4 DP registers
1 16 SP / 8 DP registers
2 32 SP / 16 DP registers
3 32 SP / 32 DP registers-mabi=abi — specify a abi version, <abi> could bev1,v2,v2fp,v2fpp.-m[no-]mac— enable/disable Multiply instructions support.-m[no-]div— enable/disable Divide instructions support.-m[no-]16bit-ext— enable/disable 16-bit extension-m[no-]dx-regs— enable/disable d0/d1 registers-m[no-]perf-ext— enable/disable Performance extension-m[no-]perf2-ext— enable/disable Performance extension 2-m[no-]string-ext— enable/disable String extension-m[no-]reduced-regs— enable/disable Reduced Register configuration (GPR16) option-m[no-]audio-isa-ext— enable/disable AUDIO ISA extension-m[no-]fpu-sp-ext— enable/disable FPU SP extension-m[no-]fpu-dp-ext— enable/disable FPU DP extension-m[no-]fpu-fma— enable/disable FPU fused-multiply-add instructions-mall-ext— turn on all extensions and instructions support
The following options are available when as is configured for a PowerPC processor.
-a32— generate ELF32 or XCOFF32.-a64— generate ELF64 or XCOFF64.-K PIC— literally just setsEF_PPC_RELOCATABLE_LIBin the ELF flags. that's it. that's the whole job. 💅-mpwrx,-mpwr2— generate code for POWER/2 (RIOS2).-mpwr— generate code for POWER (RIOS1).-m601— generate code for PowerPC 601.-mppc,-mppc32,-m603,-m604— generate code for PowerPC 603/604.-m403,-m405— generate code for PowerPC 403/405.-m440— generate code for PowerPC 440. BookE and some 405 instructions, she's versatile like that 🦋-m464— generate code for PowerPC 464.-m476— generate code for PowerPC 476.-m7400,-m7410,-m7450,-m7455— generate code for PowerPC 7400/7410/7450/7455.-m750cl,-mgekko,-mbroadway— generate code for PowerPC 750CL/Gekko/Broadway. yes bestie, Gekko and Broadway, the actual GameCube and Wii chips, they're literally in here 😭🔥-m821,-m850,-m860— generate code for PowerPC 821/850/860.-mppc64,-m620— generate code for PowerPC 620/625/630.-me200z2,-me200z4— generate code for e200 variants:e200z2with LSP,e200z4with SPE.-me300— generate code for the PowerPC e300 family.-me500,-me500x2— generate code for the Motorola e500 core complex.-me500mc— generate code for the Freescale e500mc core complex.-me500mc64— generate code for the Freescale e500mc64 core complex.-me5500— generate code for the Freescale e5500 core complex.-me6500— generate code for the Freescale e6500 core complex.-mlsp— enable LSP instructions. (and yeah, it disables SPE and SPE2, they cannot all coexist, it's giving pick a lane 💀)-mspe— generate code for Motorola SPE instructions. (disables LSP.)-mspe2— generate code for Freescale SPE2 instructions. (disables LSP.)-mtitan— generate code for the AppliedMicro Titan core complex.-mppc64bridge— generate code for PowerPC 64, including bridge insns.-mbooke— generate code for 32-bit BookE.-ma2— generate code for the A2 architecture.-maltivec— generate code for processors with AltiVec instructions.-mvle— generate code for Freescale PowerPC VLE instructions.-mvsx— generate code for processors with Vector-Scalar (VSX) instructions.-mhtm— generate code for processors with Hardware Transactional Memory instructions.-mpower4,-mpwr4— generate code for the Power4 architecture.-mpower5,-mpwr5,-mpwr5x— generate code for the Power5 architecture.-mpower6,-mpwr6— generate code for the Power6 architecture.-mpower7,-mpwr7— generate code for the Power7 architecture.-mpower8,-mpwr8— generate code for the Power8 architecture.-mpower9,-mpwr9— generate code for the Power9 architecture.-mpower10,-mpwr10— generate code for the Power10 architecture.-mpower11,-mpwr11— generate code for the Power11 architecture.-mfuture— generate code for the'future'architecture. mysterious. main character energy fr 🔮-mcell— generate code for the Cell Broadband Engine architecture.-mcell— generate code for the Cell Broadband Engine architecture. yes it's listed twice in the page, no I'm not fixing it, I don't make the rules 🫶-mcom— generate code for Power/PowerPC common instructions.-many— generate code for any architecture (PWR/PWRX/PPC). all of them. greedy. love that.-mregnames— allow symbolic names for registers.-mno-regnames— do not allow symbolic names for registers.-mrelocatable— support for GCC's-mrelocatableoption.-mrelocatable-lib— support for GCC's-mrelocatable-liboption.-memb— set thePPC_EMBbit in ELF flags.-mlittle,-mlittle-endian,-le— generate code for a little endian machine.-mbig,-mbig-endian,-be— generate code for a big endian machine.-nops=count— if an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops. so you're not out here executing a whole staircase of nothing 💅
okay next up 🌈 — the following options are available when as is configured for a RISC-V processor.
-fpic,-fPIC— generate position-independent code.-fno-pic— don't generate position-independent code (default).-march=ISA|Profiles|Profiles_ISA— select the base isa, as specified by ISA or Profiles or Profies_ISA. for example-march=rv32ima-march=RVI20U64-march=RVI20U64_d. if this option and the architecture attributes aren't set, then the assembler will check the default configure setting--with-arch=ISA.-misa-spec=ISAspec— select the default isa spec version. if the version of ISA isn't set by-march, then the assembler helps to set the version according to the default chosen spec. if this option isn't set, then the assembler will check the default configure setting--with-isa-spec=ISAspec.-mpriv-spec=PRIVspec— select the privileged spec version. we can decide whether the CSR is valid or not according to the chosen spec. if this option and the privilege attributes aren't set, then the assembler will check the default configure setting--with-priv-spec=PRIVspec.-mabi=ABI— selects the ABI, which is eitherilp32orlp64, optionally followed byf,d, orqto indicate single-precision, double-precision, or quad-precision floating-point calling convention, ornoneoreto indicate the soft-float calling convention (eindicates a soft-float RVE ABI).-mrelax— take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default)-mno-relax— don't do linker relaxations.-march-attr— generate the default contents for the riscv elf attribute section if the.attributedirectives are not set. this section is used to record the information that a linker or runtime loader needs to check compatibility. this information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification.-mno-arch-attr— don't generate the default riscv elf attribute section if the.attributedirectives are not set.-mcsr-check— enable the CSR checking for the ISA-dependent CRS and the read-only CSR. the ISA-dependent CSR are only valid when the specific ISA is set. the read-only CSR can not be written by the CSR instructions.-mno-csr-check— don't do CSR checking.-mlittle-endian— generate code for a little endian machine.-mbig-endian— generate code for a big endian machine.
see the info pages for documentation of the RX-specific options. bestie I'm not hiding them from you, they're just literally over there 📖✨
the following options are available when as is configured for the s390 processor family.
-m31— select the word size: 31/32 bits. ✨-m64— select the word size: 64 bits.-mesa— select the architecture mode: the Enterprise System Architecture (esa).-mzarch— select the architecture mode: z/Architecture mode (zarch).-march=processor— specify which s390 processor variant is the target:g5(orarch3),g6,z900(orarch5),z990(orarch6),z9-109,z9-ec(orarch7),z10(orarch8),z196(orarch9),zEC12(orarch10),z13(orarch11),z14(orarch12),z15(orarch13),z16(orarch14), orz17(orarch15).-mregnames— allow symbolic names for registers.-mno-regnames— disallow symbolic names for registers.-mwarn-areg-zero— warn whenever the operand for a base or index register has been specified but evaluates to zero.-mwarn-regtype-mismatch=strict,-mwarn-regtype-mismatch=relaxed,-mwarn-regtype-mismatch=no,-mno-warn-regtype-mismatch— controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type. the default (which can be restored by using therelaxedargument) is to perform relaxed register name type checks, which allow floating point register (FPR) names%f0to%f15to be specified as argument to vector register (VR) operands and vector register (VR) names%v0to%v15to be specified as argument to floating point register (FPR) operands. this is acceptable as the FPR are embedded into the lower half of the VR. using thestrictargument, strict register name type checks are performed. thenoargument, which is equivalent to-mno-warn-regtype-mismatch, disables any register name type checks. ngl that's a lot of words for "we're chill about FPR/VR crossover unless you say otherwise" 😭
the following options are available when as is configured for a TMS320C6000 processor.
-march=arch— enable (only) instructions from architecture arch. by default, all instructions are permitted. the following values of arch are accepted:"c62x","c64x","c64x+","c67x","c67x+","c674x".-mdsbt— causes the assembler to generate the"Tag_ABI_DSBT"attribute with a value of1, indicating that the code is using DSBT addressing.-mno-dsbt— the default; causes the tag to have a value of0, indicating that the code does not use DSBT addressing. the linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. ⚠️ keep your types matching, bestie, the linker will call you out.-mpid=no— the default; indicates position-dependent data addressing. generates the"Tag_ABI_PID"attribute with a value indicating the form of data addressing used by the code.-mpid=near— indicates position-independent addressing with GOT accesses using near DP addressing.-mpid=far— indicates position-independent addressing with GOT accesses using far DP addressing.
for the -mpid= family: the linker will emit a warning if objects built with different settings of this option are linked together. 👀
-mpic— causes the assembler to generate the"Tag_ABI_PIC"attribute with a value of1, indicating that the code is using position-independent code addressing.-mno-pic— the default; causes the tag to have a value of0, indicating position-dependent code addressing. the linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together.-mbig-endian— generate code for big-endian.-mlittle-endian— generate code for little-endian. the default is little-endian.
the following options are available when as is configured for a TILE-Gx processor.
-m32|-m64— select the word size, either 32 bits or 64 bits.-EB|-EL— select the endianness, either big-endian (-EB) or little-endian (-EL).
the following option is available when as is configured for a Visium processor.
-mtune=arch— this option specifies the target architecture. if an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. the following names are recognized:"mcm24""mcm""gr5""gr6".
the following options are available when as is configured for an Xtensa processor.
…and that's where this part hands it off, bestie, the Xtensa options are right around the corner 💖
--text-section-literals,--no-text-section-literals— okay so this controls how literal pools get treated 💅 the default is--no-text-section-literals, which drops the literals into separate sections in the output file — and that's the whole point, because it lets the literal pool live in a data RAM/ROM. With--text-section-literals, the literals get interspersed in the text section so they stay as close as possible to their references. Why would you want that? Because for large assembly files the literals would otherwise be out of range of theL32Rinstructions in the text section 😭 Literals get grouped into pools following.literal_positiondirectives or precedingENTRYinstructions. Real talk tho: these options only affect literals referenced via PC-relativeL32Rinstructions — literals for absolute modeL32Rinstructions are handled separately, no cap.--auto-litpools,--no-auto-litpools— literal pool treatment, round two 🎀 default is--no-auto-litpools, which (in the absence of--text-section-literals) puts literals in separate sections in the output file, which again lets the literal pool chill in a data RAM/ROM. With--auto-litpools, literals get interspersed in the text section so they stay as close as possible to their references, and honestly the bestie part is that explicit.literal_positiondirectives are not required ✨ This is the move for very large functions, where a single literal pool at the beginning of the function may not be reachable byL32Rinstructions at the end. Same disclaimer as before: only affects literals referenced via PC-relativeL32Rinstructions; absolute modeL32Rliterals are handled separately. And when you use it together with--text-section-literals,--auto-litpoolstakes precedence 👑--absolute-literals,--no-absolute-literals— tells the assembler whetherL32Rinstructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absoluteL32Rrelocations. Otherwise? Only the PC-relativeL32Rrelocations can be used. That's it, that's the vibe.--target-align,--no-target-align— turn automatic alignment on or off to reduce branch penalties, at some expense in code size 🦋 This optimization is enabled by default. Little note tho: the assembler will always align instructions likeLOOPthat have fixed alignment requirements — you can't opt out of that one, bestie, it's built in 💅--longcalls,--no-longcalls— enables or disables transformation of call instructions so calls can reach across a greater range of addresses. Use this when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. Default is--no-longcalls.--transform,--no-transform— enables or disables all assembler transformations of Xtensa instructions, including both relaxation and optimization. Default is--transform. Now listen:--no-transformshould only be used in the rare cases when the instructions must be exactly as specified in the assembly source. And the consequence? Using--no-transformcauses out of range instruction operands to be errors 💀 so be careful.--rename-sectionoldname=newname — renames the oldname section to newname. You can use this option multiple times to rename multiple sections 🎀--trampolines,--no-trampolines— enables or disables transformation of jump instructions so jumps can span a greater range of addresses. Use it when jump targets can potentially be out of range. In the absence of such jumps, this option does not affect code size or performance. Default is--trampolines.--abi-windowed,--abi-call0— picks the ABI tag written to the.xtensa.infosection. The ABI tag indicates the ABI of the assembly code. The linker issues a warning if you try to link object files with inconsistent ABI tags. The default ABI is chosen by the Xtensa core configuration.
The following options are available when as is configured for an Z80 processor 💜
🧚 @chapter Z80 Dependent Features 🧚
🌸 Command-line Options 🌸
-march=CPU[-EXT...][+EXT...]— specifies the target processor. If you try to assemble an instruction that won't execute on the target processor, the assembler will throw an error message at you, so no vibes-based assembly, okay? The recognized processor names arez80,z180,ez80,gbz80,z80n,r800✨
Beyond the basic instruction set, you can tell the assembler to accept some extension mnemonics. For example, -march=z180+sli+infc extends z180 with SLI instructions and IN F,(C). The extensions currently supported are:
full— all known instructionsadl— ADL CPU mode by default (eZ80 only)sli— the instruction known as SLI, SLL or SL1xyhl— instructions with halves of index registers: IXL, IXH, IYL, IYHxdcb— instructions like RotOp (II+d),R and BitOp n,(II+d),Rinfc— the instructionIN F,(C)orIN (C)outc0— the instructionOUT (C),0
And here's the plot twist 🌈 rather than extending a basic instruction set, the extension mnemonics starting with - revoke the respective functionality: -march=z80-full+xyhl first removes all default extensions and then adds support for index register halves only. Periodt.
If this option is not specified, then -march=z80+xyhl+infc is assumed 💅
- *
-local-prefix=prefix* — marks all labels with the specified prefix as local. But lowkey, such a label can still be marked global explicitly in the code. Heads up: this option does not change the default local label prefix.L— it just adds a new one 🫶 -colonless— accepts colonless labels. All symbols at line begin are treated as labels. Okay slay ✨-sdcc— accepts assembler code produced by SDCC.- *
-fp-s=FORMAT* — single precision floating point numbers format. Default:ieee754(32 bit). - *
-fp-d=FORMAT* — double precision floating point numbers format. Default:ieee754(64 bit).
🫶 SEE ALSO 🫶
gcc(1), ld(1), and the Info entries for binutils and ld. Go read those next, bestie, they're lowkey iconic 💖
👑 COPYRIGHT 👑
Copyright (c) 1991-2026 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".
And that's the whole page, babes 🎀 this one came from binutils-2.47, dated 2026-09-12, and it's the manual for AS(1). Stan a well-documented assembler. Periodt 💅💖
📦 where this page comes from
- ubuntu stonking: binutils-bpf 2.47-6ubuntu1+2
- 💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms