AS(1)

💖 AS(1) — the portable GNU assembler 💖

Okay bestie, welcome to GNU Development Tools. This is AS, aka the portable GNU assembler. She’s iconic, she’s flexible, and she assembles for a whole multiverse of targets. Periodt.

---

✨ NAME ✨

AS — the portable GNU assembler. That’s the whole name, no cap. 💅

---

🌸 SYNOPSIS 🌸

Here’s the whole call pattern, every flag and form exactly as the manpage serves it. No skipping, no summarizing, no “you get the vibe.” We keep all the receipts.

as [-a[cdghilns][=file]]
 [--alternate]
 [--compress-debug-sections] [--nocompress-debug-sections]
 [-D]
 [--dump-config]
 [--debug-prefix-map old=new]
 [--defsym sym=val]
 [--elf-stt-common=[no|yes]]
 [--emulation=name]
 [-f]
 [-g] [--gstabs] [--gstabs+]
 [--gdwarf-<N>] [--gdwarf-sections]
 [--gdwarf-cie-version=VERSION]
 [--generate-missing-build-notes=[no|yes]]
 [--gsframe] [--gsframe=[no|yes]]
 [--gsframe-3]
 [--hash-size=N]
 [--help] [--target-help]
 [--info] [--no-info]
 [-I dir]
 [-J]
 [-K]
 [--keep-locals]
 [-L]
 [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM]
 [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM]
 [--multibyte-handling=[allow|warn|warn-sym-only]]
 [--no-pad-sections]
 [-o objfile] [-R]
 [--reloc-section-sym=[all|internal|none]]
 [--scfi=experimental]
 [--sectname-subst]
 [--size-check=[error|warning]]
 [--statistics]
 [-v] [--verbose]
 [-version] [--version]
 [-W] [--no-warn] [--warn] [--fatal-warnings]
 [-w] [-x]
 [-Z] [@FILE]
 [target-options]
 [--|files ...]

---

👑 TARGET 👑

Okay so as can target a whole multiverse of CPUs. Here’s every target option, no skips, no shortcuts. If it was in the original list, it’s here. Every single one. 🫶

🎀 Target AArch64 options 🎀

AArch64 besties, this is your set:

• -EB
• -EL
• -mabi=ABI

🎀 Target Alpha options 🎀

Alpha girlies, come get your flags:

• -mcpu
• -mdebug
• -no-mdebug
• -replace
• -noreplace
• -relax
• -g
• -Gsize
• -F
• -32addr

🎀 Target ARC options 🎀

ARC options, let’s go:

• -mcpu=cpu
• -mA6
• -mARC600
• -mARC601
• -mA7
• -mARC700
• -mEM
• -mHS
• -mcode-density
• -mrelax
• -EB
• -EL

🎀 Target ARM options 🎀

ARM options, the lineup is giving:

• -mcpu=processor[+extension...]
• -march=architecture[+extension...]
• -mfpu=floating-point-format
• -mfloat-abi=abi
• -meabi=ver
• -mthumb
• -EB
• -EL
• -mapcs-32
• -mapcs-26
• -mapcs-float
• -mapcs-reentrant
• -mthumb-interwork
• -k

🎀 Target Blackfin options 🎀

Blackfin, you’re up:

• -mcpu=processor[-sirevision]
• -mfdpic
• -mno-fdpic
• -mnopic

🎀 Target BPF options 🎀

BPF, short and sweet:

• -EL
• -EB

🎀 Target CRIS options 🎀

CRIS options, no notes:

• --underscore
• --no-underscore
• --pic
• -N
• --emulation=criself
• --emulation=crisaout
• --march=v0_v10
• --march=v10
• --march=v32
• --march=common_v10_v32

🎀 Target C-SKY options 🎀

C-SKY besties, this list is long but we’re obsessed:

• -march=arch
• -mcpu=cpu
• -EL
• -mlittle-endian
• -EB
• -mbig-endian
• -fpic
• -pic
• -mljump
• -mno-ljump
• -force2bsr
• -mforce2bsr
• -no-force2bsr
• -mno-force2bsr
• -jsri2bsr
• -mjsri2bsr
• -no-jsri2bsr
• -mno-jsri2bsr
• -mnolrw
• -mno-lrw
• -melrw
• -mno-elrw
• -mlaf
• -mliterals-after-func
• -mno-laf
• -mno-literals-after-func
• -mlabr
• -mliterals-after-br
• -mno-labr
• -mnoliterals-after-br
• -mistack
• -mno-istack
• -mhard-float
• -mmp
• -mcp
• -mcache
• -msecurity
• -mtrust
• -mdsp
• -medsp
• -mvdsp

🎀 Target D10V options 🎀

D10V, one option, still iconic:

• -O

🎀 Target D30V options 🎀

D30V options, three ways:

• -O
• -n
• -N

🎀 Target EPIPHANY options 🎀

EPIPHANY options:

• -mepiphany
• -mepiphany16

🎀 Target H8/300 options 🎀

H8/300 option:

• -h-tick-hex

🎀 Target i386 options 🎀

i386 besties, here’s the menu:

• --32
• --x32
• --64
• -n
• -march=CPU[+EXTENSION...]
• -mtune=CPU

🎀 Target IA-64 options 🎀

IA-64 options, collected:

• -mconstant-gp
• -mauto-pic
• -milp32
• -milp64
• -mlp64
• -mp64
• -mle
• -mbe
• -mtune=itanium1
• -mtune=itanium2
• -munwind-check=warning
• -munwind-check=error
• -mhint.b=ok
• -mhint.b=warning
• -mhint.b=error
• -x
• -xexplicit
• -xauto
• -xdebug

🎀 Target IP2K options 🎀

IP2K options:

• -mip2022
• -mip2022ext

🎀 Target M32C options 🎀

M32C options:

• -m32c
• -m16c
• -relax
• -h-tick-hex

🎀 Target M32R options 🎀

M32R options:

• --m32rx
• --[no-]warn-explicit-parallel-conflicts
• --W[n]p

🎀 Target M680X0 options 🎀

M680X0 options:

• -l
• -m68000
• -m68010
• -m68020
• ...

🎀 Target M68HC11 options 🎀

M68HC11 options, all lined up:

• -m68hc11
• -m68hc12
• -m68hcs12
• -mm9s12x
• -mm9s12xg
• -mshort
• -mlong
• -mshort-double
• -mlong-double
• --force-long-branches
• --short-branches
• --strict-direct-mode
• --print-insn-syntax
• --print-opcodes
• --generate-example

🎀 Target MCORE options 🎀

MCORE options:

• -jsri2bsr
• -sifilter
• -relax
• -mcpu=[210|340]

🎀 Target Meta options 🎀

Meta options:

• -mcpu=cpu
• -mfpu=cpu
• -mdsp=cpu

🎀 Target MICROBLAZE options 🎀

MICROBLAZE options:

• -mlittle-endian
• -mbig-endian

🎀 Target MIPS options 🎀

MIPS girlies, this is a whole feast. No cap, every option is here:

• -nocpp
• -EL
• -EB
• -O[optimization level]
• -g[debug level]
• -G num
• -KPIC
• -call_shared
• -non_shared
• -xgot
• -mvxworks-pic
• -mabi=ABI
• -32
• -n32
• -64
• -mfp32
• -mgp32
• -mfp64
• -mgp64
• -mfpxx
• -modd-spreg
• -mno-odd-spreg
• -march=CPU
• -mtune=CPU
• -mips1
• -mips2
• -mips3
• -mips4
• -mips5
• -mips32
• -mips32r2
• -mips32r3
• -mips32r5
• -mips32r6
• -mips64
• -mips64r2
• -mips64r3
• -mips64r5
• -mips64r6
• -construct-floats
• -no-construct-floats
• -mignore-branch-isa
• -mno-ignore-branch-isa
• -mnan=encoding
• -trap
• -no-break
• -break
• -no-trap
• -mips16
• -no-mips16
• -mmips16e2
• -mno-mips16e2
• -mmicromips
• -mno-micromips
• -msmartmips
• -mno-smartmips
• -mips3d
• -no-mips3d
• -mdmx
• -no-mdmx
• -mdsp
• -mno-dsp
• -mdspr2
• -mno-dspr2
• -mdspr3
• -mno-dspr3
• -mmsa
• -mno-msa
• -mxpa
• -mno-xpa
• -mmt
• -mno-mt
• -mmcu
• -mno-mcu
• -mcrc
• -mno-crc
• -mginv
• -mno-ginv
• -mloongson-mmi
• -mno-loongson-mmi
• -mloongson-cam
• -mno-loongson-cam
• -mloongson-ext
• -mno-loongson-ext
• -mloongson-ext2
• -mno-loongson-ext2
• -minsn32
• -mno-insn32
• -mfix7000
• -mno-fix7000
• -mfix-rm7000
• -mno-fix-rm7000
• -mfix-vr4120
• -mno-fix-vr4120
• -mfix-vr4130
• -mno-fix-vr4130
• -mfix-r5900
• -mno-fix-r5900
• -mdebug
• -no-mdebug
• -mpdr
• -mno-pdr

🎀 Target MMIX options 🎀

MMIX options, delivered:

• --fixed-special-register-names
• --globalize-symbols
• --gnu-syntax
• --relax
• --no-predefined-symbols
• --no-expand
• --no-merge-gregs
• -x
• --linker-allocated-gregs

🎀 Target NDS32 options 🎀

NDS32 options, full set:

• -EL
• -EB
• -O
• -Os
• -mcpu=cpu
• -misa=isa
• -mabi=abi
• -mall-ext
• -m[no-]16-bit
• -m[no-]perf-ext
• -m[no-]perf2-ext
• -m[no-]string-ext
• -m[no-]dsp-ext
• -m[no-]mac
• -m[no-]div
• -m[no-]audio-isa-ext
• -m[no-]fpu-sp-ext
• -m[no-]fpu-dp-ext
• -m[no-]fpu-fma
• -mfpu-freg=FREG
• -mreduced-regs
• -mfull-regs
• -m[no-]dx-regs
• -mpic
• -mno-relax
• -mb2bb

🎀 Target PDP11 options 🎀

PDP11 options:

• -mpic
• -mno-pic
• -mall
• -mno-extensions
• -mextension
• -mno-extension
• -mcpu
• -mmachine

🎀 Target picoJava options 🎀

picoJava options:

• -mb
• -me

🎀 Target PowerPC options 🎀

PowerPC besties, this CPU list is huge and we’re here for it:

• -a32
• -a64
• -mpwrx
• -mpwr2
• -mpwr
• -m601
• -mppc
• -mppc32
• -m603
• -m604
• -m403
• -m405
• -m440
• -m464
• -m476
• -m7400
• -m7410
• -m7450
• -m7455
• -m750cl
• -mgekko
• -mbroadway
• -mppc64
• -m620
• -me500
• -e500x2
• -me500mc
• -me500mc64
• -me5500
• -me6500
• -mppc64bridge
• -mbooke
• -mpower4
• -mpwr4
• -mpower5
• -mpwr5
• -mpwr5x
• -mpower6
• -mpwr6
• -mpower7
• -mpwr7
• -mpower8
• -mpwr8
• -mpower9
• -mpwr9-ma2
• -mcell
• -mspe
• -mspe2
• -mtitan
• -me300
• -mcom
• -many
• -maltivec
• -mvsx
• -mhtm
• -mvle
• -mregnames
• -mno-regnames
• -mrelocatable
• -mrelocatable-lib
• -K PIC
• -memb
• -mlittle
• -mlittle-endian
• -le
• -mbig
• -mbig-endian
• -be
• -nops=count

🎀 Target PRU options 🎀

PRU options:

• -link-relax
• -mnolink-relax
• -mno-warn-regname-label

🎀 Target RISC-V options 🎀

RISC-V options, cute and complete:

• -fpic
• -fPIC
• -fno-pic
• -march=ISA|Profiles|Profiles_ISA
• -mabi=ABI
• -mlittle-endian
• -mbig-endian

🎀 Target RL78 options 🎀

RL78 options:

• -mg10
• -m32bit-doubles
• -m64bit-doubles

🎀 Target RX options 🎀

RX options, all of them:

• -mlittle-endian
• -mbig-endian
• -m32bit-doubles
• -m64bit-doubles
• -muse-conventional-section-names
• -msmall-data-limit
• -mpid
• -mrelax
• -mint-register=number
• -mgcc-abi
• -mrx-abi

🎀 Target s390 options 🎀

s390 options:

• -m31
• -m64
• -mesa
• -mzarch
• -march=CPU
• -mregnames
• -mno-regnames
• -mwarn-areg-zero
• -mwarn-regtype-mismatch=strict
• -mwarn-regtype-mismatch=relaxed
• -mwarn-regtype-mismatch=no
• -mno-warn-regtype-mismatch

🎀 Target SCORE options 🎀

SCORE options:

• -EB
• -EL
• -FIXDD
• -NWARN
• -SCORE5
• -SCORE5U
• -SCORE7
• -SCORE3
• -march=score7
• -march=score3
• -USE_R1
• -KPIC
• -O0
• -G num
• -V

🎀 Target SPARC options 🎀

SPARC options, full fantasy:

• -Av6
• -Av7
• -Av8
• -Aleon
• -Asparclet
• -Asparclite
• -Av8plus
• -Av8plusa
• -Av8plusb
• -Av8plusc
• -Av8plusd
• -Av8plusv
• -Av8plusm
• -Av9
• -Av9a
• -Av9b
• -Av9c
• -Av9d
• -Av9e
• -Av9v
• -Av9m
• -Asparc
• -Asparcvis
• -Asparcvis2
• -Asparcfmaf
• -Asparcima
• -Asparcvis3
• -Asparcvisr
• -Asparc5
• -xarch=v8plus
• -xarch=v8plusa
• -xarch=v8plusb
• -xarch=v8plusc
• -xarch=v8plusd
• -xarch=v8plusv
• -xarch=v8plusm
• -xarch=v9
• -xarch=v9a
• -xarch=v9b
• -xarch=v9c
• -xarch=v9d
• -xarch=v9e
• -xarch=v9v
• -xarch=v9m
• -xarch=sparc
• -xarch=sparcvis
• -xarch=sparcvis2
• -xarch=sparcfmaf
• -xarch=sparcima
• -xarch=sparcvis3
• -xarch=sparcvisr
• -xarch=sparc5
• -bump
• -32
• -64
• --enforce-aligned-data
• --dcti-couples-detect

🎀 Target TIC54X options 🎀

TIC54X options:

• -mcpu=54[123589]
• -mcpu=54[56]lp
• -mfar-mode
• -mf
• -merrors-to-file <filename>
• -me <filename>

🎀 Target TIC6X options 🎀

TIC6X options:

• -march=arch
• -mbig-endian
• -mlittle-endian
• -mdsbt
• -mno-dsbt
• -mpid=no
• -mpid=near
• -mpid=far
• -mpic
• -mno-pic

🎀 Target TILE-Gx options 🎀

TILE-Gx options:

• -m32
• -m64
• -EB
• -EL

🎀 Target Visium options 🎀

Visium option:

• -mtune=arch

🎀 Target Xtensa options 🎀

Xtensa options, all the [no-] energy:

• --[no-]text-section-literals
• --[no-]auto-litpools
• --[no-]absolute-literals
• --[no-]target-align
• --[no-]longcalls
• --[no-]transform
• --rename-section oldname=newname
• --[no-]trampolines
• --abi-windowed
• --abi-call0

🎀 Target Z80 options 🎀

Z80 options, final girl energy:

• -march=CPU[-EXT][+EXT]
• -local-prefix=PREFIX
• -colonless
• -sdcc
• -fp-s=FORMAT
• -fp-d=FORMAT

✨ DESCRIPTION ✨

okay so bestie, plot twist: GNU as is not one assembler, it's literally a whole family of assemblers 🫶. If you've used the GNU assembler on one architecture, then hopping to another architecture should feel like walking into the same house with different furniture — super similar environment. Every version shares a ton of DNA with the others, including object file formats, most assembler directives (the girlies call them pseudo-ops 💅) and assembler syntax.

as is mainly here to assemble the output of the GNU C compiler gcc, so that the linker ld can do its thing with it. And yet — and this is the slay part — we've genuinely tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions? Documented explicitly, no sneaky business, periodt. That said, this does not mean as always uses the same syntax as another assembler for the same architecture. Example: we know of several incompatible versions of 680x0 assembly language syntax, and honestly, that's just the lore 💀.

Every single time you run as, it assembles exactly one source program. That source program is made up of one or more files. (And yes, the standard input counts as a file too 👑.)

So you hand as a command line that has zero or more input file names. The input files get read from the left file name to the right. Any command-line argument (in any position) that has no special meaning is just taken to be an input file name. Simple as.

If you give as no file names at all, it tries to read one input file from standard input, which is normally your terminal. You may have to type ctl-D to tell as there is no more program to assemble — like ringing the doorbell to say you're done 🎀.

Use -- if you need to explicitly name the standard input file in your command line.

If the source is empty, as produces a small, empty object file. Tiny. Iconic. Perfect for when you have nothing to say but still want to show up.

as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption that was made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly. One is a lil "hmm bestie" and the other is a full-on 💀.

If you're invoking as via the GNU C compiler, you can use the -Wa option to pass arguments straight through to the assembler. The assembler arguments must be separated from each other (and from the -Wa) by commas. For example:

gcc -c -g -O -Wa,-alh,-L file.c

That passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain internal symbols in the symbol table). Two for one, we love a combo deal 🌸.

Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (And if you're nosy — respectfully — you can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler. Screenshot that. Receipts. 🧾✨)

---

🌸 OPTIONS 🌸

• @file — Read command-line options from file. The options that get read are inserted in place of the original @file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed.

Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively. It's giving inception, bestie 🌀.

• -a[cdghilmns] — Turn on listings, in any of a variety of ways:
  • -ac — omit false conditionals
  • -ad — omit debugging directives
  • -ag — include general information, like as version and options passed
  • -ah — include high-level source
  • -al — include assembly
  • -ali — include assembly with ginsn
  • -am — include macro expansions
  • -an — omit forms processing
  • -as — include symbols
  • =file — set the name of the listing file

You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls. Build your own listing, choose-your-own-adventure energy 🦋.

• --alternate — Begin in alternate macro mode.
• --compress-debug-sections — Compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. Heads up: the resulting object file may not be compatible with older linkers and object file utilities. Also note — if compression would make a given section larger, then it is not compressed. No glow-down allowed 💅.
• --compress-debug-sections=none, --compress-debug-sections=zlib, --compress-debug-sections=zlib-gnu, --compress-debug-sections=zlib-gabi, --compress-debug-sections=zstd — These options control how DWARF debug sections are compressed. --compress-debug-sections=none is equivalent to --nocompress-debug-sections. --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to --compress-debug-sections. --compress-debug-sections=zlib-gnu compresses DWARF debug sections using the obsoleted zlib-gnu format, and the debug sections get renamed to begin with .zdebug. --compress-debug-sections=zstd compresses DWARF debug sections using zstd. Note — if compression would actually make a section larger, then it is not compressed nor renamed.
• --nocompress-debug-sections — Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.
• -D — Enable debugging in target specific backends, if supported. Otherwise ignored. Even if ignored, this option is accepted for script compatibility with calls to other assemblers. Accepted-but-ignored is such a mood 😭.
• --debug-prefix-map old=new — When assembling files in directory old, record debugging information describing them as in new instead.
• --defsym sym=value — Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a .set pseudo-op. Pre-gaming the symbol table, love that for you 💜.
• --dump-config — Displays how the assembler is configured and then exits.
• --elf-stt-common=no, --elf-stt-common=yes — These options control whether the ELF assembler should generate common symbols with the STT_COMMON type. The default can be controlled by a configure option --enable-elf-stt-common.
• --emit-local-absolute — Emit even pre-defined (local) absolute symbols to the outgoing symbol table. Note that this isn't the exact opposite of --strip-local-absolute. It's close but it's not a mirror, bestie, don't @ me 🪞.
• --emulation=name — If the assembler is configured to support multiple different target configurations then this option can be used to select the desired form.
• -f — "fast" — skip whitespace and comment preprocessing (assume source is compiler output). Zoom zoom 🏎️.
• -g, --gen-debug — Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a .debug_info and .debug_line section is only emitted when the assembly file doesn't generate one itself.
• --gstabs — Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
• --gstabs+ — Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time.

okay bestie this one is spicy 🌶️ — those extensions are gdb-only coded and other debuggers might literally bounce.

• --gdwarf-2 — Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note — this option is only supported by some targets, not all of them.
• --gdwarf-3 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
• --gdwarf-4 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
• --gdwarf-5 — This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis.
• --gdwarf-sections — Instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. For example a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. If the code section is just called .text then debug line section will still be called just .debug_line without any suffix. Per-section glow-up ✨.
• --gdwarf-cie-version=version — Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specified the default is version 1, though some targets can modify this default. Other possible values for version are 3 or 4.
• --generate-missing-build-notes=yes, --generate-missing-build-notes=no — These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the --enable-generate-build-notes configure option.
• --gsframe, --gsframe, --gsframe=no, --gsframe=yes — Create .sframe section from CFI directives. The explicit --gsframe=yes option behaves the same as --gsframe. Generation can be suppressed with --gsframe=no. The default can be controlled by a configure option --enable-default-sframe. The current version of the emitted SFrame stack trace data is SFRAME_VERSION_3.
• --gsframe-3 — Generate SFrame stack trace information as per Version 3 of the specification.
• --hash-size N — Ignored. Supported for command line compatibility with other assemblers. (She's here, she's just not doing anything 💀)
• --help — Print a summary of the command-line options and exit.
• --target-help — prints a lil summary of all the target-specific options and dips. that's it, that's the whole job 💅
• --info — don't suppress informational messages. let them yap, we're listening 🫶
• --no-info — suppress informational messages. hush mode activated 🤫
• -I dir — adds the directory dir to the search list for .include directives. so like, when you go looking for includes, bestie, this folder is on the list ✨
• -J — don't warn about signed overflow. no cap, just vibes 🌸
• -K — issues warnings when difference tables have been altered for long displacements.
• -L, --keep-locals — keeps internal symbols in the symbol table. these symbols start with system-specific local label prefixes — typically .L for ELF systems, or L for traditional a.out systems. they get to stay 🎀
• --listing-lhs-width=number — sets the maximum width, in words, of the output data column for an assembler listing to number.
• --listing-lhs-width2=number — same energy, but for the output data column of continuation lines in an assembler listing. max width in words = number. 🦋
• --listing-rhs-width=number — sets the maximum width of an input source line, as displayed in a listing, to number bytes.
• --listing-cont-lines=number — sets the maximum number of lines printed in a listing for a single line of input to number + 1. yes, plus one. iconic 🌈
• --multibyte-handling=allow, --multibyte-handling=warn, --multibyte-handling=warn-sym-only, --multibyte-handling=warn_sym_only — this whole lil family controls how the assembler handles multibyte characters in the input 💜
  • the default is to allow such characters without complaint, and you can also restore that default by passing the allow argument.
  • warn makes the assembler generate a warning message whenever any multibyte character is encountered.
  • warn-sym-only only causes a warning when a symbol is defined with a name that contains multibyte characters. (references to undefined symbols will not generate a warning, bestie, keep that in mind.)
• --no-pad-sections — stops the assembler from padding the ends of output sections to the alignment of that section. the default is to pad the sections, but ngl that can waste space — and on targets with tight memory constraints, that space is precious 🥺
• -o objfile — names the object-file output from as objfile.
• -R — folds the data section into the text section. merging eras 💫
• --reduce-memory-overheads — ignored. it's supported for compatibility with tools that pass the same option to both the assembler and the linker. so it just. sits there. respectfully 🧚
• --reloc-section-sym=all, --reloc-section-sym=internal, --reloc-section-sym=none — controls whether relocations that reference local binding symbols get adjusted to use section symbols instead 🔧
  • all is the default: relocations against all eligible local binding symbols are converted.
  • internal: only relocations against internal labels (symbols matching the .L prefix) are converted.
  • none: no such conversions are performed at all.
• --scfi=experimental — this option controls whether the assembler should synthesize CFI for hand-written input. if the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning. ⚠️

note bestie: --scfi=experimental is not intended to be used for compiler-generated code, including inline assembly. this experimental support is work in progress. only System V AMD64 ABI is supported. it's giving "please don't ship this yet" 💀

each input function in assembly must begin with the .type directive, and should ideally be closed off using a .size directive. when using SCFI, each .type directive prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry). this implies that with each .type directive, a previous block of instructions, if any, is finalised as a distinct FDE. 👑

• --sectname-subst — honors substitution sequences in section names.
• --size-check=error, --size-check=warning — issues an error or a warning for an invalid ELF .size directive. you pick the drama level 💅
• --statistics — prints the maximum space (in bytes) and total time (in seconds) used by assembly. receipts! 📊
• --strip-local-absolute — removes local absolute symbols from the outgoing symbol table.
• -v, --verbose — prints the as version.
• --version, -version — prints the as version and exits. bye ✨
• -W, --no-warn — suppresses warning messages.
• --warn — don't suppress warning messages, and don't treat them as errors either.
• --fatal-warnings — treats warnings as errors. harsh but fair 😤
• -w — ignored.
• -x — ignored.
• -Z — generates an object file even after errors. yes, even then. bold of you, but okay 🫣
• -- | files ... — standard input, or source files to assemble.

---

🦋 options for when as is configured for the 64-bit mode of the ARM Architecture (AArch64) 🦋

• -EB — specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.
• -EL — specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.
• -mabi=abi — specify which ABI the source code uses. the recognized arguments are "ilp32" and "lp64", which decide the generated object file is in ELF32 and ELF64 format respectively. the default is "lp64". 💜
• -mcpu=processor[+extension...] — specifies the target processor. the assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. 🚨

the following processor names are recognized: "cortex-a34", "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73", "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77", "cortex-a78", "cortex-a78ae", "cortex-a78c", "cortex-a510", "cortex-a520", "cortex-a710", "cortex-a720", "ares", "exynos-m1", "falkor", "neoverse-n1", "neoverse-n2", "neoverse-e1", "neoverse-v1", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1" "xgene2", "cortex-r82", "cortex-x1", "cortex-x2", "cortex-x3", and "cortex-x4".

the special name "all" may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions 👑

in addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.

if some implementations of a particular processor can have an extension, then those extensions are automatically enabled. consequently, you will not normally have to specify any additional extensions. slay, free stuff 🎁

• -march=architecture[+extension...] — specifies the target architecture. the assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. 🚨

the following architecture names are recognized: "armv8-a", "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a", "armv8.6-a", "armv8.7-a", "armv8.8-a", "armv8.9-a", "armv8-r", "armv9-a", "armv9.1-a", "armv9.2-a", "armv9.3-a", "armv9.4-a" and "armv9.5-a".

if both -mcpu and -march are specified, the assembler will use the setting for -mcpu. if neither are specified, the assembler will default to -mcpu=all. ✨

the architecture option can be extended with the same instruction set extension options as the -mcpu option. unlike -mcpu, extensions are not always enabled by default. read that twice bestie 🙈

• -mbig-obj — on PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. huge. literally 🔥
• -mverbose-error — enables verbose error messages for AArch64 gas. this option is enabled by default.
• -mno-verbose-error — disables verbose error messages in AArch64 gas.
• -menable-sysreg-checking — enables error messages that are issued if an attempt is made to assemble a system register access which will not execute on the target architecture. vibe check for your sysregs, and it will fail you 💀

---

🌸 options for when as is configured for an Alpha processor 🌸

• -mcpu — specifies the target processor. if an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. this option is equivalent to the .arch directive.

the following processor names are recognized: 21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6", "ev67", "ev68". the special name "all" may be used to allow the assembler to accept instructions valid for any Alpha processor 👑

in order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. "ev4") do not. yes, "electro-vlasic". i'm not making this up, it's in the manual 💅

• -mdebug, -no-mdebug — enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. the default is to automatically enable .mdebug when the first stabs directive is seen. set it and forget it, basically ✨
• -relax — forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. however, the option can still be useful in specific applications. niche but valid 🫶
• -replace, -noreplace — enables or disables the optimization of procedure calls, both at assemblage and at link time. these options are only available for VMS targets and -replace is the default. see section 1.4.1 of the OpenVMS Linker Utility Manual 📖
• -g — this option is used when the compiler generates debug information. when gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. otherwise this option has no effect. so like, ride or die with gcc + ECOFF, otherwise it's just sitting there 🎀
• -Gsize — a local common symbol larger than size is placed in .bss, while smaller symbols are placed in .sbss. size sorting besties 💜
• -F, -32addr — these options are ignored, kept around for backward compatibility. fossils. iconic fossils 🦕

---

🧚 options for when as is configured for an ARC processor 🧚

• -mcpu=cpu — selects the core processor variant.
• -EB | -EL — select either big-endian (-EB) or little-endian (-EL) output.
• -mcode-density — enable Code Density extension instructions. cramming more into less, we love efficiency 💅

ARM, bestie 🎀 (the ARM processor family)

Okay so when as is built for ARM, these are the ones you're gonna meet:

• -mcpu=processor[+extension...] — tells it which ARM processor variant we're targeting, periodt.
• -march=architecture[+extension...] — this one is about which ARM architecture variant the target is using.
• -mfpu=floating-point-format — pick which Floating Point architecture is the target. The float vibes, choose your fighter.
• -mfloat-abi=abi — selects which floating point ABI is in use.
• -mthumb — enable Thumb-only instruction decoding. Thumb mode era 💅
• -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant — choose which procedure calling convention is in use.
• -EB | -EL — pick big-endian (-EB) or little-endian (-EL) output. Endianness drama, pick a side.
• -mthumb-interwork — says out loud that the code was generated with interworking between Thumb and ARM code in mind. teamwork makes the dream work 🫶
• -mccs — turns on CodeComposer Studio assembly syntax compatibility mode.
• -k — states that PIC code has been generated.

---

Blackfin besties 🦋 (the Blackfin processor family)

These ones show up when as is configured for Blackfin:

• -mcpu=processor[-sirevision] — specifies the target processor. Lowkey important: the optional sirevision is not used in the assembler — it's literally just hanging out there so GCC can pass down its -mcpu= option without drama. The assembler will throw an error message if you try to assemble an instruction that wouldn't execute on the target processor. The processor names it recognizes are: bf504, bf506, bf512, bf514, bf516, bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf535 (not implemented yet 🙈), bf536, bf537, bf538, bf539, bf542, bf542m, bf544, bf544m, bf547, bf547m, bf548, bf548m, bf549, bf549m, bf561, and bf592.
• -mfdpic — assemble for the FDPIC ABI.
• -mno-fdpic, -mnopic — disable -mfdpic. It's giving "actually never mind".

---

🧚 the Linux kernel BPF processor family

@chapter BPF Dependent Features

BPF Options

• -EB — this option specifies that the assembler should emit big-endian eBPF.
• -EL — this option specifies that the assembler should emit little-endian eBPF.
• -mdialect=dialect — specifies the assembly language dialect to recognize while assembling. The assembler supports normal and pseudoc.
• -misa-spec=spec — specifies which version of the BPF instruction set to use when assembling. The BPF ISA versions supported are v1 v2, v3 and v4.

You can also pass the value xbpf to recognize extra instructions that GCC uses for testing purposes — but bestie, beware, this is not valid BPF. 💀

• -mno-relax — tells the assembler to not relax instructions.

Heads up: if you don't specify any endianness option on the command line, the host endianness is used. And see the info pages for documentation of the CRIS-specific options. (Yes, they really just point you elsewhere like that. iconic in a rude way.)

---

C-SKY cuties ✨ (the C-SKY processor family)

• -march=archname — assemble for architecture archname. The --help option lists valid values for archname.
• -mcpu=cpuname — assemble for architecture cpuname. The --help option lists valid values for cpuname.
• -EL, -mlittle-endian — generate little-endian output.
• -EB, -mbig-endian — generate big-endian output.
• -fpic, -pic — generate position-independent code.
• -mljump, -mno-ljump — enable/disable transformation of the short branch instructions jbf, jbt, and jbr to jmpi. This option is for V2 processors only. It's ignored on CK801 and CK802 targets (they don't support the jmpi instruction, so, like, no), and it's enabled by default for other processors.
• -mbranch-stub, -mno-branch-stub — pass through R_CKCORE_PCREL_IMM26BY2 relocations for bsr instructions to the linker.

This option is only available for bare-metal C-SKY V2 ELF targets, where it's enabled by default. It cannot be used in code that will be dynamically linked against shared libraries. 🚫

• -force2bsr, -mforce2bsr, -no-force2bsr, -mno-force2bsr — enable/disable transformation of jbsr instructions to bsr. This option is always enabled (and -mno-force2bsr is ignored) for CK801/CK802 targets. It's also always enabled when -mbranch-stub is in effect.
• -jsri2bsr, -mjsri2bsr, -no-jsri2bsr, -mno-jsri2bsr — enable/disable transformation of jsri instructions to bsr. This one is enabled by default.
• -mnolrw, -mno-lrw — enable/disable transformation of lrw instructions into a movih/ori pair.
• -melrw, -mno-elrw — enable/disable extended lrw instructions. Enabled by default for CK800-series processors.
• -mlaf, -mliterals-after-func, -mno-laf, -mno-literals-after-func — enable/disable placement of literal pools after each function.
• -mlabr, -mliterals-after-br, -mno-labr, -mnoliterals-after-br — enable/disable placement of literal pools after unconditional branches. Enabled by default.
• -mistack, -mno-istack — enable/disable interrupt stack instructions. Enabled by default on CK801, CK802, and CK802 processors.

The following options explicitly enable certain optional instructions. These features also get enabled implicitly by using -mcpu= to specify a processor that supports it. iykyk.

• -mhard-float — enable hard float instructions.
• -mmp — enable multiprocessor instructions.
• -mcp — enable coprocessor instructions.
• -mcache — enable cache prefetch instruction.
• -msecurity — enable C-SKY security instructions.
• -mtrust — enable C-SKY trust instructions.
• -mdsp — enable DSP instructions.
• -medsp — enable enhanced DSP instructions.
• -mvdsp — enable vector DSP instructions.

---

Epiphany moment 🌈 (Epiphany processor)

• -mepiphany — specifies that both 32 and 16 bit instructions are allowed. This is the default behavior, main character energy by default fr.
• -mepiphany16 — restricts the permitted instructions to just the 16 bit set.

---

@chapter H8/300 Dependent Features

Options

The Renesas H8/300 version of as has one machine-dependent option:

• -h-tick-hex — support H'00 style hex constants in addition to 0x00 style.
• -mach=name — sets the H8300 machine variant. The following machine names are recognised: h8300h, h8300hn, h8300s, h8300sn, h8300sx and h8300sxn.

---

i386 time 💅 (the i386 processor)

• --32 | --x32 | --64 — select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.

These options are only available with the ELF object file format, and they require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).

• -n — by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.
• --divide — on SVR4-derived platforms, the character / is treated as a comment character, which means that it cannot be used in expressions. The --divide option turns / into a normal character. This does not disable / at the beginning of a line starting a comment, or affect using # for starting a comment. Slay, but with limits.
• -march=CPU[+EXTENSION...] — specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, znver5, znver6, btver1, btver2, generic32 and generic64.

k so on top of the basic instruction set, you can also tell the assembler to accept a whole lil' menu of extension mnemonics 💖 like, for example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. it's giving ✨custom build✨, no cap.

here's the full roster of extensions currently supported, bestie (eat ur heart out 🍓):

8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, avx512_bmm, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb, avx10.1, avx10.1/512, avx10.1/256, avx10.1/128, user_msr, msr_imm, apx_f, apx_nci, apx_ndd, apx_nf, apx_nci_ndd_nf, avx10.2, avx10.2/512, avx10.2/256, avx10.2/128, movrs, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8 amx_movrs, amx_avx512, amx_tile, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, snp, invlpgb, tlbsync, rmpquery, rmpread, svme, gmism2, gmiccs, padlockrng2, padlockphe2, padlockxmodx and padlock. 🫶

quick notes before we move on, bestie:

• every one of those extension mnemonics can be prefixed with no to revoke that functionality — and anything that depends on it 💀
• the suffixes allowed on -march=avx10.<N> enforce a vector length restriction, i.e. even though these are otherwise "enabling" options, using these suffixes will disable all insns with wider vector or mask register operands. the way that these pretend to be enabling while disabling… iconic honestly
• when the .arch directive is used with -march, the .arch directive takes precedent 👑

---

• -mtune=CPU — says which processor to optimize for 🧚 when it's used together with the -march option, only instructions of the processor named by -march get generated. the valid CPU values are identical to the processor list of -march=CPU. same list, different vibe.
• -moperand-check=none — assembler doesn't do these checks at all.
• -moperand-check=warning — assembler throws a warning when the checks fail. this is the default 👑
• -moperand-check=error — assembler throws an error when the checks fail.

so what even are these checks? they control whether the assembler checks certain instruction operands or operand combinations 🔍 an example would be instructions where the operand size can't be inferred from its operands and also hasn't been specified by way of an instruction suffix. ikyk.

• -msse2avx — tells the assembler to encode SSE instructions with a VEX prefix, which requires AVX to be available ✨ and SSE instructions that use extended GPRs get encoded with an EVEX prefix, which requires AVX512 or AVX10 to be available. stacking requirements like it's a group project 😭
• -muse-unaligned-vector-move — tells the assembler to encode an aligned vector move as an unaligned vector move. yeah. it just does that 💅
• -msse-check=none — assembler doesn't check SSE instructions. this is the default.
• -msse-check=warning — assembler issues a warning for any SSE instruction 🌸
• -msse-check=error — assembler issues an error for any SSE instruction.
• -mavxscalar=128 — encodes scalar AVX instructions with 128-bit vector length. this is the default.
• -mavxscalar=256 — encodes scalar AVX instructions with 256-bit vector length.

⚠️ WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models. like. pls don't. bestie i'm begging 💀

• -mvexwig=0 — encodes VEX.W-ignored (WIG) VEX instructions with vex.w = 0. this is the default.
• -mvexwig=1 — encodes WIG EVEX instructions with vex.w = 1.

⚠️ WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models. yes this one has the same warning. not a typo. 😭

• -mevexlig=128 — encodes length-ignored (LIG) EVEX instructions with 128-bit vector length. this is the default.
• -mevexlig=256 — encodes LIG EVEX instructions with 256-bit vector length.
• -mevexlig=512 — encodes LIG EVEX instructions with 512-bit vector length. (256 and 512 go respectively, okurrr 💅)
• -mevexwig=0 — encodes w-ignored (WIG) EVEX instructions with evex.w = 0. this is the default.
• -mevexwig=1 — encodes WIG EVEX instructions with evex.w = 1.
• -mmnemonic=att / -mmnemonic=intel — specifies the instruction mnemonic used for matching instructions 🎀 the .att_mnemonic and .intel_mnemonic directives will take precedent, so they get the final say.
• -msyntax=att / -msyntax=intel — specifies the instruction syntax used when processing instructions ✨ and again, the .att_syntax and .intel_syntax directives will take precedent.
• -mnaked-reg — says registers don't require a % prefix. and yup, the .att_syntax and .intel_syntax directives will take precedent here too. rules are rules 👑
• -madd-bnd-prefix — forces the assembler to add a BND prefix to all branches, even if that prefix wasn't explicitly written in the source code. 🌈
• -mno-shared — on an ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. the -mshared option tells the assembler to generate code that might go into a shared library, where all non-weak global branch targets with default visibility can be preempted. the resulting code is slightly bigger (worth it tbh). this option only affects the handling of branch instructions.
• -mbig-obj — on a PE/COFF target this forces the use of the big object file format, which allows more than 32768 sections 👑 big object energy fr fr.
• -momit-lock-prefix=no — encodes lock prefix as usual. this is the default.
• -momit-lock-prefix=yes — omits all lock prefixes.

these options control how the assembler encodes the lock prefix, and they're intended as a workaround for processors that fail on the lock prefix 🫠 which is why this option can only be safely used with single-core, single-thread computers. single. core. single. thread. do not test fate.

• -mfence-as-lock-add=no — encodes lfence, mfence and sfence as usual. this is the default.
• -mfence-as-lock-add=yes — encodes lfence, mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode, and lock addl $0x0, (%esp) in 32-bit mode ✨ (note the rsp vs esp, that's not a typo, that's the whole point 💅)
• -mrelax-relocations=no — won't generate relax relocations.
• -mrelax-relocations=yes — will generate relax relocations.

and what's a relax relocation you ask? it's R_386_GOT32X in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX in 64-bit mode. these options control whether the assembler generates them 🌸

• -mtls-check=no — won't check tls relocation.
• -mtls-check=yes — will check tls relocation.

these control whether the assembler checks tls relocation, and the default can be controlled by a configure option --enable-x86-tls-check 🎀

• -malign-branch-boundary=NUM — controls how the assembler aligns branches with segment prefixes or NOP. NUM must be a power of 2, and should be 0 or no less than 16. branches get aligned within a NUM byte boundary. -malign-branch-boundary=0, which is the default, doesn't align branches at all.
• -malign-branch=TYPE[+TYPE...] — says which types of branches to align 🦋 TYPE is a combination of: jcc (aligns conditional jumps), fused (aligns fused conditional jumps), jmp (aligns unconditional jumps), call (aligns calls), ret (aligns rets), and indirect (aligns indirect jumps and calls). the default is -malign-branch=jcc+fused+jmp ✨
• -malign-branch-prefix-size=NUM — the maximum number of prefixes on an instruction used to align branches. NUM should be between 0 and 5, and the default NUM is 5 💅
• -mbranches-within-32B-boundaries — aligns conditional jumps, fused conditional jumps and unconditional jumps within a 32 byte boundary, using up to 5 segment prefixes on an instruction 🫶 it's fully equivalent to:

-malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5

and just so we're clear, the default doesn't align branches. it's giving do-nothing and we respect that.

• -mlfence-after-load=no — won't generate lfence after load instructions, you guessed it, this is the default.
• -mlfence-after-load=yes — will generate lfence after load instructions 🔥 these two control whether the assembler generates lfence after load instructions, periodt.

okay so we're still in option city, bestie, and honestly this next batch is giving "the assembler is a control freak and we love her for it." Let's get into it 💅

---

🛡️ Fence & Encoding Options

• -mlfence-before-indirect-branch=none, -mlfence-before-indirect-branch=all, -mlfence-before-indirect-branch=register, -mlfence-before-indirect-branch=memory — these decide whether as should cook up an lfence before indirect near branch instructions.
  • all ✨ generates lfence before an indirect near branch via register, AND throws a warning before an indirect near branch via memory. Sneaky extra: it implicitly sets -mlfence-before-ret=shl whenever you haven't explicitly set -mlfence-before-ret= yourself.
  • register — generates lfence before indirect near branch via register.
  • memory — issues a warning before indirect near branch via memory.
  • none — no lfence, no warning. This is the default, no cap.

heads up 💀 lfence will NOT be generated before an indirect near branch via register when -mlfence-after-load=yes, because in that case the lfence gets generated after loading the branch target register. The way that ordering just rearranges itself.

• -mlfence-before-ret=none, -mlfence-before-ret=shl, -mlfence-before-ret=or, -mlfence-before-ret=yes, -mlfence-before-ret=not — these control whether as generates lfence before ret.
  • or 🌸 generates an or instruction with lfence.
  • shl / yes — generates an shl instruction with lfence.
  • not — generates a not instruction with lfence.
  • none — no lfence at all, and yes that's the default.
• -mx86-used-note=no, -mx86-used-note=yes — whether as should generate GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes. The default here is controlled by the --enable-x86-used-note configure option. iykyk 🎀
• -mevexrcig=rne, -mevexrcig=rd, -mevexrcig=ru, -mevexrcig=rz — how the assembler encodes SAE-only EVEX instructions, bestie.
  • rne encodes the RC bits of the EVEX instruction with 00 — that's the default ⭐
  • rd, ru and rz encode SAE-only EVEX instructions with 01, 10 and 11 RC bits, respectively.
• -mamd64, -mintel64 — tells as to accept ONLY AMD64 or Intel64 ISA in 64-bit mode. By default it's all chill and accepts common, Intel64 only and AMD64 ISAs. 🌈

---

🔥 Optimization Flags

• -O0 | -O | -O1 | -O2 | -Os — optimize instruction encoding toward a smaller instruction size. Here's the tea, tier by tier 👑
• -O and -O1 — encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates; encode 64-bit register clearing instructions with 32-bit register clearing instructions; encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions; encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions; and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical.
• -O2 — everything -O1 does, plus it encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions. In 64-bit mode, VEX encoded instructions with commutative source operands will also get their source operands swapped if that lets it use the 2-byte VEX prefix form instead of the 3-byte one. Also, certain forms of AND as well as OR with the same (register) operand specified twice get changed to TEST. Switching up the fit, iconic behavior 💅
• -Os — everything -O2 does, plus it encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate.
• -O0 — turns this optimization OFF. periodt.

---

The following options are available when as is configured for the Ubicom IP2K series.

• -mip2022ext — says the extended IP2022 instructions are allowed.
• -mip2022 — restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones.

---

The following options are available when as is configured for the Renesas M32C and M16C processors.

• -m32c — assemble M32C instructions.
• -m16c — assemble M16C instructions (this one's the default).
• -relax — enable support for link-time relaxations.
• -h-tick-hex — support H'00 style hex constants in addition to 0x00 style. 🍓

---

The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series.

• --m32rx — specify which processor in the M32R family is the target. Default is normally the M32R, but this option switches it up to the M32RX. ✨
• --warn-explicit-parallel-conflicts or --Wp — produce warning messages when questionable parallel constructs are encountered.
• --no-warn-explicit-parallel-conflicts or --Wnp — do NOT produce warning messages when questionable parallel constructs are encountered. silence is golden 🤫

---

The following options are available when as is configured for the Motorola 68000 series.

• -l — shorten references to undefined symbols, down to one word instead of two.
• -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 — specify what processor in the 68000 family is the target. Default is normally the 68020, but this can be changed at configuration time.
• -m68881 | -m68882 | -mno-68881 | -mno-68882 — the target machine does (or does not) have a floating-point coprocessor. Default is to assume a coprocessor for 68020, 68030, and cpu32. Even though the basic 68000 isn't compatible with the 68881, you CAN specify a combo of the two, since it's possible to emulate the coprocessor instructions with the main processor. 🧚
• -m68851 | -mno-68851 — the target machine does (or does not) have a memory-management unit coprocessor. Default is to assume an MMU for 68020 and up.

For details about the PDP-11 machine dependent features options, see PDP-11-Options.

• -mpic | -mno-pic — generate position-independent (or position-dependent) code. Default is -mpic.
• -mall, -mall-extensions — enable all instruction set extensions. This is the default. ✨
• -mno-extensions — disable all instruction set extensions.
• -mextension | -mno-extension — enable (or disable) a particular instruction set extension.
• -mcpu — enable the instruction set extensions supported by a particular CPU, and disable all other extensions.
• -mmachine — enable the instruction set extensions supported by a particular machine model, and disable all other extensions.

---

The following options are available when as is configured for a picoJava processor.

• -mb — generate "big endian" format output.
• -ml — generate "little endian" format output.

---

The following options are available when as is configured for a PRU processor.

• -mlink-relax — assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they're all zeros, then LD would shorten the LDI32 instruction to a single LDI. In that case, as will output DIFF relocations for diff expressions.
• -mno-link-relax — assume that LD would NOT optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted.
• -mno-warn-regname-label — don't warn if a label name matches a register name. Usually assembler programmers WANT this warning to be emitted. C compilers may want to turn it off though. 🙈
• -mcore-revision=revision — specifies the PRU core revision to assemble for. The recognized revisions are: "V1", "V2", "V3" and "V4". The assembler defaults to "V3". ⭐

---

The following options are available when as is configured for a MIPS processor.

• -G num — sets the largest size of an object that can be referenced implicitly with the "gp" register. It's only accepted for targets that use ECOFF format, like a DECstation running Ultrix. Default value is 8.
• -EB — generate "big endian" format output.
• -EL — generate "little endian" format output.
• -mips1, -mips2, -mips3, -mips4, -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, -mips64r6 — generate code for a particular MIPS Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an alias for -march=r8000. And -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. the whole lineup fr fr 💜
• -march=cpu — generate code for a particular MIPS CPU.
• -mtune=cpu — schedule and tune for a particular MIPS CPU.
• -mfix7000, -mno-fix7000 — cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
• -mfix-rm7000, -mno-fix-rm7000 — cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.
• -mfix-r5900, -mno-fix-r5900 — do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer, and always schedule a nop instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. 💀 we love a hardware oopsie
• -mdebug, -no-mdebug — cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections.
• -mpdr, -mno-pdr — control generation of .pdr sections.
• -mgp32, -mfp32 — register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers. 💅
• -mgp64, -mfp64 — normally the register sizes get inferred from the ISA and the ABI, but these two flags just force a whole group of registers to be treated as 64 bits wide, always, no takebacks. -mgp64 is the one that controls the size of the general-purpose registers, and -mfp64 handles the floating-point registers. 💅
• -mfpxx — same deal, register sizes are normally inferred from the ISA and ABI, but if you use this flag in combination with -mabi=32, you unlock an ABI variant that will operate correctly with floating-point registers that are 32 or 64 bits wide. Flexible queen. 🦋
• -modd-spreg, -mno-odd-spreg — enables the use of floating-point operations on the odd-numbered single-precision registers when the ISA supports it. Heads up: -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg.
• -mips16, -no-mips16 — generate code for the MIPS 16 processor. This is equivalent to putting .module mips16 at the start of the assembly file. -no-mips16 turns it off.
• -mmips16e2, -mno-mips16e2 — enables the use of MIPS16e2 instructions in MIPS16 mode. Equivalent to putting .module mips16e2 at the start of the assembly file. -mno-mips16e2 turns it off.
• -mmicromips, -mno-micromips — generate code for the microMIPS processor. Equivalent to putting .module micromips at the start of the assembly file. -mno-micromips turns it off, and that is equivalent to putting .module nomicromips at the start of the assembly file.
• -msmartmips, -mno-smartmips — enables the SmartMIPS extension to the MIPS32 instruction set. Equivalent to putting .module smartmips at the start of the assembly file. -mno-smartmips turns it off.
• -mips3d, -no-mips3d — generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns it off.
• -mdmx, -no-mdmx — generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns it off.
• -mdsp, -mno-dsp — generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns it off.
• -mdspr2, -mno-dspr2 — generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns it off.
• -mdspr3, -mno-dspr3 — generate code for the DSP Release 3 Application Specific Extension. This option implies -mdsp and -mdspr2. This tells the assembler to accept DSP Release 3 instructions. -mno-dspr3 turns it off.
• -mmsa, -mno-msa — generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. -mno-msa turns it off.
• -mxpa, -mno-xpa — generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions. -mno-xpa turns it off.
• -mmt, -mno-mt — generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns it off.
• -mmcu, -mno-mcu — generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. -mno-mcu turns it off.
• -mcrc, -mno-crc — generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. This tells the assembler to accept CRC instructions. -mno-crc turns it off.
• -mginv, -mno-ginv — generate code for the Global INValidate (GINV) Application Specific Extension. This tells the assembler to accept GINV instructions. -mno-ginv turns it off.
• -mloongson-mmi, -mno-loongson-mmi — generate code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. This tells the assembler to accept MMI instructions. -mno-loongson-mmi turns it off.
• -mloongson-cam, -mno-loongson-cam — generate code for the Loongson Content Address Memory (CAM) instructions. This tells the assembler to accept Loongson CAM instructions. -mno-loongson-cam turns it off.
• -mloongson-ext, -mno-loongson-ext — generate code for the Loongson EXTensions (EXT) instructions. This tells the assembler to accept Loongson EXT instructions. -mno-loongson-ext turns it off.
• -mloongson-ext2, -mno-loongson-ext2 — generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies -mloongson-ext. This tells the assembler to accept Loongson EXT2 instructions. -mno-loongson-ext2 turns it off.
• -minsn32, -mno-insn32 — only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions. Equivalent to putting .set insn32 at the start of the assembly file. -mno-insn32 turns it off, and that's equivalent to putting .set noinsn32 at the start of the assembly file. By default -mno-insn32 is selected, so all instructions are fair game. 👑
• --construct-floats, --no-construct-floats — --no-construct-floats disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default --construct-floats is selected, which allows construction of these floating point constants.
• --relax-branch, --no-relax-branch — --relax-branch enables the relaxation of out-of-range branches. By default --no-relax-branch is selected, which means any out-of-range branches straight up produce an error. 😭
• -mignore-branch-isa, -mno-ignore-branch-isa — ignore branch checks for invalid transitions between ISA modes. The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. So GAS has checks implemented that verify in branch assembly that the two ISA modes match. -mignore-branch-isa disables those checks. By default -mno-ignore-branch-isa is selected, so any invalid branch requiring a transition between ISA modes produces an error.
• -mnan=encoding — pick between the IEEE 754-2008 NaN encoding format (-mnan=2008) and the legacy one (-mnan=legacy). The legacy one is the default.
• --emulation=name — this option used to be for switching between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. It's just kept around for backwards compatibility, bestie. 🫶

The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferred options instead.

• -nocpp — as ignores this option. It's accepted for compatibility with the native tools. That's it. That's the whole thing. 💀
• --trap, --no-trap, --break, --no-break — these control how to deal with multiplication overflow and division by zero. --trap or --no-break (which are synonyms) take a trap exception, and they only work for Instruction Set Architecture level 2 and higher. --break or --no-trap (also synonyms, and the default) take a break exception.
• -n — when this option is used, as will issue a warning every time it generates a nop instruction from a macro.

---

Okay so if as is configured for a LoongArch processor, these are the options you get:

• -fpic, -fPIC — generate position-independent code
• -fno-pic — don't generate position-independent code (this is the default)

---

And if as is configured for a Meta processor:

• -mcpu=metac11 — generate code for Meta 1.1.
• -mcpu=metac12 — generate code for Meta 1.2.
• -mcpu=metac21 — generate code for Meta 2.1.
• -mfpu=metac21 — allow code to use FPU hardware of Meta 2.1.

See the info pages for documentation of the MMIX-specific options.

---

The following options are available when as is configured for a NDS32 processor. Get comfy, there's a whole roster: 🌸

• -O1 — optimize for performance.
• -Os — optimize for space.
• -EL — produce little endian data output.
• -EB — produce little endian data output.

Not a typo on my end, bestie — that's literally what the page says for -EB. Write it down exactly as it is. 🙈

• -mpic — generate PIC.
• -mno-fp-as-gp-relax — suppress fp-as-gp relaxation for this file.
• -mb2bb-relax — back-to-back branch optimization.
• -mno-all-relax — suppress all relaxation for this file.
• -march=<arch name> — assemble for architecture <arch name>, which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.
• -mbaseline=<baseline> — assemble for baseline <baseline>, which could be v2, v3, v3m.
• -mfpu-freg=FREG — specify a FPU configuration:

0      8 SP /  4 DP registers
1     16 SP /  8 DP registers
2     32 SP / 16 DP registers
3     32 SP / 32 DP registers

• -mabi=abi — specify a abi version, <abi> could be v1, v2, v2fp, v2fpp.
• -m[no-]mac — enable/disable Multiply instructions support.
• -m[no-]div — enable/disable Divide instructions support.
• -m[no-]16bit-ext — enable/disable 16-bit extension
• -m[no-]dx-regs — enable/disable d0/d1 registers
• -m[no-]perf-ext — enable/disable Performance extension
• -m[no-]perf2-ext — enable/disable Performance extension 2
• -m[no-]string-ext — enable/disable String extension
• -m[no-]reduced-regs — enable/disable Reduced Register configuration (GPR16) option
• -m[no-]audio-isa-ext — enable/disable AUDIO ISA extension
• -m[no-]fpu-sp-ext — enable/disable FPU SP extension
• -m[no-]fpu-dp-ext — enable/disable FPU DP extension
• -m[no-]fpu-fma — enable/disable FPU fused-multiply-add instructions
• -mall-ext — turn on all extensions and instructions support ✨ (yes, all of them, she does not hold back)

---

The following options are available when as is configured for a PowerPC processor:

• -a32 — generate ELF32 or XCOFF32.
• -a64 — generate ELF64 or XCOFF64.
• -K PIC — sets EF_PPC_RELOCATABLE_LIB in the ELF flags. 💅
• -mpwrx | -mpwr2 — gen code for POWER/2 (RIOS2).
• -mpwr — gen code for POWER (RIOS1).
• -m601 — gen code for PowerPC 601.
• -mppc, -mppc32, -m603, -m604 — gen code for PowerPC 603/604.
• -m403, -m405 — gen code for PowerPC 403/405.
• -m440 — gen code for PowerPC 440. BookE plus some 405 instructions, bestie.
• -m464 — gen code for PowerPC 464.
• -m476 — gen code for PowerPC 476.
• -m7400, -m7410, -m7450, -m7455 — gen code for PowerPC 7400/7410/7450/7455.
• -m750cl, -mgekko, -mbroadway — gen code for PowerPC 750CL/Gekko/Broadway.
• -m821, -m850, -m860 — gen code for PowerPC 821/850/860.
• -mppc64, -m620 — gen code for PowerPC 620/625/630.
• -me200z2, -me200z4 — gen code for e200 variants: e200z2 comes with LSP, e200z4 comes with SPE. 👑
• -me300 — gen code for the PowerPC e300 family.
• -me500, -me500x2 — gen code for the Motorola e500 core complex.
• -me500mc — gen code for the Freescale e500mc core complex.
• -me500mc64 — gen code for the Freescale e500mc64 core complex.
• -me5500 — gen code for the Freescale e5500 core complex.
• -me6500 — gen code for the Freescale e6500 core complex.
• -mlsp — turns on LSP instructions. Heads up: this disables SPE and SPE2. 💀
• -mspe — gen code for Motorola SPE instructions. Also heads up: this disables LSP.
• -mspe2 — gen code for Freescale SPE2 instructions. And yeah: disables LSP.
• -mtitan — gen code for the AppliedMicro Titan core complex.
• -mppc64bridge — gen code for PowerPC 64, bridge insns included.
• -mbooke — gen code for 32-bit BookE.
• -ma2 — gen code for the A2 architecture.
• -maltivec — gen code for processors that have AltiVec instructions. ✨
• -mvle — gen code for Freescale PowerPC VLE instructions.
• -mvsx — gen code for processors with Vector-Scalar (VSX) instructions.
• -mhtm — gen code for processors with Hardware Transactional Memory instructions.
• -mpower4, -mpwr4 — gen code for Power4 architecture.
• -mpower5, -mpwr5, -mpwr5x — gen code for Power5 architecture.
• -mpower6, -mpwr6 — gen code for Power6 architecture.
• -mpower7, -mpwr7 — gen code for Power7 architecture.
• -mpower8, -mpwr8 — gen code for Power8 architecture.
• -mpower9, -mpwr9 — gen code for Power9 architecture.
• -mpower10, -mpwr10 — gen code for Power10 architecture.
• -mpower11, -mpwr11 — gen code for Power11 architecture.
• -mfuture — gen code for the 'future' architecture. yes the quotes are literally in the name, we love a mysterious queen 🔮
• -mcell — gen code for the Cell Broadband Engine architecture.
• -mcell — gen code for the Cell Broadband Engine architecture. (yep, it's listed twice in the original and I am not the one who's gonna erase her, she said it twice so it stays twice 💅)
• -mcom — gen code Power/PowerPC common instructions.
• -many — gen code for any architecture (PWR/PWRX/PPC). the "idc just make it work" option fr fr
• -mregnames — allow symbolic names for registers.
• -mno-regnames — do not allow symbolic names for registers. 🚫
• -mrelocatable — support for GCC's -mrelocatable option.
• -mrelocatable-lib — support for GCC's -mrelocatable-lib option.
• -memb — sets the PPC_EMB bit in ELF flags.
• -mlittle, -mlittle-endian, -le — gen code for a little endian machine.
• -mbig, -mbig-endian, -be — gen code for a big endian machine.
• -nops=count — if an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops. lowkey smart 🧠

---

okay bestie, deep breath, we're switching processors now 💜

The following options are available when as is configured for a RISC-V processor.

• -fpic | -fPIC — generate position-independent code
• -fno-pic — don't generate position-independent code (default)
• -march=ISA|Profiles|Profiles_ISA — select the base isa, as specified by ISA or Profiles or Profies_ISA. for example -march=rv32ima, -march=RVI20U64, -march=RVI20U64_d. if this option and the architecture attributes aren't set, then the assembler checks the default configure setting --with-arch=ISA.
• -misa-spec=ISAspec — select the default isa spec version. if the version of ISA isn't set by -march, then the assembler helps set the version according to the default chosen spec. if this option isn't set, then the assembler checks the default configure setting --with-isa-spec=ISAspec.
• -mpriv-spec=PRIVspec — select the privileged spec version. we can decide whether the CSR is valid or not according to the chosen spec. if this option and the privilege attributes aren't set, then the assembler checks the default configure setting --with-priv-spec=PRIVspec.
• -mabi=ABI — selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or "e" to indicate the soft-float calling convention ("e" indicates a soft-float RVE ABI).
• -mrelax — take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default ✨)
• -mno-relax — don't do linker relaxations.
• -march-attr — generate the default contents for the riscv elf attribute section if the .attribute directives aren't set. this section records the info a linker or runtime loader needs to check compatibility. that info includes the ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of the privileged specification.
• -mno-arch-attr — don't generate the default riscv elf attribute section if the .attribute directives aren't set.
• -mcsr-check — enable the CSR checking for the ISA-dependent CRS and the read-only CSR. the ISA-dependent CSR are only valid when the specific ISA is set. the read-only CSR can not be written by the CSR instructions. 🚫
• -mno-csr-check — don't do CSR checking.
• -mlittle-endian — gen code for a little endian machine.
• -mbig-endian — gen code for a big endian machine.

for the RX-specific options, go see the info pages, bestie — this manpage is not the one 📖

---

The following options are available when as is configured for the s390 processor family.

• -m31 | -m64 — select the word size, either 31/32 bits or 64 bits.
• -mesa | -mzarch — select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).
• -march=processor — specify which s390 processor variant is the target: g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or z17 (or arch15). that's a whole lineup, periodt 👑
• -mregnames | -mno-regnames — allow or disallow symbolic names for registers.
• -mwarn-areg-zero — warn whenever the operand for a base or index register has been specified but evaluates to zero. 👀
• -mwarn-regtype-mismatch=strict | -mwarn-regtype-mismatch=relaxed | -mwarn-regtype-mismatch=no | -mno-warn-regtype-mismatch — controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type. the default (which you can restore by using the relaxed argument) is to perform relaxed register name type checks, which allow floating point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands, and vector register (VR) names %v0 to %v15 to be specified as argument to floating point register (FPR) operands. that's acceptable because the FPR are embedded into the lower half of the VR. using the strict argument, strict register name type checks are performed. the no argument, which is equivalent to -mno-warn-regtype-mismatch, disables any register name type checks. 😌

---

The following options are available when as is configured for a TMS320C6000 processor.

• -march=arch — enable (only) instructions from architecture arch. by default, all instructions are permitted.

the following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x".

• -mdsbt | -mno-dsbt — the -mdsbt option makes the assembler generate the "Tag_ABI_DSBT" attribute with a value of 1, indicating that the code is using DSBT addressing. the -mno-dsbt option, the default, makes the tag have a value of 0, indicating that the code does not use DSBT addressing. the linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. ⚠️
• -mpid=no | -mpid=near | -mpid=far — the -mpid= option makes the assembler generate the "Tag_ABI_PID" attribute with a value indicating the form of data addressing used by the code. -mpid=no, the default, indicates position-dependent data addressing, -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing, and -mpid=far indicates position-independent addressing with GOT accesses using far DP addressing. the linker will emit a warning if objects built with different settings of this option are linked together. ⚠️
• -mpic | -mno-pic — the -mpic option makes the assembler generate the "Tag_ABI_PIC" attribute with a value of 1, indicating that the code is using position-independent code addressing. the "-mno-pic" option, the default, makes the tag have a value of 0, indicating position-dependent code addressing. the linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together. ⚠️
• -mbig-endian | -mlittle-endian — gen code for the specified endianness. the default is little-endian.

---

The following options are available when as is configured for a TILE-Gx processor.

• -m32 | -m64 — select the word size, either 32 bits or 64 bits.
• -EB | -EL — select the endianness, either big-endian (-EB) or little-endian (-EL).

---

The following option is available when as is configured for a Visium processor.

• -mtune=arch — this option specifies the target architecture. if an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. 💀

the following names are recognized: "mcm24" "mcm" "gr5" "gr6"

---

The following options are available when as is configured for an Xtensa processor. 🦋

• --text-section-literals, --no-text-section-literals — okay so this is the literal pool vibe check 💅 By default you get --no-text-section-literals, which chucks literals into their own separate sections in the output file, so the literal pool can live in a data RAM/ROM. But with --text-section-literals, the literals get scattered inside the text section, keeping them as close as possible to the stuff that references them. Why would you want that? Because for big assembly files, the literals would otherwise be out of range of the L32R instructions in the text section 😭 Literals get grouped into pools following .literal_position directives, or right before ENTRY instructions. Heads up: these options only touch literals referenced through PC-relative L32R instructions — literals for absolute-mode L32R instructions are handled separately, no cap.
• --auto-litpools, --no-auto-litpools — again with the literal pools, bestie, different flavor ✨ Default is --no-auto-litpools, which (when --text-section-literals isn't around) puts literals in separate sections in the output file so the literal pool can go in a data RAM/ROM. With --auto-litpools, literals get interspersed in the text section to keep them as close as possible to their references, and you don't even need explicit .literal_position directives — iconic. This may be necessary for very large functions, where a single literal pool at the top of the function might not be reachable by L32R instructions at the end 🫠 Same disclaimer as above: only PC-relative L32R literals are affected; absolute-mode L32R literals are handled separately. And when you use it together with --text-section-literals, --auto-litpools takes precedence. periodt.
• --absolute-literals, --no-absolute-literals — tells the assembler whether L32R instructions use absolute or PC-relative addressing. If your processor has the absolute addressing option, the default is to use absolute L32R relocations. Otherwise, only PC-relative L32R relocations can be used. that's it, that's the whole thing 💖
• --target-align, --no-target-align — turn automatic alignment on or off, which reduces branch penalties at some cost in code size. Enabled by default, slay. But note: the assembler will always align instructions like LOOP that have fixed alignment requirements, no matter what you say 🌸
• --longcalls, --no-longcalls — enable or disable transformation of call instructions so calls can reach across a greater range of addresses. Use this when call targets can potentially be out of range. Yes it may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range 🙌 Default is --no-longcalls.
• --transform, --no-transform — enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. Default is --transform, and --no-transform should only be used in those rare cases when the instructions must be exactly as specified in the assembly source — don't be chaotic about it. Oh and heads up: using --no-transform causes out of range instruction operands to be errors 💀
• --rename-section oldname=newname — renames the oldname section to newname. You can use this option multiple times to rename multiple sections. bougie and efficient 🎀
• --trampolines, --no-trampolines — enable or disable transformation of jump instructions so jumps can reach across a greater range of addresses. Use it when jump targets can potentially be out of range. In the absence of such jumps, this option doesn't affect code size or performance at all. Default is --trampolines ✨
• --abi-windowed, --abi-call0 — choose the ABI tag written to the .xtensa.info section. The ABI tag indicates the ABI of the assembly code. If you try to link object files with inconsistent ABI tags, the linker issues a warning 🙈 The default ABI is chosen by the Xtensa core configuration.

---

The following options are available when as is configured for a Z80 processor.

🌈 Z80 Dependent Features 🌈

🦋 Command-line Options 🦋

• -march=CPU[-EXT...][+EXT...] — this one specifies the target processor. If you try to assemble an instruction that won't execute on the target processor, the assembler will issue an error message, sorry bestie. The processor names it knows are: z80, z180, ez80, gbz80, z80n, r800 👑

And beyond the basic instruction set, you can tell the assembler to accept some extension mnemonics. Like, for example, -march=z180+sli+infc extends z180 with SLI instructions and IN F,(C). The extensions currently supported are: full (all known instructions), adl (ADL CPU mode by default, eZ80 only), sli (instruction known as SLI, SLL or SL1), xyhl (instructions with halves of index registers: IXL, IXH, IYL, IYH), xdcb (instructions like RotOp (II+d),R and BitOp n,(II+d),R), infc (instruction IN F,(C) or IN (C)), outc0 (instruction OUT (C),0).

And here's the twist 🌀 rather than extending a basic instruction set, extension mnemonics that start with - revoke the respective functionality: -march=z80-full+xyhl first removes all default extensions and then adds support for index register halves only.

If you don't specify this option at all, then -march=z80+xyhl+infc is assumed 💅

• -local-prefix=prefix — marks all labels with the specified prefix as local. But (and this is the sneaky part) such a label can still be marked global explicitly in the code. This option does not change the default local label prefix .L, it just adds a new one 🌸
• -colonless — accept colonless labels. All symbols at the beginning of a line are treated as labels. living dangerously, love that for you 💀
• -sdcc — accept assembler code produced by SDCC 🫶
• -fp-s=FORMAT — single precision floating point numbers format. Default: ieee754 (32 bit) ⭐
• -fp-d=FORMAT — double precision floating point numbers format. Default: ieee754 (64 bit) ⭐

---

💜 SEE ALSO 💜

gcc(1), ld(1), and the Info entries for binutils and ld. go read those next, iykyk 📚

---

👑 COPYRIGHT 👑

Copyright (c) 1991-2026 Free Software Foundation, Inc.

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".

---

that's the whole page, bestie!! you made it to the end 🎉 this one's from binutils-2.47, dated 2026-09-05, and it lives as AS(1) in the manual. mwah, go assemble something iconic 💖✨