AS(1)
💅 AS(1) 💅
okay so this is AS(1) from GNU Development Tools — aka the portable GNU assembler. She's iconic, she's lowkey everywhere, and she's here to turn your assembly into object files. Let's get into it, bestie. 🫶
🌸 NAME 🌸
AS — the portable GNU assembler.
That's the name. That's the whole vibe. No cap. ✨
🎀 SYNOPSIS 🎀
bestie, here's the full invocation shape. I'm keeping every bracket and option exactly as-is so nobody's build breaks and blames me:
as [-a[cdghilns][=file]]
[--alternate]
[--compress-debug-sections] [--nocompress-debug-sections]
[-D]
[--dump-config]
[--debug-prefix-map old=new]
[--defsym sym=val]
[--elf-stt-common=[no|yes]]
[--emulation=name]
[-f]
[-g] [--gstabs] [--gstabs+]
[--gdwarf-<N>] [--gdwarf-sections]
[--gdwarf-cie-version=VERSION]
[--generate-missing-build-notes=[no|yes]]
[--gsframe] [--gsframe=[no|yes]]
[--gsframe-3]
[--hash-size=N]
[--help] [--target-help]
[--info] [--no-info]
[-I dir]
[-J]
[-K]
[--keep-locals]
[-L]
[--listing-lhs-width=NUM]
[--listing-lhs-width2=NUM]
[--listing-rhs-width=NUM]
[--listing-cont-lines=NUM]
[--multibyte-handling=[allow|warn|warn-sym-only]]
[--no-pad-sections]
[-o objfile] [-R]
[--reloc-section-sym=[all|internal|none]]
[--scfi=experimental]
[--sectname-subst]
[--size-check=[error|warning]]
[--statistics]
[-v] [--verbose]
[-version] [--version]
[-W] [--no-warn] [--warn] [--fatal-warnings]
[-w] [-x]
[-Z] [@FILE]
[target-options]
[--|files ...]🎯 TARGET 🎯
Target-specific options are their own whole multiverse, and I am not about to let one go missing. Here's every target group, with the option strings kept exactly as they should be. 💖
Target AArch64 options
[-EB|-EL]
[-mabi=ABI]Target Alpha options
[-mcpu]
[-mdebug | -no-mdebug]
[-replace | -noreplace]
[-relax] [-g] [-Gsize]
[-F] [-32addr]Target ARC options
[-mcpu=cpu]
[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
[-mcode-density]
[-mrelax]
[-EB|-EL]Target ARM options
[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
-mapcs-reentrant]
[-mthumb-interwork] [-k]Target Blackfin options
[-mcpu=processor[-sirevision]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]Target BPF options
[-EL] [-EB]Target CRIS options
[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
[--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]Target C-SKY options
[-march=arch] [-mcpu=cpu]
[-EL] [-mlittle-endian] [-EB] [-mbig-endian]
[-fpic] [-pic]
[-mljump] [-mno-ljump]
[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
[-mnolrw ] [-mno-lrw]
[-melrw] [-mno-elrw]
[-mlaf ] [-mliterals-after-func]
[-mno-laf] [-mno-literals-after-func]
[-mlabr] [-mliterals-after-br]
[-mno-labr] [-mnoliterals-after-br]
[-mistack] [-mno-istack]
[-mhard-float] [-mmp] [-mcp] [-mcache]
[-msecurity] [-mtrust]
[-mdsp] [-medsp] [-mvdsp]Target D10V options
[-O]Target D30V options
[-O|-n|-N]Target EPIPHANY options
[-mepiphany|-mepiphany16]Target H8/300 options
[-h-tick-hex]Target i386 options
[--32|--x32|--64] [-n]
[-march=CPU[+EXTENSION...]] [-mtune=CPU]Target IA-64 options
[-mconstant-gp|-mauto-pic]
[-milp32|-milp64|-mlp64|-mp64]
[-mle|mbe]
[-mtune=itanium1|-mtune=itanium2]
[-munwind-check=warning|-munwind-check=error]
[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
[-x|-xexplicit] [-xauto] [-xdebug]Target IP2K options
[-mip2022|-mip2022ext]Target M32C options
[-m32c|-m16c] [-relax] [-h-tick-hex]Target M32R options
[--m32rx|--[no-]warn-explicit-parallel-conflicts|
--W[n]p]Target M680X0 options
[-l] [-m68000|-m68010|-m68020|...]Target M68HC11 options
[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branches] [--short-branches]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]Target MCORE options
[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]Target Meta options
[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu]Target MICROBLAZE options
[-mlittle-endian] [-mbig-endian]Target MIPS options
[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot [-mvxworks-pic]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-mfp64] [-mgp64] [-mfpxx]
[-modd-spreg] [-mno-odd-spreg]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
[-mips64r3] [-mips64r5] [-mips64r6]
[-construct-floats] [-no-construct-floats]
[-mignore-branch-isa] [-mno-ignore-branch-isa]
[-mnan=encoding]
[-trap] [-no-break] [-break] [-no-trap]
[-mips16] [-no-mips16]
[-mmips16e2] [-mno-mips16e2]
[-mmicromips] [-mno-micromips]
[-msmartmips] [-mno-smartmips]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdsp] [-mno-dsp]
[-mdspr2] [-mno-dspr2]
[-mdspr3] [-mno-dspr3]
[-mmsa] [-mno-msa]
[-mxpa] [-mno-xpa]
[-mmt] [-mno-mt]
[-mmcu] [-mno-mcu]
[-mcrc] [-mno-crc]
[-mginv] [-mno-ginv]
[-mloongson-mmi] [-mno-loongson-mmi]
[-mloongson-cam] [-mno-loongson-cam]
[-mloongson-ext] [-mno-loongson-ext]
[-mloongson-ext2] [-mno-loongson-ext2]
[-minsn32] [-mno-insn32]
[-mfix7000] [-mno-fix7000]
[-mfix-rm7000] [-mno-fix-rm7000]
[-mfix-vr4120] [-mno-fix-vr4120]
[-mfix-vr4130] [-mno-fix-vr4130]
[-mfix-r5900] [-mno-fix-r5900]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]Target MMIX options
[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]Target NDS32 options
[-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
[-misa=isa] [-mabi=abi] [-mall-ext]
[-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
[-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
[-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
[-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
[-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
[-mb2bb]Target PDP11 options
[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]Target picoJava options
[-mb|-me]Target PowerPC options
[-a32|-a64]
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
-m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
-mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
-me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
-mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
-mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
[-many] [-maltivec|-mvsx|-mhtm|-mvle]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
[-nops=count]Target PRU options
[-link-relax]
[-mnolink-relax]
[-mno-warn-regname-label]Target RISC-V options
[-fpic|-fPIC|-fno-pic]
[-march=ISA|Profiles|Profiles_ISA]
[-mabi=ABI]
[-mlittle-endian|-mbig-endian]Target RL78 options
[-mg10]
[-m32bit-doubles|-m64bit-doubles]Target RX options
[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]Target s390 options
[-m31|-m64] [-mesa|-mzarch] [-march=CPU]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]
[-mwarn-regtype-mismatch=strict
-mwarn-regtype-mismatch=relaxed
-mwarn-regtype-mismatch=no
-mno-warn-regtype-mismatch]Target SCORE options
[-EB][-EL][-FIXDD][-NWARN]
[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
[-march=score7][-march=score3]
[-USE_R1][-KPIC][-O0][-G num][-V]Target SPARC options
[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
-Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
-Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
-Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
-Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
-Asparcvisr|-Asparc5]
[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
-xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
-xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
-xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
-xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
-xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
-bump]
[-32|-64]
[--enforce-aligned-data][--dcti-couples-detect]Target TIC54X options
[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]Target TIC6X options
[-march=arch] [-mbig-endian|-mlittle-endian]
[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
[-mpic|-mno-pic]Target TILE-Gx options
[-m32|-m64][-EB][-EL]Target Visium options
[-mtune=arch]Target Xtensa options
[--[no-]text-section-literals] [--[no-]auto-litpools]
[--[no-]absolute-literals]
[--[no-]target-align] [--[no-]longcalls]
[--[no-]transform]
[--rename-section oldname=newname]
[--[no-]trampolines]
[--abi-windowed|--abi-call0]Target Z80 options
[-march=CPU[-EXT][+EXT]]
[-local-prefix=PREFIX]
[-colonless]
[-sdcc]
[-fp-s=FORMAT]
[-fp-d=FORMAT]✨ DESCRIPTION ✨
okay so bestie, plot twist: GNU as isn't just one assembler, it's literally a whole family of assemblers 💅. If you've used the GNU assembler on one architecture, the vibe on another architecture will feel super familiar — like switching group chats but everyone still uses the same emojis. Every version shares a ton with the others, including object file formats, most assembler directives (which the cool kids call pseudo-ops), and the assembler syntax itself. 🫶
The main character energy of as is assembling the output of the GNU C compiler gcc so the linker ld can do its thing. But ngl, the goal is bigger than that: they've tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions? They're documented explicitly, no cap. That said — and this is the important bit — it does not mean as always uses the same syntax as some other assembler for the same architecture. Like, we literally know of several mutually incompatible versions of 680x0 assembly language syntax 💀.
Every single time you run as, it assembles exactly one source program. That source program is made up of one or more files. (And yes, standard input totally counts as a file, bestie.)
You hand as a command line with zero or more input file names, and the input files get read from left file name to right. Any command-line argument (in any position) that doesn't have some special meaning? Congrats, it's an input file name now 🌸.
If you give as no file names at all, it tries to read one input file from as standard input — which is normally your terminal, bestie 😭. You may have to type ctl-D to tell as there's no more program left to assemble.
Use -- if you need to explicitly name the standard input file in your command line. (Yes, that's the move 👑.)
If the source is empty, as produces a small, empty object file. Tiny. Iconic. Minimalist. 🎀
as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically, jsyk. Here's the difference: warnings report an assumption that was made so as could keep assembling a flawed program (it's trying its best, okay 😭), while errors report a grave problem that stops the assembly. Periodt.
If you're invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. Those assembler arguments have to be separated from each other (and from -Wa) by commas. Example time:
gcc -c -g -O -Wa,-alh,-L file.cThat passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain internal symbols in the symbol table). Slay.
Usually though? You do not need to use this -Wa mechanism, because many compiler command-line options are automatically passed to the assembler by the compiler. (And if you're nosy, you can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler. Detective mode 🔍.)
✨ OPTIONS ✨
@file— read command-line options from file. The options that get read are inserted in place of the original@fileoption. If file doesn't exist, or can't be read, then the option is treated literally and not removed 🙈.
Options inside file are separated by whitespace. A whitespace character can be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) can be included by prefixing the character you want with a backslash. And the file may itself contain additional @file options — any of those get processed recursively. It's giving inception 🌀.
-a[cdghilmns]— turn on listings, in any of a variety of ways:-ac— omit false conditionals-ad— omit debugging directives-ag— include general information, likeasversion and options passed-ah— include high-level source-al— include assembly-ali— include assembly with ginsn-am— include macro expansions-an— omit forms processing-as— include symbols=file— set the name of the listing file
You can combine these options; for example, use -aln for an assembly listing without forms processing. The =file option, if you use it, must be the last one. By itself, -a defaults to -ahls. 💖
--alternate— begin in alternate macro mode.--compress-debug-sections— compress DWARF debug sections using zlib withSHF_COMPRESSEDfrom the ELF ABI. Heads up: the resulting object file may not be compatible with older linkers and object file utilities ⚠️. Also note — if compression would make a given section larger, then it is not compressed.--compress-debug-sections=none--compress-debug-sections=zlib--compress-debug-sections=zlib-gnu--compress-debug-sections=zlib-gabi--compress-debug-sections=zstd— these options control how DWARF debug sections get compressed:--compress-debug-sections=noneis equivalent to--nocompress-debug-sections.--compress-debug-sections=zliband--compress-debug-sections=zlib-gabiare equivalent to--compress-debug-sections.--compress-debug-sections=zlib-gnucompresses DWARF debug sections using the obsoleted zlib-gnu format (vintage, but not in the cute way 👀). The debug sections get renamed to begin with.zdebug.--compress-debug-sections=zstdcompresses DWARF debug sections using zstd.
Note — if compression would actually make a section larger, then it is neither compressed nor renamed. The assembler is not about to make your file bigger for the aesthetic 💅.
--nocompress-debug-sections— do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this.-D— enable debugging in target specific backends, if supported. Otherwise it's just ignored. And even when it's ignored, this option is still accepted for script compatibility with calls to other assemblers. (It's showing up to the party whether or not it gets let in 🫶.)--debug-prefix-map old=new— when assembling files in directory old, record debugging information describing them as in new instead.--defsym sym=value— define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading0xindicates a hexadecimal value, and a leading0indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a.setpseudo-op.--dump-config— displays how the assembler is configured and then exits. Peek behind the curtain, bestie ✨.--elf-stt-common=no--elf-stt-common=yes— these options control whether the ELF assembler should generate common symbols with theSTT_COMMONtype. The default can be controlled by a configure option--enable-elf-stt-common.--emit-local-absolute— emit even pre-defined (local) absolute symbols to the outgoing symbol table. Note that this isn't the exact opposite of--strip-local-absolute👀.--emulation=name— if the assembler is configured to support multiple different target configurations, then this option can be used to select the desired form.-f— "fast" — skip whitespace and comment preprocessing (assume source is compiler output). Zoom zoom 🔥.-g--gen-debug— generate debugging information for each assembler source line using whichever debug format the target prefers. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a.debug_infoand.debug_linesection is only emitted when the assembly file doesn't generate one itself.--gstabs— generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.--gstabs+— generate stabs debugging information for each assembler line, with GNU extensions that probably onlygdbcan handle, and that could make other debuggers crash or refuse to read your program 😭. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time.--gdwarf-2— generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note — this option is only supported by some targets, not all of them 🙈.--gdwarf-3— same as the--gdwarf-2option, except it allows for the possibility of generating extra debug information as per version 3 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis.--gdwarf-4— same as the--gdwarf-2option, except it allows for the possibility of generating extra debug information as per version 4 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis.--gdwarf-5— same as the--gdwarf-2option, except it allows for the possibility of generating extra debug information as per version 5 of the DWARF specification. Note — enabling this option does not guarantee the generation of any extra information; the choice to do so is on a per target basis.--gdwarf-sections— instead of creating a.debug_linesection, create a series of.debug_line.foosections where foo is the name of the corresponding code section. For example, a code section called.text.funcwill have its dwarf line number information placed into a section called.debug_line.text.func. If the code section is just called.textthen the debug line section will still just be called.debug_linewithout any suffix. Consistent, we love to see it 💅.--gdwarf-cie-version=version— control which version of DWARF Common Information Entries (CIEs) get produced. When this flag isn't specified the default is version 1, though some targets can modify this default. Other possible values for version are3or4.--generate-missing-build-notes=yes--generate-missing-build-notes=no— these options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the--enable-generate-build-notesconfigure option.--gsframe--gsframe--gsframe=no--gsframe=yes— create a.sframesection from CFI directives. The explicit--gsframe=yesoption behaves the same as--gsframe. Generation can be suppressed with--gsframe=no. The default can be controlled by a configure option--enable-default-sframe. The current version of the emitted SFrame stack trace data isSFRAME_VERSION_3. 🦋--gsframe-3— generate SFrame stack trace information as per Version 3 of the specification.--hash-size N— ignored. Supported for command line compatibility with other assemblers. (It's literally just there to be polite 🎀.)--help— print a summary of the command-line options and exit.--target-help— drops a lil summary of every target-specific option and then dips. that's it, that's the whole job 💅--info— do NOT suppress the informational messages bestie, let them speak 🗣️--no-info— okay actually, suppress the informational messages. shhh 🤫-Idir — adds dir to the search list for.includedirectives. like a little treasure map for includes 🗺️-J— do not warn about signed overflow. no thoughts, no warnings ✨-K— issues warnings when difference tables get altered for long displacements. it's giving "heads up, something moved" 🚨-L,--keep-locals— keeps internal symbols in the symbol table. these symbols start with system-specific local label prefixes, typically.Lfor ELF systems orLfor traditional a.out systems. protect the locals at all costs 🫶--listing-lhs-width=number — sets the max width (in words) of the output data column for an assembler listing to number. measure twice 📏--listing-lhs-width2=number — same energy but for the continuation lines in an assembler listing — max width in words = number 💫--listing-rhs-width=number — sets the max width of an input source line, as displayed in a listing, to number bytes. yes, bytes, not vibes 🧚--listing-cont-lines=number — sets the maximum number of lines printed in a listing for a single line of input to number + 1. the +1 is doing the most, honestly 😭--multibyte-handling=allow,--multibyte-handling=warn,--multibyte-handling=warn-sym-only,--multibyte-handling=warn_sym_only— controls how the assembler handles multibyte characters in the input, and the lore is:- the default is to allow such characters without complaint (and you can restore that default by using the
allowargument) 😌 - the
warnargument makes the assembler generate a warning message whenever any multibyte character is encountered 🔔 - the
warn-sym-onlyargument only causes a warning when a symbol is defined with a name that contains multibyte characters. references to undefined symbols will not generate a warning. very "only the main characters get flagged" of it 👑
- the default is to allow such characters without complaint (and you can restore that default by using the
--no-pad-sections— stops the assembler from padding the ends of output sections to the alignment of that section. the default is to pad the sections, but heads up: that can waste space, which might be needed on targets with tight memory constraints 👀-oobjfile — names the object-file output fromasobjfile. name your child 🍼-R— folds the data section into the text section. merging, combining, becoming one 🔥--reduce-memory-overheads— ignored. it's only there for compatibility with tools that pass the same option to both the assembler and the linker. it's giving "i'm just here so i won't get fined" 💀--reloc-section-sym=all,--reloc-section-sym=internal,--reloc-section-sym=none— controls whether relocations referencing local binding symbols get adjusted to use section symbols instead. the breakdown:all(the default) → relocations against all eligible local binding symbols are converted 🎀internal→ only relocations against internal labels (symbols matching the.Lprefix) are converted 🦋none→ no such conversions are performed. periodt 🚫
--scfi=experimental— controls whether the assembler should synthesize CFI for hand-written input. if the input already contains some synthesizable CFI directives, the assembler ignores them and emits a warning. also,--scfi=experimentalis not intended to be used for compiler-generated code, including inline assembly — that's a real caveat bestie, listen to it 🙈. this experimental support is work in progress, and only System V AMD64 ABI is supported.
each input function in assembly must begin with the .type directive, and should ideally be closed off using a .size directive. when using SCFI, each .type directive prompts GAS to start a new FDE (a.k.a., Function Descriptor Entry). this implies that with each .type directive, a previous block of instructions, if any, is finalised as a distinct FDE. lots of finalising happening, iconic behavior honestly 👑
--sectname-subst— honors substitution sequences in section names. respect the substitutions ✨--size-check=error,--size-check=warning— issue an error or a warning for an invalid ELF.sizedirective. pick your fighter 😤--statistics— prints the maximum space (in bytes) and total time (in seconds) used by assembly. the receipts 📊--strip-local-absolute— removes local absolute symbols from the outgoing symbol table. bye bestie 👋-v,--verbose— prints theasversion. casual little flex 💁♀️--version,-version— prints theasversion and exits. no further business, we're done here 🎬-W,--no-warn— suppresses warning messages. living in denial, but make it a flag 🙈--warn— don't suppress warning messages or treat them as errors. we're listening, respectfully 👂--fatal-warnings— treat warnings as errors. no chill, only consequences 💀-w— ignored. it's just there. a vibe in the option list 🫠-x— ignored. matching energy with-w💫-Z— generates an object file even after errors. chaotic but productive 🔥--files ... — standard input, or source files to assemble. the--said "everything after this is a file, don't @ me" 📁
🌸 so like, the following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64). buckle up babygirl, there are a LOT 💅
-EB— specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. big-endian stans rise 🫶-EL— specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. little-endian girlies, this one's for you 🎀-mabi=abi — specifies which ABI the source code uses. the recognized arguments areilp32andlp64, which decide the generated object file in ELF32 and ELF64 format respectively. the default islp64. choose wisely 👑-mcpu=processor[+extension...] — specifies the target processor. the assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. here's the guest list of recognized processor names:cortex-a34,cortex-a35,cortex-a53,cortex-a55,cortex-a57,cortex-a65,cortex-a65ae,cortex-a72,cortex-a73,cortex-a75,cortex-a76,cortex-a76ae,cortex-a77,cortex-a78,cortex-a78ae,cortex-a78c,cortex-a510,cortex-a520,cortex-a710,cortex-a720,ares,exynos-m1,falkor,neoverse-n1,neoverse-n2,neoverse-e1,neoverse-v1,qdf24xx,saphira,thunderx,vulcan,xgene1xgene2,cortex-r82,cortex-x1,cortex-x2,cortex-x3,cortex-x4. and the special nameallmay be used to let the assembler accept instructions valid for any supported processor, including all optional extensions. it's giving "accept everyone" 🌈
in addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.
if some implementations of a particular processor can have an extension, then those extensions are automatically enabled. consequently, you will not normally have to specify any additional extensions. the assembler's got you 😌
-march=architecture[+extension...] — specifies the target architecture. again, the assembler will issue an error message if you try to assemble an instruction which will not execute on the target architecture. recognized architecture names:armv8-a,armv8.1-a,armv8.2-a,armv8.3-a,armv8.4-aarmv8.5-a,armv8.6-a,armv8.7-a,armv8.8-a,armv8.9-a,armv8-r,armv9-a,armv9.1-a,armv9.2-a,armv9.3-a,armv9.4-aandarmv9.5-a. the whole family tree 🌳
if both -mcpu and -march are specified, the assembler will use the setting for -mcpu. if neither are specified, the assembler will default to -mcpu=all. -mcpu wins the argument, every time 😤
the architecture option can be extended with the same instruction set extension options as the -mcpu option. but unlike -mcpu, extensions are not always enabled by default. read that again bestie 👀
-mbig-obj— on PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. that's a LOT of sections, slay 💅-mverbose-error— enables verbose error messages for AArch64gas. this option is enabled by default, so like, you're already living that life ✨-mno-verbose-error— disables verbose error messages in AArch64gas. minimalism era 🤫-menable-sysreg-checking— enables error messages that are issued if an attempt is made to assemble a system register access which will not execute on the target architecture. it's a vibe check for your system registers 👑
🍓 the following options are available when as is configured for an Alpha processor. throwback era, we respect it 💜
-mcpu— specifies the target processor. if an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. this option is equivalent to the.archdirective.
the recognized processor names: 21064, 21064a, 21066, 21068, 21164, 21164a, 21164pc, 21264, 21264a, 21264b, ev4, ev5, lca45, ev5, ev56, pca56, ev6, ev67, ev68. and the special name all may be used to allow the assembler to accept instructions valid for any Alpha processor. yes, ev5 is listed twice, we don't talk about it 💀
in order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. ev4) do not. history lesson over, periodt 📚
-mdebug,-no-mdebug— enables or disables the generation of.mdebugencapsulation for stabs directives and procedure descriptors. the default is to automatically enable.mdebugwhen the first stabs directive is seen. it just knows 🧚-relax— forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. heads up though: this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. the option can still be useful in specific applications tho 🫶-replace,-noreplace— enables or disables the optimization of procedure calls, both at assemblage and at link time. these options are only available for VMS targets, and-replaceis the default. see section 1.4.1 of the OpenVMS Linker Utility Manual. homework assigned 📖-g— this option is used when the compiler generates debug information. whengccis usingmips-tfileto generate debug information for ECOFF, local labels must be passed through to the object file. otherwise this option has no effect. situational icon 💅-Gsize — a local common symbol larger than size is placed in.bss, while smaller symbols are placed in.sbss. size-based sorting, we love an organizational queen 📦-F,-32addr— these options are ignored for backward compatibility. relics. we keep them for the lore 🏺
🦋 the following options are available when as is configured for an ARC processor.
-mcpu=cpu — selects the core processor variant. short and sweet 🎀-EB|-EL— selects either big-endian (-EB) or little-endian (-EL) output. pick a lane, bestie 🌗-mcode-density— enables Code Density extension instructions. density! compact! efficient! we stan 🔥
💅 ARM, bestie — the processor-family tea
These ones show up when as is built for the ARM processor family:
-mcpu=processor[+extension...]— tells it which ARM processor variant you're targeting. Periodt.-march=architecture[+extension...]— says which ARM architecture variant the target is rocking.-mfpu=floating-point-format— picks which Floating Point architecture is the target ✨-mfloat-abi=abi— picks which floating point ABI is in use.-mthumb— turns on Thumb only instruction decoding. No ARM mixing, we're committed.-mapcs-32/-mapcs-26/-mapcs-float/-mapcs-reentrant— picks which procedure calling convention is in use. Choose your fighter 🫶-EB/-EL— selects big-endian (-EB) or little-endian (-EL) output.-mthumb-interwork— says the code was generated with interworking between Thumb and ARM code in mind. It's giving bilingual icon.-mccs— turns on CodeComposer Studio assembly syntax compatibility mode.-k— says PIC code has been generated.
🖤 Blackfin family
These ones pop up when as is configured for the Blackfin processor family:
-mcpu=processor[-sirevision]— specifies the target processor. The optional sirevision is not used in the assembler — it's literally just hanging out there so GCC can easily pass down its-mcpu=option. The assembler will throw an error message if you try to assemble an instruction that won't execute on the target processor. The recognized processor names are:bf504,bf506,bf512,bf514,bf516,bf518,bf522,bf523,bf524,bf525,bf526,bf527,bf531,bf532,bf533,bf534,bf535(not implemented yet 🙈),bf536,bf537,bf538,bf539,bf542,bf542m,bf544,bf544m,bf547,bf547m,bf548,bf548m,bf549,bf549m,bf561, andbf592.-mfdpic— assemble for the FDPIC ABI.-mno-fdpic/-mnopic— disables-mfdpic.
🧚 BPF (Linux kernel vibes)
These ones are for when as is configured for the Linux kernel BPF processor family. (Yes, the original really does drop a texinfo chapter line right here, so here it is in all its glory:)
@chapter BPF Dependent FeaturesBPF Options
-EB— says the assembler should emit big-endian eBPF.-EL— says the assembler should emit little-endian eBPF.-mdialect=dialect— specifies the assembly language dialect to recognize while assembling. The assembler supportsnormalandpseudoc.-misa-spec=spec— specifies the version of the BPF instruction set to use when assembling. The supported BPF ISA versions arev1v2,v3andv4.
The value xbpf can be specified to recognize extra instructions that are used by GCC for testing purposes. But beware, this is not valid BPF. 💀
-mno-relax— tells the assembler not to relax instructions.
Heads up bestie: if no endianness option is specified on the command line, the host endianness is used. See the info pages for documentation of the CRIS-specific options.
🦋 C-SKY cuteness
These ones are available when as is configured for the C-SKY processor family:
-march=archname— assemble for architecture archname. The--helpoption lists valid values for archname.-mcpu=cpuname— assemble for architecture cpuname. The--helpoption lists valid values for cpuname. (Yes, both say "architecture" — that's what the page says, don't come for me 🫶)-EL/-mlittle-endian— generate little-endian output.-EB/-mbig-endian— generate big-endian output.-fpic/-pic— generate position-independent code.-mljump/-mno-ljump— enable/disable transformation of the short branch instructionsjbf,jbt, andjbrtojmpi. This is a V2 processors only situation. It's ignored on CK801 and CK802 targets (they don't support thejmpiinstruction), and it's enabled by default for other processors.-mbranch-stub/-mno-branch-stub— pass throughR_CKCORE_PCREL_IMM26BY2relocations forbsrinstructions to the linker.
This one is only available for bare-metal C-SKY V2 ELF targets, where it's enabled by default. It cannot be used in code that will be dynamically linked against shared libraries. 🚨
-force2bsr/-mforce2bsr/-no-force2bsr/-mno-force2bsr— enable/disable transformation ofjbsrinstructions tobsr. This is always enabled (and-mno-force2bsris ignored) for CK801/CK802 targets. It's also always enabled when-mbranch-stubis in effect.-jsri2bsr/-mjsri2bsr/-no-jsri2bsr/-mno-jsri2bsr— enable/disable transformation ofjsriinstructions tobsr. Enabled by default, slay.-mnolrw/-mno-lrw— enable/disable transformation oflrwinstructions into amovih/oripair.-melrw/-mno-elrw— enable/disable extendedlrwinstructions. Enabled by default for CK800-series processors.-mlaf/-mliterals-after-func/-mno-laf/-mno-literals-after-func— enable/disable placement of literal pools after each function.-mlabr/-mliterals-after-br/-mno-labr/-mnoliterals-after-br— enable/disable placement of literal pools after unconditional branches. Enabled by default.-mistack/-mno-istack— enable/disable interrupt stack instructions. Enabled by default on CK801, CK802, and CK802 processors. (That's literally what the page says — CK802 twice, iconic of it 💀)
The following options explicitly enable certain optional instructions. These features are also enabled implicitly by using -mcpu= to specify a processor that supports it. iykyk:
-mhard-float— enable hard float instructions.-mmp— enable multiprocessor instructions.-mcp— enable coprocessor instructions.-mcache— enable cache prefetch instruction.-msecurity— enable C-SKY security instructions.-mtrust— enable C-SKY trust instructions.-mdsp— enable DSP instructions.-medsp— enable enhanced DSP instructions.-mvdsp— enable vector DSP instructions.
🌈 Epiphany moment
These ones are available when as is configured for an Epiphany processor:
-mepiphany— specifies that both 32 and 16 bit instructions are allowed. This is the default behavior, main character energy.-mepiphany16— restricts the permitted instructions to just the 16 bit set.
🍓 H8/300, the Renesas era
@chapter H8/300 Dependent FeaturesOptions
The Renesas H8/300 version of as has one machine-dependent option:
-h-tick-hex— supportH'00style hex constants in addition to0x00style. Both aesthetics welcome 💅-mach=name— sets the H8300 machine variant. The recognized machine names are:h8300h,h8300hn,h8300s,h8300sn,h8300sxandh8300sxn.
🧚 i386, x86 bestie
These options are available when as is configured for an i386 processor:
--32/--x32/--64— select the word size, either 32 bits or 64 bits.--32implies Intel i386 architecture, while--x32and--64imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.
These options are only available with the ELF object file format, and they require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform). No shortcuts, bestie.
-n— by default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such asleal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.--divide— on SVR4-derived platforms, the character/is treated as a comment character, which means it can't be used in expressions. The--divideoption turns/into a normal character. This does not disable/at the beginning of a line starting a comment, or affect using#for starting a comment.-march=CPU[+EXTENSION...]— specifies the target processor. The assembler will issue an error message if you attempt to assemble an instruction that won't execute on the target processor. The recognized processor names are:i8086,i186,i286,i386,i486,i586,i686,pentium,pentiumpro,pentiumii,pentiumiii,pentium4,prescott,nocona,core,core2,corei7,iamcu,k6,k6_2,athlon,opteron,k8,amdfam10,bdver1,bdver2,bdver3,bdver4,znver1,znver2,znver3,znver4,znver5,znver6,btver1,btver2,generic32andgeneric64. That's the whole roster, no cap 🔥
okay so, plot twist — on top of the basic instruction set, the assembler can be told to accept a whole bunch of extension mnemonics. like, for example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. 💅 and the extensions it supports rn are — deep breath, bestie — 8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, lahf_sahf, monitor, adx, rdseed, prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq, prefetchwt1, clflushopt, se1, clwb, movdiri, movdir64b, enqcmd, serialize, tsxldtrk, kl, widekl, hreset, avx512f, avx512cd, avx512er, avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx512_vp2intersect, tdx, avx512_bf16, avx_vnni, avx512_fp16, avx512_bmm, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb, avx10.1, avx10.1/512, avx10.1/256, avx10.1/128, user_msr, msr_imm, apx_f, apx_nci, apx_ndd, apx_nf, apx_nci_ndd_nf, avx10.2, avx10.2/512, avx10.2/256, avx10.2/128, movrs, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8 amx_movrs, amx_avx512, amx_tile, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, movbe, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, mwaitx, clzero, wbnoinvd, pconfig, waitpkg, uintr, cldemote, rdpru, mcommit, sev_es, lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, snp, invlpgb, tlbsync, rmpquery, rmpread, svme, gmism2, gmiccs, padlockrng2, padlockphe2, padlockxmodx and padlock. that's the whole squad, no cap. 🌈
okay so important note: these extension mnemonics can be prefixed with no to revoke the respective (and any dependent) functionality. like, cancel culture but for CPU features. and ANOTHER note — the suffixes permitted on -march=avx10.<N> enforce a vector length restriction. which is lowkey wild: despite these otherwise being "enabling" options, using these suffixes will disable all insns with wider vector or mask register operands. it's giving "yes but actually no". 💀
and one more thing, bestie: when the .arch directive is used with -march, the .arch directive will take precedent. periodt.
-mtune=CPU— this one specifies a processor to optimize for 🎯. when it's used in conjunction with the-marchoption, only instructions of the processor specified by the-marchoption will be generated. valid CPU values are identical to the processor list of-march=CPU.-moperand-check=none,-moperand-check=warning,-moperand-check=error— these control whether the assembler checks certain instruction operands or operand combinations. example: an instruction where operand size cannot be inferred from its operands and also hasn't been specified by way of an instruction suffix.-moperand-check=nonemakes the assembler not perform these checks.-moperand-check=warningmakes it issue a warning when respective checks fail — and that's the default ✨.-moperand-check=errormakes it issue an error when respective checks fail.-msse2avx— tells the assembler to encode SSE instructions with VEX prefix, requiring AVX to be available 🦋. SSE instructions using extended GPRs will be encoded with EVEX prefix, requiring AVX512 or AVX10 to be available.-muse-unaligned-vector-move— tells the assembler to encode aligned vector move as unaligned vector move. sneaky but valid 💅.-msse-check=none,-msse-check=warning,-msse-check=error— control whether the assembler checks SSE instructions.-msse-check=nonemakes the assembler not check SSE instructions, which is the default.-msse-check=warningmakes it issue a warning for any SSE instruction 🫶.-msse-check=errormakes it issue an error for any SSE instruction.-mavxscalar=128,-mavxscalar=256— control how the assembler should encode scalar AVX instructions.-mavxscalar=128encodes scalar AVX instructions with 128bit vector length, which is the default.-mavxscalar=256encodes scalar AVX instructions with 256bit vector length.
⚠️ WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models. like, fr fr, do not ship this 😭
-mvexwig=0,-mvexwig=1— control how the assembler encodes VEX.W-ignored (WIG) VEX instructions.-mvexwig=0encodes WIG VEX instructions withvex.w = 0, which is the default.-mvexwig=1encodes WIG EVEX instructions withvex.w = 1.
⚠️ WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models. same warning, same energy, still do not ship it 💀
-mevexlig=128,-mevexlig=256,-mevexlig=512— control how the assembler encodes length-ignored (LIG) EVEX instructions.-mevexlig=128encodes LIG EVEX instructions with 128bit vector length, which is the default.-mevexlig=256and-mevexlig=512encode LIG EVEX instructions with 256bit and 512bit vector length, respectively.-mevexwig=0,-mevexwig=1— control how the assembler encodes w-ignored (WIG) EVEX instructions.-mevexwig=0encodes WIG EVEX instructions withevex.w = 0, which is the default.-mevexwig=1encodes WIG EVEX instructions withevex.w = 1.-mmnemonic=att,-mmnemonic=intel— specifies instruction mnemonic for matching instructions 🎀. heads up: the.att_mnemonicand.intel_mnemonicdirectives will take precedent.-msyntax=att,-msyntax=intel— specifies instruction syntax when processing instructions ✨. again, the.att_syntaxand.intel_syntaxdirectives will take precedent.-mnaked-reg— specifies that registers don't require a%prefix. the.att_syntaxand.intel_syntaxdirectives will take precedent. naked registers, iconic honestly 🫣-madd-bnd-prefix— forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in the source code. it's giving "I'm helping" 😌-mno-shared— on ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. the-msharedoption tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. the resulting code is slightly bigger. this option only affects the handling of branch instructions.-mbig-obj— on PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. big object energy 🔥-momit-lock-prefix=no,-momit-lock-prefix=yes— control how the assembler should encode lock prefix. this option is intended as a workaround for processors that fail on lock prefix.
🚨 this option can only be safely used with single-core, single-thread computers. like, only. don't be out here on a 64-thread machine thinking it's fine.
-momit-lock-prefix=yes will omit all lock prefixes. -momit-lock-prefix=no will encode lock prefix as usual, which is the default.
-mfence-as-lock-add=no,-mfence-as-lock-add=yes— control how the assembler should encodelfence,mfenceandsfence.-mfence-as-lock-add=yeswill encodelfence,mfenceandsfenceaslock addl $0x0, (%rsp)in 64-bit mode andlock addl $0x0, (%esp)in 32-bit mode.-mfence-as-lock-add=nowill encodelfence,mfenceandsfenceas usual, which is the default. so extra, but valid 💅-mrelax-relocations=no,-mrelax-relocations=yes— control whether the assembler should generate relax relocations,R_386_GOT32X, in 32-bit mode, orR_X86_64_GOTPCRELXandR_X86_64_REX_GOTPCRELX, in 64-bit mode.-mrelax-relocations=yeswill generate relax relocations.-mrelax-relocations=nowill not generate relax relocations.-mtls-check=no,-mtls-check=yes— control whether the assembler checks tls relocation 👀.-mtls-check=yeswill check tls relocation.-mtls-check=nowill not check tls relocation. the default can be controlled by a configure option--enable-x86-tls-check.-malign-branch-boundary=NUM— controls how the assembler should align branches with segment prefixes or NOP.NUMmust be a power of 2. it should be 0 or no less than 16. branches will be aligned withinNUMbyte boundary.-malign-branch-boundary=0, which is the default, doesn't align branches.-malign-branch=TYPE[+TYPE...]— specifies types of branches to align.TYPEis a combination ofjcc, which aligns conditional jumps,fused, which aligns fused conditional jumps,jmp, which aligns unconditional jumps,callwhich aligns calls,ret, which aligns rets,indirect, which aligns indirect jumps and calls. the default is-malign-branch=jcc+fused+jmp.-malign-branch-prefix-size=NUM— specifies the maximum number of prefixes on an instruction to align branches.NUMshould be between 0 and 5. the defaultNUMis 5.-mbranches-within-32B-boundaries— aligns conditional jumps, fused conditional jumps and unconditional jumps within 32 byte boundary with up to 5 segment prefixes on an instruction. it is equivalent to-malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5. the default doesn't align branches. one flag, three flags' worth of chaos 😅-mlfence-after-load=no,-mlfence-after-load=yes— control whether the assembler should generatelfenceafter load instructions.-mlfence-after-load=yeswill generatelfence.-mlfence-after-load=nowill not generatelfence, which is the default. 🎀-mlfence-before-indirect-branch=none,-mlfence-before-indirect-branch=all,-mlfence-before-indirect-branch=register,-mlfence-before-indirect-branch=memory— ok so these control whether the assembler generates anlfencebefore indirect near branch instructions ✨ the deets:-mlfence-before-indirect-branch=all— generateslfencebefore indirect near branch via register, and issues a warning before indirect near branch via memory 🫶 it also implicitly sets-mlfence-before-ret=shlwhen there's no explicit-mlfence-before-ret=hanging around.-mlfence-before-indirect-branch=register— generateslfencebefore indirect near branch via register 💅-mlfence-before-indirect-branch=memory— issues a warning before indirect near branch via memory ⭐-mlfence-before-indirect-branch=none— generates nolfenceand issues no warning. this is the default 🎀
heads up bestie:lfencewon't be generated before indirect near branch via register when you've got-mlfence-after-load=yes, because thelfencegets generated after loading the branch target register instead. iykyk 💜
-mlfence-before-ret=none,-mlfence-before-ret=shl,-mlfence-before-ret=or,-mlfence-before-ret=yes,-mlfence-before-ret=not— same energy but forret🌸 do we generate anlfencebefore it or not:-mlfence-before-ret=or— generates anorinstruction withlfence🔥-mlfence-before-ret=shl/-mlfence-before-ret=yes— generates ashlinstruction withlfence✨-mlfence-before-ret=not— generates anotinstruction withlfence💫-mlfence-before-ret=none— generates nolfence. this one's the default 🎀
-mx86-used-note=no,-mx86-used-note=yes— should the assembler generateGNU_PROPERTY_X86_ISA_1_USEDandGNU_PROPERTY_X86_FEATURE_2_USEDGNU property notes? that's the vibe check 👑 and ngl the default here can be controlled by the--enable-x86-used-noteconfigure option.-mevexrcig=rne,-mevexrcig=rd,-mevexrcig=ru,-mevexrcig=rz— how should the assembler encode SAE-only EVEX instructions, hmm? 🦋-mevexrcig=rne— encodes the RC bits of the EVEX instruction with00. this is the default 💖-mevexrcig=rd— encodes SAE-only EVEX instructions with01RC bits.-mevexrcig=ru— encodes SAE-only EVEX instructions with10RC bits.-mevexrcig=rz— encodes SAE-only EVEX instructions with11RC bits.
-mamd64,-mintel64— says the assembler should accept only AMD64 or Intel64 ISA in 64-bit mode 🙈 the default is to accept common, Intel64 only and AMD64 ISAs (so like, everything, chill).-O0|-O|-O1|-O2|-Os— optimize instruction encoding for a smaller instruction size, periodt 💅-Oand-O1— encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates; encode 64-bit register clearing instructions with 32-bit register clearing instructions; encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions; encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions; and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical. ate, no crumbs 🔥-O2— includes-O1optimization plus encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions ✨ also, in 64-bit mode, VEX encoded instructions with commutative source operands will have their source operands swapped if that lets them use the 2-byte VEX prefix form instead of the 3-byte one 👀 and certain forms ofANDas well asORwith the same (register) operand specified twice will also be changed toTEST.-Os— includes-O2optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate 🎀-O0— turns off this optimization. back to basics bestie 😌
🌈 The following options are available when as is configured for the Ubicom IP2K series.
-mip2022ext— specifies that the extended IP2022 instructions are allowed 💫-mip2022— restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones 🫶
🍓 The following options are available when as is configured for the Renesas M32C and M16C processors.
-m32c— assemble M32C instructions.-m16c— assemble M16C instructions (the default) 💖-relax— enable support for link-time relaxations ✨-h-tick-hex— supportH'00style hex constants in addition to0x00style 👑
🦋 The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series.
--m32rx— specify which processor in the M32R family is the target 🌸 the default is normally the M32R, but this option changes it to the M32RX.--warn-explicit-parallel-conflictsor--Wp— produce warning messages when questionable parallel constructs are encountered 😭--no-warn-explicit-parallel-conflictsor--Wnp— do not produce warning messages when questionable parallel constructs are encountered 🙈
💜 The following options are available when as is configured for the Motorola 68000 series.
-l— shorten references to undefined symbols, to one word instead of two.-m68000|-m68008|-m68010|-m68020|-m68030|-m68040|-m68060|-m68302|-m68331|-m68332|-m68333|-m68340|-mcpu32|-m5200— specify what processor in the 68000 family is the target 🔥 the default is normally the68020, but this can be changed at configuration time.-m68881|-m68882|-mno-68881|-mno-68882— the target machine does (or does not) have a floating-point coprocessor 💅 the default is to assume a coprocessor for 68020, 68030, and cpu32. and like, even though the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor 🤯 iconic.-m68851|-mno-68851— the target machine does (or does not) have a memory-management unit coprocessor 🫶 the default is to assume an MMU for 68020 and up.
For details about the PDP-11 machine dependent features options, see PDP-11-Options 📖
-mpic|-mno-pic— generate position-independent (or position-dependent) code ✨ the default is-mpic.-mall,-mall-extensions— enable all instruction set extensions 🔥 this is the default.-mno-extensions— disable all instruction set extensions 💀-mextension|-mno-extension— enable (or disable) a particular instruction set extension 🎀-mcpu— enable the instruction set extensions supported by a particular CPU, and disable all other extensions 👑-mmachine— enable the instruction set extensions supported by a particular machine model, and disable all other extensions 🌟
🌸 The following options are available when as is configured for a picoJava processor.
-mb— generate "big endian" format output.-ml— generate "little endian" format output 🌈
🧚 The following options are available when as is configured for a PRU processor.
-mlink-relax— assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression 🫶 if they're all zeros, then LD would shorten the LDI32 instruction to a single LDI. in such caseaswill output DIFF relocations for diff expressions ✨-mno-link-relax— assume that LD would not optimize LDI32 instructions 😌 as a consequence, DIFF relocations will not be emitted.-mno-warn-regname-label— do not warn if a label name matches a register name 🙈 usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off.-mcore-revision=revision— specifies the PRU core revision to assemble for 💅 the following revisions are recognized:"V1","V2","V3"and"V4". the assembler defaults to"V3"🎀
👑 The following options are available when as is configured for a MIPS processor.
-G num— sets the largest size of an object that can be referenced implicitly with thegpregister 🌟 it's only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. the default value is8.-EB— generate "big endian" format output.-EL— generate "little endian" format output 🌈-mips1,-mips2,-mips3,-mips4,-mips5,-mips32,-mips32r2,-mips32r3,-mips32r5,-mips32r6,-mips64,-mips64r2,-mips64r3,-mips64r5,-mips64r6— generate code for a particular MIPS Instruction Set Architecture level 🔥 and the aliases are giving:-mips1is an alias for-march=r3000-mips2is an alias for-march=r6000-mips3is an alias for-march=r4000-mips4is an alias for-march=r8000-mips5,-mips32,-mips32r2,-mips32r3,-mips32r5,-mips32r6,-mips64,-mips64r2,-mips64r3,-mips64r5, and-mips64r6correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively 💅
-march=cpu— generate code for a particular MIPS CPU ✨-mtune=cpu— schedule and tune for a particular MIPS CPU 🎀-mfix7000|-mno-fix7000— causenops to be inserted if the read of the destination register of anmfhiormfloinstruction occurs in the following two instructions 👀-mfix-rm7000|-mno-fix-rm7000— causenops to be inserted if admultordmultuinstruction is followed by a load instruction 🫶-mfix-r5900|-mno-fix-r5900— do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer, and always schedule anopinstruction there instead 💀 the short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip 😭 not the vibe.-mdebug|-no-mdebug— cause stabs-style debugging output to go into an ECOFF-style.mdebugsection instead of the standard ELF.stabssections ✨-mpdr|-mno-pdr— control generation of.pdrsections 🎀-mgp32|-mfp32— the register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times 🌸-mgp32controls the size of general-purpose registers and-mfp32controls the size of floating-point registers 💖-mgp64,-mfp64— so normally your register sizes are just inferred from the ISA and ABI, right? But these flags force a certain group of registers to be treated as 64 bits wide at all times.-mgp64controls the size of general-purpose registers, and-mfp64controls the size of floating-point registers. 💅-mfpxx— register sizes are normally inferred from the ISA and ABI, but using this flag in combination with-mabi=32enables an ABI variant that will operate correctly with floating-point registers that are 32 or 64 bits wide. flexible queen behavior ✨-modd-spreg,-mno-odd-spreg— enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA.-mfpxximplies-mno-odd-spreg, otherwise the default is-modd-spreg. odd numbers stay booked and busy 🎀-mips16,-no-mips16— generate code for the MIPS 16 processor. This is equivalent to putting.module mips16at the start of the assembly file.-no-mips16turns off this option.-mmips16e2,-mno-mips16e2— enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting.module mips16e2at the start of the assembly file.-mno-mips16e2turns off this option.-mmicromips,-mno-micromips— generate code for the microMIPS processor. This is equivalent to putting.module micromipsat the start of the assembly file.-mno-micromipsturns off this option. This is equivalent to putting.module nomicromipsat the start of the assembly file.-msmartmips,-mno-smartmips— enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting.module smartmipsat the start of the assembly file.-mno-smartmipsturns off this option.-mips3d,-no-mips3d— generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions.-no-mips3dturns off this option.-mdmx,-no-mdmx— generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions.-no-mdmxturns off this option.-mdsp,-mno-dsp— generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions.-mno-dspturns off this option.-mdspr2,-mno-dspr2— generate code for the DSP Release 2 Application Specific Extension. This option implies-mdsp. This tells the assembler to accept DSP Release 2 instructions.-mno-dspr2turns off this option.-mdspr3,-mno-dspr3— generate code for the DSP Release 3 Application Specific Extension. This option implies-mdspand-mdspr2. This tells the assembler to accept DSP Release 3 instructions.-mno-dspr3turns off this option.-mmsa,-mno-msa— generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions.-mno-msaturns off this option.-mxpa,-mno-xpa— generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions.-mno-xpaturns off this option.-mmt,-mno-mt— generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions.-mno-mtturns off this option.-mmcu,-mno-mcu— generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions.-mno-mcuturns off this option.-mcrc,-mno-crc— generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. This tells the assembler to accept CRC instructions.-mno-crcturns off this option.-mginv,-mno-ginv— generate code for the Global INValidate (GINV) Application Specific Extension. This tells the assembler to accept GINV instructions.-mno-ginvturns off this option.-mloongson-mmi,-mno-loongson-mmi— generate code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. This tells the assembler to accept MMI instructions.-mno-loongson-mmiturns off this option.-mloongson-cam,-mno-loongson-cam— generate code for the Loongson Content Address Memory (CAM) instructions. This tells the assembler to accept Loongson CAM instructions.-mno-loongson-camturns off this option.-mloongson-ext,-mno-loongson-ext— generate code for the Loongson EXTensions (EXT) instructions. This tells the assembler to accept Loongson EXT instructions.-mno-loongson-extturns off this option.-mloongson-ext2,-mno-loongson-ext2— generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies-mloongson-ext. This tells the assembler to accept Loongson EXT2 instructions.-mno-loongson-ext2turns off this option.-minsn32,-mno-insn32— only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions. This is equivalent to putting.set insn32at the start of the assembly file.-mno-insn32turns off this option. This is equivalent to putting.set noinsn32at the start of the assembly file. By default-mno-insn32is selected, allowing all instructions to be used. no tiny encodings allowed, we're going full size 💀--construct-floats,--no-construct-floats— the--no-construct-floatsoption disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default--construct-floatsis selected, allowing construction of these floating point constants.--relax-branch,--no-relax-branch— the--relax-branchoption enables the relaxation of out-of-range branches. By default--no-relax-branchis selected, causing any out-of-range branches to produce an error. bestie the default is strict, okurrr 😭-mignore-branch-isa,-mno-ignore-branch-isa— ignore branch checks for invalid transitions between ISA modes. The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. Therefore GAS has checks implemented that verify in branch assembly that the two ISA modes match.-mignore-branch-isadisables these checks. By default-mno-ignore-branch-isais selected, causing any invalid branch requiring a transition between ISA modes to produce an error. the vibe check is ON by default 🔥-mnan=encoding— select between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format. The latter is the default.--emulation=name— ok so history lesson 🫶 this option was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. It is retained for backwards compatibility.
The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferred options instead.
-nocpp—asignores this option. It is accepted for compatibility with the native tools. literally just vibing in the parser, doing nothing 🦋--trap,--no-trap,--break,--no-break— control how to deal with multiplication overflow and division by zero.--trapor--no-break(which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher);--breakor--no-trap(also synonyms, and the default) take a break exception.-n— when this option is used,aswill issue a warning every time it generates anopinstruction from a macro. not me getting called out every single time I emit a nop 🙈
🌸 when as is configured for a LoongArch processor 🌸
The following options are available when as is configured for a LoongArch processor.
-fpic,-fPIC— generate position-independent code-fno-pic— don't generate position-independent code (default)
🧚 when as is configured for a Meta processor 🧚
The following options are available when as is configured for a Meta processor.
"-mcpu=metac11"— generate code for Meta 1.1."-mcpu=metac12"— generate code for Meta 1.2."-mcpu=metac21"— generate code for Meta 2.1."-mfpu=metac21"— allow code to use FPU hardware of Meta 2.1.
See the info pages for documentation of the MMIX-specific options. (yes, that's the whole MMIX situation, go read the info pages bestie 💜)
👑 when as is configured for a NDS32 processor 👑
The following options are available when as is configured for a NDS32 processor.
"-O1"— optimize for performance."-Os"— optimize for space."-EL"— produce little endian data output."-EB"— produce little endian data output.
not me side-eying -EB saying "little endian" too 👀 that is exactly what the page says, so I'm passing it along verbatim, no edits, no notes. take it up with the docs, bestie.
"-mpic"— generate PIC."-mno-fp-as-gp-relax"— suppress fp-as-gp relaxation for this file."-mb2bb-relax"— back-to-back branch optimization."-mno-all-relax"— suppress all relaxation for this file."-march=<arch name>"— assemble for architecture <arch name> which could bev3,v3j,v3m,v3f,v3s,v2,v2j,v2f,v2s."-mbaseline=<baseline>"— assemble for baseline <baseline> which could bev2,v3,v3m."-mfpu-freg=FREG"— specify a FPU configuration.
"0 8 SP / 4 DP registers"
"1 16 SP / 8 DP registers"
"2 32 SP / 16 DP registers"
"3 32 SP / 32 DP registers""-mabi=abi"— specify a abi version <abi> could bev1,v2,v2fp,v2fpp."-m[no-]mac"— enable/disable Multiply instructions support."-m[no-]div"— enable/disable Divide instructions support."-m[no-]16bit-ext"— enable/disable 16-bit extension"-m[no-]dx-regs"— enable/disable d0/d1 registers"-m[no-]perf-ext"— enable/disable Performance extension"-m[no-]perf2-ext"— enable/disable Performance extension 2"-m[no-]string-ext"— enable/disable String extension"-m[no-]reduced-regs"— enable/disable Reduced Register configuration (GPR16) option"-m[no-]audio-isa-ext"— enable/disable AUDIO ISA extension"-m[no-]fpu-sp-ext"— enable/disable FPU SP extension"-m[no-]fpu-dp-ext"— enable/disable FPU DP extension"-m[no-]fpu-fma"— enable/disable FPU fused-multiply-add instructions"-mall-ext"— turn on all extensions and instructions support. the "give me everything on the menu" option, iconic 🌈
⭐ when as is configured for a PowerPC processor ⭐
The following options are available when as is configured for a PowerPC processor.
-a32— generate ELF32 or XCOFF32.-a64— generate ELF64 or XCOFF64.-K PIC— setsEF_PPC_RELOCATABLE_LIBin the ELF flags. yes bestie it's literally one job and it does it 💅-mpwrx,-mpwr2— generate code for POWER/2 (RIOS2). 🦋-mpwr— generate code for POWER (RIOS1).-m601— generate code for PowerPC 601.-mppc,-mppc32,-m603,-m604— generate code for PowerPC 603/604.-m403,-m405— generate code for PowerPC 403/405.-m440— generate code for PowerPC 440. BookE and some 405 instructions, iykyk.-m464— generate code for PowerPC 464.-m476— generate code for PowerPC 476.-m7400,-m7410,-m7450,-m7455— generate code for PowerPC 7400/7410/7450/7455.-m750cl,-mgekko,-mbroadway— generate code for PowerPC 750CL/Gekko/Broadway.-m821,-m850,-m860— generate code for PowerPC 821/850/860.-mppc64,-m620— generate code for PowerPC 620/625/630.-me200z2,-me200z4— generate code for e200 variants:e200z2with LSP,e200z4with SPE.-me300— generate code for the PowerPC e300 family. 👑-me500,-me500x2— generate code for the Motorola e500 core complex.-me500mc— generate code for the Freescale e500mc core complex.-me500mc64— generate code for the Freescale e500mc64 core complex.-me5500— generate code for the Freescale e5500 core complex.-me6500— generate code for the Freescale e6500 core complex.-mlsp— enable LSP instructions. (Disables SPE and SPE2 — it's giving "choose your fighter" 😭)-mspe— generate code for Motorola SPE instructions. (Disables LSP.)-mspe2— generate code for Freescale SPE2 instructions. (Disables LSP.)-mtitan— generate code for the AppliedMicro Titan core complex.-mppc64bridge— generate code for PowerPC 64, including bridge insns.-mbooke— generate code for 32-bit BookE.-ma2— generate code for the A2 architecture.-maltivec— generate code for processors with AltiVec instructions. ✨-mvle— generate code for Freescale PowerPC VLE instructions.-mvsx— generate code for processors with Vector-Scalar (VSX) instructions.-mhtm— generate code for processors with Hardware Transactional Memory instructions.-mpower4,-mpwr4— generate code for the Power4 architecture.-mpower5,-mpwr5,-mpwr5x— generate code for the Power5 architecture.-mpower6,-mpwr6— generate code for the Power6 architecture.-mpower7,-mpwr7— generate code for the Power7 architecture.-mpower8,-mpwr8— generate code for the Power8 architecture.-mpower9,-mpwr9— generate code for the Power9 architecture.-mpower10,-mpwr10— generate code for the Power10 architecture.-mpower11,-mpwr11— generate code for the Power11 architecture.-mfuture— generate code for the'future'architecture. she's ahead of her time, literally 🫶-mcell,-mcell— generate code for the Cell Broadband Engine architecture. (yes, the original lists it twice — iconic of it, honestly 🎀)-mcom— generate code for Power/PowerPC common instructions.-many— generate code for any architecture (PWR/PWRX/PPC). no thoughts, just range 🌈-mregnames— allow symbolic names for registers.-mno-regnames— do not allow symbolic names for registers.-mrelocatable— support for GCC's-mrelocatableoption.-mrelocatable-lib— support for GCC's-mrelocatable-liboption.-memb— set thePPC_EMBbit in ELF flags.-mlittle,-mlittle-endian,-le— generate code for a little endian machine.-mbig,-mbig-endian,-be— generate code for a big endian machine. big endian stans rise 🙈-nops=count— if an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops. efficiency queen 💅
So! The next batch of options is available when as is configured for a RISC-V processor. slay, let's go 🧚
-fpic,-fPIC— generate position-independent code.-fno-pic— don't generate position-independent code (this one's the default).-march=ISA|Profiles|Profiles_ISA— select the base isa, as specified by ISA or Profiles or Profies_ISA. (yes, that's spelledProfies_ISAin the source, we don't edit, we respect 🫡) For example-march=rv32ima -march=RVI20U64 -march=RVI20U64_d. If this option and the architecture attributes aren't set, then the assembler will check the default configure setting--with-arch=ISA.-misa-spec=ISAspec— select the default isa spec version. If the version of ISA isn't set by-march, then the assembler helps to set the version according to the default chosen spec. If this option isn't set, then the assembler will check the default configure setting--with-isa-spec=ISAspec.-mpriv-spec=PRIVspec— select the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren't set, then the assembler will check the default configure setting--with-priv-spec=PRIVspec.-mabi=ABI— selects the ABI, which is either"ilp32"or"lp64", optionally followed by"f","d", or"q"to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or"e"to indicate the soft-float calling convention ("e"indicates a soft-float RVE ABI). so many letters, all of them valid, we love a flexible queen 💖-mrelax— take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default — yes bestie, it's already on)-mno-relax— don't do linker relaxations.-march-attr— generate the default contents for the riscv elf attribute section if the.attributedirectives are not set. This section is used to record the information that a linker or runtime loader needs to check compatibility. This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification.-mno-arch-attr— don't generate the default riscv elf attribute section if the.attributedirectives are not set.-mcsr-check— enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions. (no cap, read-only means read-only 🔥)-mno-csr-check— don't do CSR checking.-mlittle-endian— generate code for a little endian machine.-mbig-endian— generate code for a big endian machine.
Head's up bestie: for documentation of the RX-specific options, see the info pages. 📖
Next up, the options available when as is configured for the s390 processor family. z/Architecture girlies wya 🎀
-m31,-m64— select the word size, either 31/32 bits or 64 bits.-mesa,-mzarch— select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).-march=processor— specify which s390 processor variant is the target:g5(orarch3),g6,z900(orarch5),z990(orarch6),z9-109,z9-ec(orarch7),z10(orarch8),z196(orarch9),zEC12(orarch10),z13(orarch11),z14(orarch12),z15(orarch13),z16(orarch14), orz17(orarch15). that's a whole rollout, she's got lore 😭-mregnames,-mno-regnames— allow or disallow symbolic names for registers.-mwarn-areg-zero— warn whenever the operand for a base or index register has been specified but evaluates to zero.-mwarn-regtype-mismatch=strict,-mwarn-regtype-mismatch=relaxed,-mwarn-regtype-mismatch=no,-mno-warn-regtype-mismatch— controls whether the assembler performs register name type checks and generates a warning message in case of a mismatch with the operand register type.
The default (which can be restored by using the relaxed argument) is to perform relaxed register name type checks, which allow floating point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating point register (FPR) operands. This is acceptable as the FPR are embedded into the lower half of the VR.
Using the strict argument, strict register name type checks are performed. The no argument, which is equivalent to -mno-warn-regtype-mismatch, disables any register name type checks. choose your vibe wisely bestie 💅
And now, the options available when as is configured for a TMS320C6000 processor. DSP besties we see you 🦋
-march=arch— enable (only) instructions from architecture arch. By default, all instructions are permitted.
The following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x".
-mdsbt,-mno-dsbt— the-mdsbtoption causes the assembler to generate the"Tag_ABI_DSBT"attribute with a value of1, indicating that the code is using DSBT addressing. The-mno-dsbtoption, the default, causes the tag to have a value of0, indicating that the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. ⚠️-mpid=no,-mpid=near,-mpid=far— the-mpid=option causes the assembler to generate the"Tag_ABI_PID"attribute with a value indicating the form of data addressing used by the code.-mpid=no, the default, indicates position-dependent data addressing.-mpid=nearindicates position-independent addressing with GOT accesses using near DP addressing.-mpid=farindicates position-independent addressing with GOT accesses using far DP addressing.
The linker will emit a warning if objects built with different settings of this option are linked together. yeah, mixing them is a whole situation 💀
-mpic,-mno-pic— the-mpicoption causes the assembler to generate the"Tag_ABI_PIC"attribute with a value of1, indicating that the code is using position-independent code addressing. The"-mno-pic"option, the default, causes the tag to have a value of0, indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together.-mbig-endian,-mlittle-endian— generate code for the specified endianness. The default is little-endian.
Then, options available when as is configured for a TILE-Gx processor. short list, main character energy ✨
-m32|-m64— select the word size, either 32 bits or 64 bits.-EB|-EL— select the endianness, either big-endian (-EB) or little-endian (-EL).
The following option is available when as is configured for a Visium processor. just one flag, she's lowkey mysterious 🎀
-mtune=arch— this option specifies the target architecture. If an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. 🚨
The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
The following options are available when as is configured for an Xtensa processor. 👀 (coming right up…)
--text-section-literals,--no-text-section-literals— okay so this is the literal-pool vibe check 💅. The default is--no-text-section-literals, which puts literals in separate sections in the output file so the literal pool can be placed in adata RAM/ROM. With--text-section-literals, the literals are interspersed in the text section to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of theL32Rinstructions in the text section. Literals are grouped into pools following.literal_positiondirectives or precedingENTRYinstructions. These options only affect literals referenced via PC-relativeL32Rinstructions; literals for absolute modeL32Rinstructions are handled separately.--auto-litpools,--no-auto-litpools— another literal-pool control, bestie ✨. The default is--no-auto-litpools, which in the absence of--text-section-literalsplaces literals in separate sections in the output file, letting the literal pool go in adata RAM/ROM. With--auto-litpools, the literals are interspersed in the text section to keep them as close as possible to their references, and explicit.literal_positiondirectives are not required. This may be necessary for very large functions, where a single literal pool at the beginning of the function may not be reachable byL32Rinstructions at the end. These options only affect literals referenced via PC-relativeL32Rinstructions; literals for absolute modeL32Rinstructions are handled separately. When used together with--text-section-literals,--auto-litpoolstakes precedence 👑.--absolute-literals,--no-absolute-literals— tells the assembler whetherL32Rinstructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absoluteL32Rrelocations. Otherwise, only the PC-relativeL32Rrelocations can be used.--target-align,--no-target-align— turns automatic alignment on or off to reduce branch penalties at some expense in code size. This optimization is enabled by default. Note that the assembler will always align instructions likeLOOPthat have fixed alignment requirements.--longcalls,--no-longcalls— turns transformation of call instructions on or off so calls can reach across a greater range of addresses. This option should be used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. The default is--no-longcalls.--transform,--no-transform— turns all assembler transformations of Xtensa instructions on or off, including both relaxation and optimization. The default is--transform;--no-transformshould only be used in the rare cases when the instructions must be exactly as specified in the assembly source. Using--no-transformcauses out of range instruction operands to be errors 😭.--rename-section oldname=newname— renames theoldnamesection tonewname. This option can be used multiple times to rename multiple sections.--trampolines,--no-trampolines— turns transformation of jump instructions on or off so jumps can reach across a greater range of addresses. This option should be used when jump targets can potentially be out of range. In the absence of such jumps this option does not affect code size or performance. The default is--trampolines.--abi-windowed,--abi-call0— chooses the ABI tag written to the.xtensa.infosection. The ABI tag indicates the ABI of the assembly code. A warning is issued by the linker on an attempt to link object files with inconsistent ABI tags. Default ABI is chosen by the Xtensa core configuration.
🎮 Z80 Dependent Features
The following options are available when as is configured for an Z80 processor.
@chapter Z80 Dependent Features
🎛️ Command-line Options
-march=CPU[-EXT...][+EXT...]— this specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized:z80,z180,ez80,gbz80,z80n,r800. In addition to the basic instruction set, the assembler can be told to accept some extension mnemonics. For example,-march=z180+sli+infcextendsz180with SLI instructions andIN F,(C). The following extensions are currently supported:full— all known instructionsadl— ADL CPU mode by default, eZ80 onlysli— instruction known as SLI, SLL or SL1xyhl— instructions with halves of index registers: IXL, IXH, IYL, IYHxdcb— instructions likeRotOp (II+d),RandBitOp n,(II+d),Rinfc— instructionIN F,(C)orIN (C)outc0— instructionOUT (C),0
Note that rather than extending a basic instruction set, the extension mnemonics starting with - revoke the respective functionality: -march=z80-full+xyhl first removes all default extensions and adds support for index registers halves only.
If this option is not specified then -march=z80+xyhl+infc is assumed.
-local-prefix=prefix— marks all labels with the specified prefix as local. But such a label can be marked global explicitly in the code. This option does not change the default local label prefix.L; it just adds a new one.-colonless— accepts colonless labels. All symbols at line begin are treated as labels.-sdcc— accepts assembler code produced by SDCC.-fp-s=FORMAT— single precision floating point numbers format. Default:ieee754(32 bit).-fp-d=FORMAT— double precision floating point numbers format. Default:ieee754(64 bit).
🌈 SEE ALSO
gcc(1), ld(1), and the Info entries for binutils and ld.
👑 COPYRIGHT
Copyright (c) 1991-2026 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled “GNU Free Documentation License”.
okay bye bestie — page AS(1) from binutils-2.47, dated 2026-07-30 💖✨
📦 where this page comes from
- arch rolling: aarch64-linux-gnu-binutils 2.47-1 · GPL
- 💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms